^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Toshiba PCI Secure Digital Host Controller Interface driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Ondrej Zary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007 Richard Betts, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on asic3_mmc.c, copyright (c) 2005 SDG Systems, LLC and,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * sdhci.c, copyright (C) 2005-2006 Pierre Ossman
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "toshsd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRIVER_NAME "toshsd"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const struct pci_device_id pci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA, 0x0805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { /* end: all zeroes */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_DEVICE_TABLE(pci, pci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void toshsd_init(struct toshsd_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* enable clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) pci_write_config_byte(host->pdev, SD_PCICFG_CLKSTOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SD_PCICFG_CLKSTOP_ENABLE_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) pci_write_config_byte(host->pdev, SD_PCICFG_CARDDETECT, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) iowrite16(0, host->ioaddr + SD_SOFTWARERESET); /* assert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) iowrite16(1, host->ioaddr + SD_SOFTWARERESET); /* deassert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Clear card registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) iowrite32(0, host->ioaddr + SD_CARDSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) iowrite32(0, host->ioaddr + SD_ERRORSTATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) iowrite16(0, host->ioaddr + SD_STOPINTERNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* SDIO clock? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) iowrite16(0x100, host->ioaddr + SDIO_BASE + SDIO_CLOCKNWAITCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* enable LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pci_write_config_byte(host->pdev, SD_PCICFG_SDLED_ENABLE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) SD_PCICFG_LED_ENABLE1_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pci_write_config_byte(host->pdev, SD_PCICFG_SDLED_ENABLE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SD_PCICFG_LED_ENABLE2_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* set interrupt masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) iowrite32(~(u32)(SD_CARD_RESP_END | SD_CARD_RW_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) | SD_CARD_CARD_REMOVED_0 | SD_CARD_CARD_INSERTED_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) | SD_BUF_READ_ENABLE | SD_BUF_WRITE_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) | SD_BUF_CMD_TIMEOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) host->ioaddr + SD_INTMASKCARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) iowrite16(0x1000, host->ioaddr + SD_TRANSACTIONCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Set MMC clock / power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Note: This controller uses a simple divider scheme therefore it cannot run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * SD/MMC cards at full speed (24/20MHz). HCLK (=33MHz PCI clock?) is too high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * and the next slowest is 16MHz (div=2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void __toshsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct toshsd_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (ios->clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u16 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) while (ios->clock < HCLK / div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) div *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) clk = div >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (div == 1) { /* disable the divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pci_write_config_byte(host->pdev, SD_PCICFG_CLKMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SD_PCICFG_CLKMODE_DIV_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clk |= SD_CARDCLK_DIV_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pci_write_config_byte(host->pdev, SD_PCICFG_CLKMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) clk |= SD_CARDCLK_ENABLE_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) iowrite16(clk, host->ioaddr + SD_CARDCLOCKCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) switch (ios->power_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case MMC_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pci_write_config_byte(host->pdev, SD_PCICFG_POWER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SD_PCICFG_PWR1_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case MMC_POWER_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case MMC_POWER_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pci_write_config_byte(host->pdev, SD_PCICFG_POWER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SD_PCICFG_PWR1_33V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pci_write_config_byte(host->pdev, SD_PCICFG_POWER2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SD_PCICFG_PWR2_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mdelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) switch (ios->bus_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case MMC_BUS_WIDTH_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) iowrite16(SD_CARDOPT_REQUIRED | SD_CARDOPT_DATA_RESP_TIMEOUT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) | SD_CARDOPT_C2_MODULE_ABSENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) | SD_CARDOPT_DATA_XFR_WIDTH_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) host->ioaddr + SD_CARDOPTIONSETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case MMC_BUS_WIDTH_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) iowrite16(SD_CARDOPT_REQUIRED | SD_CARDOPT_DATA_RESP_TIMEOUT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) | SD_CARDOPT_C2_MODULE_ABSENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) | SD_CARDOPT_DATA_XFR_WIDTH_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) host->ioaddr + SD_CARDOPTIONSETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void toshsd_set_led(struct toshsd_host *host, unsigned char state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) iowrite16(state, host->ioaddr + SDIO_BASE + SDIO_LEDCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void toshsd_finish_request(struct toshsd_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct mmc_request *mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Write something to end the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) toshsd_set_led(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static irqreturn_t toshsd_thread_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct toshsd_host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct mmc_data *data = host->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct sg_mapping_iter *sg_miter = &host->sg_miter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned short *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_warn(&host->pdev->dev, "Spurious Data IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (host->cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) host->cmd->error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) toshsd_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!sg_miter_next(sg_miter))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) buf = sg_miter->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Ensure we dont read more than one block. The chip will interrupt us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * When the next block is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) count = sg_miter->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (count > data->blksz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) count = data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_dbg(&host->pdev->dev, "count: %08x, flags %08x\n", count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) data->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Transfer the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ioread32_rep(host->ioaddr + SD_DATAPORT, buf, count >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) iowrite32_rep(host->ioaddr + SD_DATAPORT, buf, count >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) sg_miter->consumed = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sg_miter_stop(sg_miter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void toshsd_cmd_irq(struct toshsd_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct mmc_command *cmd = host->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!host->cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_warn(&host->pdev->dev, "Spurious CMD irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) buf = (u8 *)cmd->resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (cmd->flags & MMC_RSP_PRESENT && cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* R2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) buf[12] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) data = ioread16(host->ioaddr + SD_RESPONSE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) buf[13] = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) buf[14] = data >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) data = ioread16(host->ioaddr + SD_RESPONSE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) buf[15] = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) buf[8] = data >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) data = ioread16(host->ioaddr + SD_RESPONSE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) buf[9] = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) buf[10] = data >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) data = ioread16(host->ioaddr + SD_RESPONSE3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) buf[11] = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) buf[4] = data >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) data = ioread16(host->ioaddr + SD_RESPONSE4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) buf[5] = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) buf[6] = data >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) data = ioread16(host->ioaddr + SD_RESPONSE5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) buf[7] = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) buf[0] = data >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) data = ioread16(host->ioaddr + SD_RESPONSE6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) buf[1] = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) buf[2] = data >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) data = ioread16(host->ioaddr + SD_RESPONSE7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) buf[3] = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } else if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* R1, R1B, R3, R6, R7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) data = ioread16(host->ioaddr + SD_RESPONSE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) buf[0] = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) buf[1] = data >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) data = ioread16(host->ioaddr + SD_RESPONSE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) buf[2] = data & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) buf[3] = data >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_dbg(&host->pdev->dev, "Command IRQ complete %d %d %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) cmd->opcode, cmd->error, cmd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* If there is data to handle we will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * finish the request in the mmc_data_end_irq handler.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (host->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) toshsd_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void toshsd_data_end_irq(struct toshsd_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct mmc_data *data = host->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (data->error == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) data->bytes_xfered = data->blocks * data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) data->bytes_xfered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_dbg(&host->pdev->dev, "Completed data request xfr=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) data->bytes_xfered);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) iowrite16(0, host->ioaddr + SD_STOPINTERNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) toshsd_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static irqreturn_t toshsd_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct toshsd_host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 int_reg, int_mask, int_status, detail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int error = 0, ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int_status = ioread32(host->ioaddr + SD_CARDSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int_mask = ioread32(host->ioaddr + SD_INTMASKCARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int_reg = int_status & ~int_mask & ~IRQ_DONT_CARE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_dbg(&host->pdev->dev, "IRQ status:%x mask:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int_status, int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* nothing to do: it's not our IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!int_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) goto irq_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (int_reg & SD_BUF_CMD_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dev_dbg(&host->pdev->dev, "Timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } else if (int_reg & SD_BUF_CRC_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_err(&host->pdev->dev, "BadCRC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } else if (int_reg & (SD_BUF_ILLEGAL_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) | SD_BUF_CMD_INDEX_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) | SD_BUF_STOP_BIT_END_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) | SD_BUF_OVERFLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) | SD_BUF_UNDERFLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) | SD_BUF_DATA_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_err(&host->pdev->dev, "Buffer status error: { %s%s%s%s%s%s}\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int_reg & SD_BUF_ILLEGAL_ACCESS ? "ILLEGAL_ACC " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int_reg & SD_BUF_CMD_INDEX_ERR ? "CMD_INDEX " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int_reg & SD_BUF_STOP_BIT_END_ERR ? "STOPBIT_END " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int_reg & SD_BUF_OVERFLOW ? "OVERFLOW " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int_reg & SD_BUF_UNDERFLOW ? "UNDERFLOW " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int_reg & SD_BUF_DATA_TIMEOUT ? "DATA_TIMEOUT " : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) detail = ioread32(host->ioaddr + SD_ERRORSTATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_err(&host->pdev->dev, "detail error status { %s%s%s%s%s%s%s%s%s%s%s%s%s}\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) detail & SD_ERR0_RESP_CMD_ERR ? "RESP_CMD " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) detail & SD_ERR0_RESP_NON_CMD12_END_BIT_ERR ? "RESP_END_BIT " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) detail & SD_ERR0_RESP_CMD12_END_BIT_ERR ? "RESP_END_BIT " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) detail & SD_ERR0_READ_DATA_END_BIT_ERR ? "READ_DATA_END_BIT " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) detail & SD_ERR0_WRITE_CRC_STATUS_END_BIT_ERR ? "WRITE_CMD_END_BIT " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) detail & SD_ERR0_RESP_NON_CMD12_CRC_ERR ? "RESP_CRC " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) detail & SD_ERR0_RESP_CMD12_CRC_ERR ? "RESP_CRC " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) detail & SD_ERR0_READ_DATA_CRC_ERR ? "READ_DATA_CRC " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) detail & SD_ERR0_WRITE_CMD_CRC_ERR ? "WRITE_CMD_CRC " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) detail & SD_ERR1_NO_CMD_RESP ? "NO_CMD_RESP " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) detail & SD_ERR1_TIMEOUT_READ_DATA ? "READ_DATA_TIMEOUT " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) detail & SD_ERR1_TIMEOUT_CRS_STATUS ? "CRS_STATUS_TIMEOUT " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) detail & SD_ERR1_TIMEOUT_CRC_BUSY ? "CRC_BUSY_TIMEOUT " : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (host->cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) host->cmd->error = error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (error == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) iowrite32(int_status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ~(SD_BUF_CMD_TIMEOUT | SD_CARD_RESP_END),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) host->ioaddr + SD_CARDSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) toshsd_init(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) __toshsd_set_ios(host->mmc, &host->mmc->ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) goto irq_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Card insert/remove. The mmc controlling code is stateless. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (int_reg & (SD_CARD_CARD_INSERTED_0 | SD_CARD_CARD_REMOVED_0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) iowrite32(int_status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ~(SD_CARD_CARD_REMOVED_0 | SD_CARD_CARD_INSERTED_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) host->ioaddr + SD_CARDSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (int_reg & SD_CARD_CARD_INSERTED_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) toshsd_init(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mmc_detect_change(host->mmc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Data transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (int_reg & (SD_BUF_READ_ENABLE | SD_BUF_WRITE_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) iowrite32(int_status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ~(SD_BUF_WRITE_ENABLE | SD_BUF_READ_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) host->ioaddr + SD_CARDSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) goto irq_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Command completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (int_reg & SD_CARD_RESP_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) iowrite32(int_status & ~(SD_CARD_RESP_END),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) host->ioaddr + SD_CARDSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) toshsd_cmd_irq(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Data transfer completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (int_reg & SD_CARD_RW_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) iowrite32(int_status & ~(SD_CARD_RW_END),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) host->ioaddr + SD_CARDSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) toshsd_data_end_irq(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) irq_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void toshsd_start_cmd(struct toshsd_host *host, struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct mmc_data *data = host->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int c = cmd->opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev_dbg(&host->pdev->dev, "Command opcode: %d\n", cmd->opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (cmd->opcode == MMC_STOP_TRANSMISSION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) iowrite16(SD_STOPINT_ISSUE_CMD12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) host->ioaddr + SD_STOPINTERNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) cmd->resp[0] = cmd->opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) cmd->resp[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) cmd->resp[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) cmd->resp[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) toshsd_finish_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) switch (mmc_resp_type(cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case MMC_RSP_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) c |= SD_CMD_RESP_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case MMC_RSP_R1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) c |= SD_CMD_RESP_TYPE_EXT_R1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case MMC_RSP_R1B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) c |= SD_CMD_RESP_TYPE_EXT_R1B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case MMC_RSP_R2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) c |= SD_CMD_RESP_TYPE_EXT_R2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case MMC_RSP_R3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) c |= SD_CMD_RESP_TYPE_EXT_R3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_err(&host->pdev->dev, "Unknown response type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mmc_resp_type(cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) host->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (cmd->opcode == MMC_APP_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) c |= SD_CMD_TYPE_ACMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (cmd->opcode == MMC_GO_IDLE_STATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) c |= (3 << 8); /* removed from ipaq-asic3.h for some reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) c |= SD_CMD_DATA_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (data->blocks > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) iowrite16(SD_STOPINT_AUTO_ISSUE_CMD12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) host->ioaddr + SD_STOPINTERNAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) c |= SD_CMD_MULTI_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) c |= SD_CMD_TRANSFER_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* MMC_DATA_WRITE does not require a bit to be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Send the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) iowrite32(cmd->arg, host->ioaddr + SD_ARG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) iowrite16(c, host->ioaddr + SD_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static void toshsd_start_data(struct toshsd_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) unsigned int flags = SG_MITER_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_dbg(&host->pdev->dev, "setup data transfer: blocksize %08x nr_blocks %d, offset: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) data->blksz, data->blocks, data->sg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) host->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) flags |= SG_MITER_TO_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) flags |= SG_MITER_FROM_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Set transfer length and blocksize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) iowrite16(data->blocks, host->ioaddr + SD_BLOCKCOUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) iowrite16(data->blksz, host->ioaddr + SD_CARDXFERDATALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Process requests from the MMC layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void toshsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct toshsd_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* abort if card not present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (!(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_PRESENT_0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mrq->cmd->error = -ENOMEDIUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) mmc_request_done(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) WARN_ON(host->mrq != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) host->mrq = mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (mrq->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) toshsd_start_data(host, mrq->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) toshsd_set_led(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) toshsd_start_cmd(host, mrq->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static void toshsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct toshsd_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) __toshsd_set_ios(mmc, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int toshsd_get_ro(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct toshsd_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return !(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_WRITE_PROTECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int toshsd_get_cd(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct toshsd_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return !!(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_PRESENT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static const struct mmc_host_ops toshsd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .request = toshsd_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .set_ios = toshsd_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .get_ro = toshsd_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .get_cd = toshsd_get_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static void toshsd_powerdown(struct toshsd_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* mask all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) iowrite32(0xffffffff, host->ioaddr + SD_INTMASKCARD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* disable card clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) iowrite16(0x000, host->ioaddr + SDIO_BASE + SDIO_CLOCKNWAITCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* power down card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) pci_write_config_byte(host->pdev, SD_PCICFG_POWER1, SD_PCICFG_PWR1_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* disable clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) pci_write_config_byte(host->pdev, SD_PCICFG_CLKSTOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static int toshsd_pm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct toshsd_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) toshsd_powerdown(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) pci_enable_wake(pdev, PCI_D3hot, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) pci_set_power_state(pdev, PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int toshsd_pm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct toshsd_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pci_set_power_state(pdev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pci_restore_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ret = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) toshsd_init(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int toshsd_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct toshsd_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) resource_size_t base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mmc = mmc_alloc_host(sizeof(struct toshsd_host), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (!mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) host->mmc = mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) host->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) pci_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ret = pci_request_regions(pdev, DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) host->ioaddr = pci_iomap(pdev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (!host->ioaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* Set MMC host parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) mmc->ops = &toshsd_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) mmc->caps = MMC_CAP_4_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) mmc->ocr_avail = MMC_VDD_32_33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) mmc->f_min = HCLK / 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) mmc->f_max = HCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) spin_lock_init(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) toshsd_init(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ret = request_threaded_irq(pdev->irq, toshsd_irq, toshsd_thread_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) IRQF_SHARED, DRIVER_NAME, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) base = pci_resource_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dev_dbg(&pdev->dev, "MMIO %pa, IRQ %d\n", &base, pdev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) pm_suspend_ignore_children(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) pci_iounmap(pdev, host->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pci_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static void toshsd_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct toshsd_host *host = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mmc_remove_host(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) toshsd_powerdown(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) free_irq(pdev->irq, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) pci_iounmap(pdev, host->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) mmc_free_host(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) pci_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static const struct dev_pm_ops toshsd_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) SET_SYSTEM_SLEEP_PM_OPS(toshsd_pm_suspend, toshsd_pm_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static struct pci_driver toshsd_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .id_table = pci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .probe = toshsd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .remove = toshsd_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .driver.pm = &toshsd_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) module_pci_driver(toshsd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) MODULE_AUTHOR("Ondrej Zary, Richard Betts");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) MODULE_DESCRIPTION("Toshiba PCI Secure Digital Host Controller Interface driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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