^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the MMC / SD / SDIO cell found in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2015-19 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2016-17 Horms Solutions, Simon Horman
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2007 Ian Molton
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2004 Ian Molton
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef TMIO_MMC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TMIO_MMC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pagemap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CTL_SD_CMD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CTL_ARG_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CTL_STOP_INTERNAL_ACTION 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CTL_XFER_BLK_COUNT 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CTL_RESPONSE 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* driver merges STATUS and following STATUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CTL_STATUS 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* driver merges IRQ_MASK and following IRQ_MASK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CTL_IRQ_MASK 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CTL_SD_CARD_CLK_CTL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CTL_SD_XFER_LEN 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CTL_SD_MEM_CARD_OPT 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CTL_SD_ERROR_DETAIL_STATUS 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CTL_SD_DATA_PORT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CTL_TRANSACTION_CTL 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CTL_SDIO_STATUS 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CTL_SDIO_IRQ_MASK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CTL_DMA_ENABLE 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CTL_RESET_SD 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CTL_VERSION 0xe2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CTL_SDIF_MODE 0xe6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TMIO_STOP_STP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TMIO_STOP_SEC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Definitions for values the CTL_STATUS register can take */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TMIO_STAT_CMDRESPEND BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TMIO_STAT_DATAEND BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TMIO_STAT_CARD_REMOVE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TMIO_STAT_CARD_INSERT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TMIO_STAT_SIGSTATE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TMIO_STAT_WRPROTECT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TMIO_STAT_CARD_REMOVE_A BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TMIO_STAT_CARD_INSERT_A BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TMIO_STAT_SIGSTATE_A BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* These belong technically to CTL_STATUS2, but the driver merges them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TMIO_STAT_CMD_IDX_ERR BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TMIO_STAT_CRCFAIL BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TMIO_STAT_STOPBIT_ERR BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TMIO_STAT_DATATIMEOUT BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TMIO_STAT_RXOVERFLOW BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TMIO_STAT_TXUNDERRUN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TMIO_STAT_CMDTIMEOUT BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TMIO_STAT_DAT0 BIT(23) /* only known on R-Car so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TMIO_STAT_RXRDY BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TMIO_STAT_TXRQ BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TMIO_STAT_ALWAYS_SET_27 BIT(27) /* only known on R-Car 2+ so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TMIO_STAT_ILL_FUNC BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TMIO_STAT_SCLKDIVEN BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TMIO_STAT_CMD_BUSY BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TMIO_STAT_ILL_ACCESS BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Definitions for values the CTL_SD_CARD_CLK_CTL register can take */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLK_CTL_DIV_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLK_CTL_SCLKEN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Definitions for values the CTL_SD_MEM_CARD_OPT register can take */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CARD_OPT_WIDTH8 BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CARD_OPT_WIDTH BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Definitions for values the CTL_SDIO_STATUS register can take */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TMIO_SDIO_STAT_IOIRQ 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TMIO_SDIO_STAT_EXPUB52 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TMIO_SDIO_STAT_EXWT 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TMIO_SDIO_MASK_ALL 0xc007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TMIO_SDIO_SETBITS_MASK 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Definitions for values the CTL_DMA_ENABLE register can take */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DMA_ENABLE_DMASDRW BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Define some IRQ masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* This is the mask used at reset by the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TMIO_MASK_INIT_RCAR2 0x8b7f031d /* Initial value for R-Car Gen2+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TMIO_MASK_ALL 0x837f031d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TMIO_MAX_BLK_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct tmio_mmc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct tmio_mmc_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct tmio_mmc_dma_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void (*start)(struct tmio_mmc_host *host, struct mmc_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void (*enable)(struct tmio_mmc_host *host, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void (*request)(struct tmio_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct tmio_mmc_data *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void (*release)(struct tmio_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void (*abort)(struct tmio_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void (*dataend)(struct tmio_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void (*end)(struct tmio_mmc_host *host); /* held host->lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct tmio_mmc_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void __iomem *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct mmc_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct mmc_host_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Callbacks for clock / power control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void (*set_pwr)(struct platform_device *host, int state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* pio related stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct scatterlist *sg_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct scatterlist *sg_orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int sg_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int bus_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct tmio_mmc_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* DMA support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bool dma_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct dma_chan *chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct dma_chan *chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct tasklet_struct dma_issue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct scatterlist bounce_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 *bounce_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Track lost interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct delayed_work delayed_reset_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct work_struct done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 sdcard_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 sdio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int clk_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 sdcard_irq_setbit_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spinlock_t lock; /* protect host private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long last_req_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct mutex ios_lock; /* protect set_ios() context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) bool native_hotplug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bool sdio_irq_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Mandatory callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int (*clk_enable)(struct tmio_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Optional callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) void (*clk_disable)(struct tmio_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int (*multi_io_quirk)(struct mmc_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int direction, int blk_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int (*write16_hook)(struct tmio_mmc_host *host, int addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void (*reset)(struct tmio_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bool (*check_retune)(struct tmio_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void (*fixup_request)(struct tmio_mmc_host *host, struct mmc_request *mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void (*prepare_hs400_tuning)(struct tmio_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void (*hs400_downgrade)(struct tmio_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void (*hs400_complete)(struct tmio_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) const struct tmio_mmc_dma_ops *dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct tmio_mmc_data *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void tmio_mmc_host_free(struct tmio_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int tmio_mmc_host_probe(struct tmio_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void tmio_mmc_host_remove(struct tmio_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void tmio_mmc_do_data_irq(struct tmio_mmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) irqreturn_t tmio_mmc_irq(int irq, void *devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline char *tmio_mmc_kmap_atomic(struct scatterlist *sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) local_irq_save(*flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return kmap_atomic(sg_page(sg)) + sg->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned long *flags, void *virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) kunmap_atomic(virt - sg->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) local_irq_restore(*flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int tmio_mmc_host_runtime_suspend(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int tmio_mmc_host_runtime_resume(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ioread16(host->ctl + (addr << host->bus_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u16 *buf, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ioread16_rep(host->ctl + (addr << host->bus_shift), buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ioread16(host->ctl + (addr << host->bus_shift)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ioread16(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 *buf, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* If there is a hook and it returns non-zero then there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * is an error and the write should be skipped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (host->write16_hook && host->write16_hook(host, addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) iowrite16(val, host->ctl + (addr << host->bus_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u16 *buf, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) iowrite16_rep(host->ctl + (addr << host->bus_shift), buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (addr == CTL_IRQ_MASK || addr == CTL_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) val |= host->sdcard_irq_setbit_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) iowrite16(val & 0xffff, host->ctl + (addr << host->bus_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) iowrite16(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) iowrite32(val, host->ctl + (addr << host->bus_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) const u32 *buf, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) iowrite32_rep(host->ctl + (addr << host->bus_shift), buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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