^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for sunxi SD/MMC host controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * (C) Copyright 2017 Sootech SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk/sunxi-ng.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mmc/card.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mmc/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mmc/sd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mmc/sdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* register offset definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SDXC_REG_CMDR (0x18) /* SMC Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SDXC_REG_STAS (0x3C) /* SMC Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SDXC_REG_CHDA (0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SDXC_REG_CBDA (0x94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* New registers introduced in A64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define mmc_readl(host, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) readl((host)->reg_base + SDXC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define mmc_writel(host, reg, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writel((value), (host)->reg_base + SDXC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* global control register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SDXC_SOFT_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SDXC_FIFO_RESET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SDXC_DMA_RESET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SDXC_DMA_ENABLE_BIT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SDXC_POSEDGE_LATCH_DATA BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SDXC_DDR_MODE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SDXC_MEMORY_ACCESS_DONE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SDXC_ACCESS_DONE_DIRECT BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SDXC_ACCESS_BY_AHB BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SDXC_ACCESS_BY_DMA (0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SDXC_HARDWARE_RESET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* clock control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SDXC_MASK_DATA0 BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SDXC_CARD_CLOCK_ON BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SDXC_LOW_POWER_ON BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SDXC_WIDTH1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SDXC_WIDTH4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SDXC_WIDTH8 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* smc command bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SDXC_RESP_EXPIRE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SDXC_LONG_RESPONSE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SDXC_CHECK_RESPONSE_CRC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SDXC_DATA_EXPIRE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SDXC_WRITE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SDXC_SEQUENCE_MODE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SDXC_SEND_AUTO_STOP BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SDXC_WAIT_PRE_OVER BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SDXC_STOP_ABORT_CMD BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SDXC_SEND_INIT_SEQUENCE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SDXC_UPCLK_ONLY BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SDXC_READ_CEATA_DEV BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SDXC_CCS_EXPIRE BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SDXC_ENABLE_BIT_BOOT BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SDXC_ALT_BOOT_OPTIONS BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SDXC_BOOT_ACK_EXPIRE BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SDXC_BOOT_ABORT BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SDXC_VOLTAGE_SWITCH BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SDXC_USE_HOLD_REGISTER BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SDXC_START BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* interrupt bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SDXC_RESP_ERROR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SDXC_COMMAND_DONE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SDXC_DATA_OVER BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SDXC_TX_DATA_REQUEST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SDXC_RX_DATA_REQUEST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SDXC_RESP_CRC_ERROR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SDXC_DATA_CRC_ERROR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SDXC_RESP_TIMEOUT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SDXC_DATA_TIMEOUT BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SDXC_FIFO_RUN_ERROR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SDXC_HARD_WARE_LOCKED BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SDXC_START_BIT_ERROR BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SDXC_AUTO_COMMAND_DONE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SDXC_END_BIT_ERROR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SDXC_SDIO_INTERRUPT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SDXC_CARD_INSERT BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SDXC_CARD_REMOVE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SDXC_INTERRUPT_ERROR_BIT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SDXC_INTERRUPT_DONE_BIT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SDXC_RXWL_FLAG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SDXC_TXWL_FLAG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SDXC_FIFO_EMPTY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SDXC_FIFO_FULL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SDXC_CARD_PRESENT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SDXC_CARD_DATA_BUSY BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SDXC_DATA_FSM_BUSY BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SDXC_DMA_REQUEST BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SDXC_FIFO_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Function select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SDXC_CEATA_ON (0xceaa << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SDXC_SEND_IRQ_RESPONSE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SDXC_SDIO_READ_WAIT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SDXC_ABORT_READ_DATA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SDXC_SEND_CCSD BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SDXC_SEND_AUTO_STOPCCSD BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* IDMA controller bus mod bit field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SDXC_IDMAC_SOFT_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SDXC_IDMAC_FIX_BURST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SDXC_IDMAC_IDMA_ON BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SDXC_IDMAC_REFETCH_DES BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* IDMA status bit field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SDXC_IDMAC_IDLE (0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SDXC_IDMAC_SUSPEND (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SDXC_IDMAC_DESC_READ (2 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SDXC_IDMAC_DESC_CHECK (3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SDXC_IDMAC_READ (6 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SDXC_IDMAC_WRITE (7 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SDXC_IDMAC_DESC_CLOSE (8 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * If the idma-des-size-bits of property is ie 13, bufsize bits are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Bits 0-12: buf1 size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Bits 13-25: buf2 size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Bits 26-31: not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Since we only ever set buf1 size, we can simply store it directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SDXC_CLK_400K 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SDXC_CLK_25M 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SDXC_CLK_50M 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SDXC_CLK_50M_DDR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SDXC_CLK_50M_DDR_8BIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SDXC_2X_TIMING_MODE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SDXC_CAL_START BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SDXC_CAL_DONE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SDXC_CAL_DL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SDXC_CAL_DL_SW_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SDXC_CAL_DL_SW_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SDXC_CAL_DL_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct sunxi_mmc_clk_delay {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 sample;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct sunxi_idma_des {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) __le32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __le32 buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) __le32 buf_addr_ptr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) __le32 buf_addr_ptr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct sunxi_mmc_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 idma_des_size_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) const struct sunxi_mmc_clk_delay *clk_delays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* does the IP block support autocalibration? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) bool can_calibrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Does DATA0 needs to be masked while the clock is updated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) bool mask_data0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * hardware only supports new timing mode, either due to lack of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * a mode switch in the clock controller, or the mmc controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * is permanently configured in the new timing mode, without the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * NTSR mode switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) bool needs_new_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* clock hardware can switch between old and new timing modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) bool ccu_has_timings_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct sunxi_mmc_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) const struct sunxi_mmc_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* IO mapping base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* clock management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct clk *clk_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct clk *clk_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct clk *clk_sample;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct clk *clk_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 int_sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 sdio_imask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dma_addr_t sg_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void *sg_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) bool wait_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct mmc_request *manual_stop_mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int ferror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* vqmmc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) bool vqmmc_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bool use_new_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned long expire = jiffies + msecs_to_jiffies(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) rval = mmc_readl(host, REG_GCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (rval & SDXC_HARDWARE_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (sunxi_mmc_reset_host(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * TODO: sun9i has a larger FIFO and supports higher trigger values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mmc_writel(host, REG_FTRGL, 0x20070008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Maximum timeout value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mmc_writel(host, REG_TMOUT, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Unmask SDIO interrupt if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mmc_writel(host, REG_IMASK, host->sdio_imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Clear all pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mmc_writel(host, REG_RINTR, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Debug register? undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mmc_writel(host, REG_DBGC, 0xdeb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Enable CEATA support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Set DMA descriptor list base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) mmc_writel(host, REG_DLBA, host->sg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rval = mmc_readl(host, REG_GCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rval |= SDXC_INTERRUPT_ENABLE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Undocumented, but found in Allwinner code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) rval &= ~SDXC_ACCESS_DONE_DIRECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mmc_writel(host, REG_GCTRL, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dma_addr_t next_desc = host->sg_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int i, max_len = (1 << host->cfg->idma_des_size_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) for (i = 0; i < data->sg_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) SDXC_IDMAC_DES0_OWN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) SDXC_IDMAC_DES0_DIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (data->sg[i].length == max_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pdes[i].buf_size = 0; /* 0 == max_len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) next_desc += sizeof(struct sunxi_idma_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pdes[i].buf_addr_ptr1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) cpu_to_le32(sg_dma_address(&data->sg[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) SDXC_IDMAC_DES0_ER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) pdes[i - 1].buf_addr_ptr2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * Avoid the io-store starting the idmac hitting io-mem before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * descriptors hit the main-mem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u32 i, dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (dma_len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) for_each_sg(data->sg, sg, data->sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (sg->offset & 3 || sg->length & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "unaligned scatterlist: os %x length %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) sg->offset, sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) sunxi_mmc_init_idma_des(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) rval = mmc_readl(host, REG_GCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) rval |= SDXC_DMA_ENABLE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mmc_writel(host, REG_GCTRL, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) rval |= SDXC_DMA_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mmc_writel(host, REG_GCTRL, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (!(data->flags & MMC_DATA_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mmc_writel(host, REG_DMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 arg, cmd_val, ri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned long expire = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) cmd_val = SDXC_START | SDXC_RESP_EXPIRE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (req->cmd->opcode == SD_IO_RW_EXTENDED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) cmd_val |= SD_IO_RW_DIRECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ((req->cmd->arg >> 28) & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) cmd_val |= MMC_STOP_TRANSMISSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mmc_writel(host, REG_CARG, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mmc_writel(host, REG_CMDR, cmd_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ri = mmc_readl(host, REG_RINTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) time_before(jiffies, expire));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_err(mmc_dev(host->mmc), "send stop command failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (req->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) req->stop->resp[0] = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (req->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) req->stop->resp[0] = mmc_readl(host, REG_RESP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mmc_writel(host, REG_RINTR, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct mmc_command *cmd = host->mrq->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct mmc_data *data = host->mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* For some cmds timeout is normal with sd/mmc cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) cmd->opcode == SD_IO_RW_DIRECT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_dbg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) host->mmc->index, cmd->opcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) host->int_sum & SDXC_RESP_ERROR ? " RE" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Called in interrupt context! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct mmc_request *mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct mmc_data *data = mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) mmc_writel(host, REG_IMASK, host->sdio_imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) mmc_writel(host, REG_IDIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) sunxi_mmc_dump_errinfo(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) mrq->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) host->manual_stop_mrq = mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (mrq->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mrq->stop->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (mrq->cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) data->bytes_xfered = data->blocks * data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mmc_writel(host, REG_IDST, 0x337);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mmc_writel(host, REG_DMAC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) rval = mmc_readl(host, REG_GCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) rval |= SDXC_DMA_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mmc_writel(host, REG_GCTRL, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) rval &= ~SDXC_DMA_ENABLE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mmc_writel(host, REG_GCTRL, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) rval |= SDXC_FIFO_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mmc_writel(host, REG_GCTRL, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) mmc_writel(host, REG_RINTR, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) host->int_sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) host->wait_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct sunxi_mmc_host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u32 msk_int, idma_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) bool finalize = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) bool sdio_int = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) irqreturn_t ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) idma_int = mmc_readl(host, REG_IDST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) msk_int = mmc_readl(host, REG_MISTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) host->mrq, msk_int, idma_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (mrq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) host->wait_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) host->int_sum |= msk_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if ((host->int_sum & SDXC_RESP_TIMEOUT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) !(host->int_sum & SDXC_COMMAND_DONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) mmc_writel(host, REG_IMASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) host->sdio_imask | SDXC_COMMAND_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Don't wait for dma on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) finalize = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) !host->wait_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) finalize = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (msk_int & SDXC_SDIO_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) sdio_int = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) mmc_writel(host, REG_RINTR, msk_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) mmc_writel(host, REG_IDST, idma_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (finalize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = sunxi_mmc_finalize_request(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (finalize && ret == IRQ_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (sdio_int)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mmc_signal_sdio_irq(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct sunxi_mmc_host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned long iflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) spin_lock_irqsave(&host->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) mrq = host->manual_stop_mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) spin_unlock_irqrestore(&host->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!mrq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dev_err(mmc_dev(host->mmc), "no request for manual stop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * We will never have more than one outstanding request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * and we do not complete the request until after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * we've cleared host->manual_stop_mrq so we do not need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * spin lock this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * Additionally we have wait states within this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * so having it in a lock is a very bad idea.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) sunxi_mmc_send_manual_stop(host, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) spin_lock_irqsave(&host->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) host->manual_stop_mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) spin_unlock_irqrestore(&host->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) unsigned long expire = jiffies + msecs_to_jiffies(750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) oclk_en ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) rval = mmc_readl(host, REG_CLKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (oclk_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) rval |= SDXC_CARD_CLOCK_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (host->cfg->mask_data0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) rval |= SDXC_MASK_DATA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mmc_writel(host, REG_CLKCR, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mmc_writel(host, REG_CMDR, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) rval = mmc_readl(host, REG_CMDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) } while (time_before(jiffies, expire) && (rval & SDXC_START));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* clear irq status bits set by the command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mmc_writel(host, REG_RINTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (rval & SDXC_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (host->cfg->mask_data0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) rval = mmc_readl(host, REG_CLKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (!host->cfg->can_calibrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * FIXME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * This is not clear how the calibration is supposed to work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * yet. The best rate have been obtained by simply setting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * delay to 0, as Allwinner does in its BSP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * The only mode that doesn't have such a delay is HS400, that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * is in itself a TODO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct mmc_ios *ios, u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* clk controller delays not used under new timings mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (host->use_new_timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* some old controllers don't support delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (!host->cfg->clk_delays)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* determine delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (rate <= 400000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) index = SDXC_CLK_400K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) } else if (rate <= 25000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) index = SDXC_CLK_25M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) } else if (rate <= 52000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (ios->timing != MMC_TIMING_UHS_DDR50 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ios->timing != MMC_TIMING_MMC_DDR52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) index = SDXC_CLK_50M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) } else if (ios->bus_width == MMC_BUS_WIDTH_8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) index = SDXC_CLK_50M_DDR_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) index = SDXC_CLK_50M_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u32 rval, clock = ios->clock, div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret = sunxi_mmc_oclk_onoff(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* Our clock is gated now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mmc->actual_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (!ios->clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * Under the old timing mode, 8 bit DDR requires the module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * clock to be double the card clock. Under the new timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * mode, all DDR modes require a doubled module clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * We currently only support the standard MMC DDR52 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * This block should be updated once support for other DDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * modes is added.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (ios->timing == MMC_TIMING_MMC_DDR52 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) (host->use_new_timings ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ios->bus_width == MMC_BUS_WIDTH_8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) clock <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (host->use_new_timings && host->cfg->ccu_has_timings_switch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dev_err(mmc_dev(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) "error setting new timing mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) rate = clk_round_rate(host->clk_mmc, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (rate < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) clock, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) clock, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* setting clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = clk_set_rate(host->clk_mmc, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) rate, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* set internal divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) rval = mmc_readl(host, REG_CLKCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) rval &= ~0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) rval |= div - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) mmc_writel(host, REG_CLKCR, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* update card clock rate to account for internal divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) rate /= div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * Configure the controller to use the new timing mode if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * On controllers that only support the new timing mode, such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * the eMMC controller on the A64, this register does not exist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * and any writes to it are ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (host->use_new_timings) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* Don't touch the delay bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) rval = mmc_readl(host, REG_SD_NTSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) rval |= SDXC_2X_TIMING_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) mmc_writel(host, REG_SD_NTSR, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* sunxi_mmc_clk_set_phase expects the actual card clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ret = sunxi_mmc_clk_set_phase(host, ios, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * FIXME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * In HS400 we'll also need to calibrate the data strobe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * signal. This should only happen on the MMC2 controller (at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * least on the A64).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ret = sunxi_mmc_oclk_onoff(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* And we just enabled our clock back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) mmc->actual_clock = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) unsigned char width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) case MMC_BUS_WIDTH_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) case MMC_BUS_WIDTH_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) case MMC_BUS_WIDTH_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* set ddr mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) rval = mmc_readl(host, REG_GCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (ios->timing == MMC_TIMING_UHS_DDR50 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ios->timing == MMC_TIMING_MMC_DDR52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) rval |= SDXC_DDR_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) rval &= ~SDXC_DDR_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) mmc_writel(host, REG_GCTRL, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) host->ferror = sunxi_mmc_clk_set_rate(host, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /* Android code had a usleep_range(50000, 55000); here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static void sunxi_mmc_card_power(struct sunxi_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) switch (ios->power_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) case MMC_POWER_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dev_dbg(mmc_dev(mmc), "Powering card up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (!IS_ERR(mmc->supply.vmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) host->ferror = mmc_regulator_set_ocr(mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) mmc->supply.vmmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ios->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (host->ferror)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (!IS_ERR(mmc->supply.vqmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) host->ferror = regulator_enable(mmc->supply.vqmmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (host->ferror) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_err(mmc_dev(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) "failed to enable vqmmc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) host->vqmmc_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) case MMC_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dev_dbg(mmc_dev(mmc), "Powering card off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (!IS_ERR(mmc->supply.vmmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) regulator_disable(mmc->supply.vqmmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) host->vqmmc_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct sunxi_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) sunxi_mmc_card_power(host, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) sunxi_mmc_set_bus_width(host, ios->bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) sunxi_mmc_set_clk(host, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* vqmmc regulator is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (!IS_ERR(mmc->supply.vqmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ret = mmc_regulator_set_vqmmc(mmc, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return ret < 0 ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct sunxi_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) u32 imask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) pm_runtime_get_noresume(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) imask = mmc_readl(host, REG_IMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) host->sdio_imask = SDXC_SDIO_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) imask |= SDXC_SDIO_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) host->sdio_imask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) imask &= ~SDXC_SDIO_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) mmc_writel(host, REG_IMASK, imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) pm_runtime_put_noidle(host->mmc->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct sunxi_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) mmc_writel(host, REG_HWRST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) mmc_writel(host, REG_HWRST, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) udelay(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct sunxi_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct mmc_command *cmd = mrq->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct mmc_data *data = mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) unsigned long iflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) u32 imask = SDXC_INTERRUPT_ERROR_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) bool wait_dma = host->wait_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* Check for set_ios errors (should never happen) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (host->ferror) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) mrq->cmd->error = host->ferror;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) mmc_request_done(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ret = sunxi_mmc_map_dma(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dev_err(mmc_dev(mmc), "map DMA failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) cmd->error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) data->error = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) mmc_request_done(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (cmd->opcode == MMC_GO_IDLE_STATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) cmd_val |= SDXC_SEND_INIT_SEQUENCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) imask |= SDXC_COMMAND_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) cmd_val |= SDXC_RESP_EXPIRE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (cmd->flags & MMC_RSP_136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) cmd_val |= SDXC_LONG_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (cmd->flags & MMC_RSP_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) cmd_val |= SDXC_CHECK_RESPONSE_CRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (cmd->data->stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) imask |= SDXC_AUTO_COMMAND_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) cmd_val |= SDXC_SEND_AUTO_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) imask |= SDXC_DATA_OVER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (cmd->data->flags & MMC_DATA_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) cmd_val |= SDXC_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) wait_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) imask |= SDXC_COMMAND_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) imask |= SDXC_COMMAND_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) cmd_val & 0x3f, cmd_val, cmd->arg, imask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) spin_lock_irqsave(&host->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (host->mrq || host->manual_stop_mrq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) spin_unlock_irqrestore(&host->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) dev_err(mmc_dev(mmc), "request already pending\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) mrq->cmd->error = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) mmc_request_done(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) mmc_writel(host, REG_BLKSZ, data->blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) sunxi_mmc_start_dma(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) host->mrq = mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) host->wait_dma = wait_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) mmc_writel(host, REG_IMASK, host->sdio_imask | imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) mmc_writel(host, REG_CARG, cmd->arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) mmc_writel(host, REG_CMDR, cmd_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) spin_unlock_irqrestore(&host->lock, iflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static int sunxi_mmc_card_busy(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct sunxi_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static const struct mmc_host_ops sunxi_mmc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .request = sunxi_mmc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .set_ios = sunxi_mmc_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .get_ro = mmc_gpio_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .get_cd = mmc_gpio_get_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .start_signal_voltage_switch = sunxi_mmc_volt_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .hw_reset = sunxi_mmc_hw_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .card_busy = sunxi_mmc_card_busy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) [SDXC_CLK_50M] = { .output = 90, .sample = 120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* Value from A83T "new timing mode". Works but might not be right. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) [SDXC_CLK_400K] = { .output = 180, .sample = 180 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) [SDXC_CLK_25M] = { .output = 180, .sample = 75 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) [SDXC_CLK_50M] = { .output = 150, .sample = 120 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static const struct sunxi_mmc_cfg sun4i_a10_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .idma_des_size_bits = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .clk_delays = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .can_calibrate = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static const struct sunxi_mmc_cfg sun5i_a13_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .idma_des_size_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .clk_delays = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .can_calibrate = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .idma_des_size_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .clk_delays = sunxi_mmc_clk_delays,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .can_calibrate = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .idma_des_size_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .clk_delays = sunxi_mmc_clk_delays,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .can_calibrate = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .ccu_has_timings_switch = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .idma_des_size_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .clk_delays = sun9i_mmc_clk_delays,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .can_calibrate = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .idma_des_size_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .clk_delays = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .can_calibrate = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .mask_data0 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .needs_new_timings = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .idma_des_size_bits = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .clk_delays = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .can_calibrate = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .needs_new_timings = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static const struct of_device_id sunxi_mmc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static int sunxi_mmc_enable(struct sunxi_mmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (!IS_ERR(host->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ret = reset_control_reset(host->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ret = clk_prepare_enable(host->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) goto error_assert_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ret = clk_prepare_enable(host->clk_mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dev_err(host->dev, "Enable mmc clk err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) goto error_disable_clk_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ret = clk_prepare_enable(host->clk_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) dev_err(host->dev, "Enable output clk err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) goto error_disable_clk_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ret = clk_prepare_enable(host->clk_sample);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) dev_err(host->dev, "Enable sample clk err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) goto error_disable_clk_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * Sometimes the controller asserts the irq on boot for some reason,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * make sure the controller is in a sane state before enabling irqs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ret = sunxi_mmc_reset_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) goto error_disable_clk_sample;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) error_disable_clk_sample:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) clk_disable_unprepare(host->clk_sample);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) error_disable_clk_output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) clk_disable_unprepare(host->clk_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) error_disable_clk_mmc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) clk_disable_unprepare(host->clk_mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) error_disable_clk_ahb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) clk_disable_unprepare(host->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) error_assert_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (!IS_ERR(host->reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) reset_control_assert(host->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static void sunxi_mmc_disable(struct sunxi_mmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) sunxi_mmc_reset_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) clk_disable_unprepare(host->clk_sample);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) clk_disable_unprepare(host->clk_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) clk_disable_unprepare(host->clk_mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) clk_disable_unprepare(host->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (!IS_ERR(host->reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) reset_control_assert(host->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) host->cfg = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (!host->cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ret = mmc_regulator_get_supply(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) host->reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (IS_ERR(host->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return PTR_ERR(host->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (IS_ERR(host->clk_ahb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) dev_err(&pdev->dev, "Could not get ahb clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return PTR_ERR(host->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (IS_ERR(host->clk_mmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) dev_err(&pdev->dev, "Could not get mmc clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return PTR_ERR(host->clk_mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (host->cfg->clk_delays) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) host->clk_output = devm_clk_get(&pdev->dev, "output");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (IS_ERR(host->clk_output)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) dev_err(&pdev->dev, "Could not get output clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return PTR_ERR(host->clk_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) host->clk_sample = devm_clk_get(&pdev->dev, "sample");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (IS_ERR(host->clk_sample)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) dev_err(&pdev->dev, "Could not get sample clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return PTR_ERR(host->clk_sample);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) "ahb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (PTR_ERR(host->reset) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return PTR_ERR(host->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) ret = sunxi_mmc_enable(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) host->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (host->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) goto error_disable_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) error_disable_mmc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) sunxi_mmc_disable(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static int sunxi_mmc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct sunxi_mmc_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (!mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) dev_err(&pdev->dev, "mmc alloc host failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) platform_set_drvdata(pdev, mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) host->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) host->mmc = mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) spin_lock_init(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ret = sunxi_mmc_resource_request(host, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) goto error_free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) &host->sg_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (!host->sg_cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) goto error_free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (host->cfg->ccu_has_timings_switch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * Supports both old and new timing modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) * Try setting the clk to new timing mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /* And check the result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * For whatever reason we were not able to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * the current active mode. Default to old mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) dev_warn(&pdev->dev, "MMC clk timing mode unknown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) host->use_new_timings = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) host->use_new_timings = !!ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) } else if (host->cfg->needs_new_timings) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /* Supports new timing mode only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) host->use_new_timings = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) mmc->ops = &sunxi_mmc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) mmc->max_blk_count = 8192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) mmc->max_blk_size = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* 400kHz ~ 52MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) mmc->f_min = 400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) mmc->f_max = 52000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) MMC_CAP_SDIO_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * Some H5 devices do not have signal traces precise enough to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * use HS DDR mode for their eMMC chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * We still enable HS DDR modes for all the other controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) * variants that support them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if ((host->cfg->clk_delays || host->use_new_timings) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) !of_device_is_compatible(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) "allwinner,sun50i-h5-emmc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) ret = mmc_of_parse(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) goto error_free_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * If we don't support delay chains in the SoC, we can't use any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * of the higher speed modes. Mask them out in case the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * tree specifies the properties for them, which gets added to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * the caps by mmc_of_parse() above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (!(host->cfg->clk_delays || host->use_new_timings)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) MMC_CAP_1_2V_DDR | MMC_CAP_UHS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) mmc->caps2 &= ~MMC_CAP2_HS200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /* TODO: This driver doesn't support HS400 mode yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) mmc->caps2 &= ~MMC_CAP2_HS400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ret = sunxi_mmc_init_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) goto error_free_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ret = mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) goto error_free_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) dev_info(&pdev->dev, "initialized, max. request size: %u KB%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) mmc->max_req_size >> 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) host->use_new_timings ? ", uses new timings mode" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) error_free_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) error_free_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static int sunxi_mmc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) struct mmc_host *mmc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) struct sunxi_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) mmc_remove_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) pm_runtime_force_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) disable_irq(host->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) sunxi_mmc_disable(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static int sunxi_mmc_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) struct mmc_host *mmc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct sunxi_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) ret = sunxi_mmc_enable(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) sunxi_mmc_init_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) sunxi_mmc_set_bus_width(host, mmc->ios.bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) sunxi_mmc_set_clk(host, &mmc->ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) enable_irq(host->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static int sunxi_mmc_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) struct mmc_host *mmc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) struct sunxi_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) * When clocks are off, it's possible receiving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) * fake interrupts, which will stall the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) * Disabling the irq will prevent this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) disable_irq(host->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) sunxi_mmc_reset_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) sunxi_mmc_disable(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static const struct dev_pm_ops sunxi_mmc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) sunxi_mmc_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static struct platform_driver sunxi_mmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .name = "sunxi-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .of_match_table = of_match_ptr(sunxi_mmc_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .pm = &sunxi_mmc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .probe = sunxi_mmc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .remove = sunxi_mmc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) module_platform_driver(sunxi_mmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) MODULE_ALIAS("platform:sunxi-mmc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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