^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sdricoh_cs.c - driver for Ricoh Secure Digital Card Readers that can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * found on some Ricoh RL5c476 II cardbus bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006 - 2008 Sascha Sommer <saschasommer@freenet.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define VERBOSE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <pcmcia/cistpl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <pcmcia/ds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRIVER_NAME "sdricoh_cs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static unsigned int switchlocked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* i/o region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SDRICOH_PCI_REGION 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SDRICOH_PCI_REGION_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R104_VERSION 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R200_CMD 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R204_CMD_ARG 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R208_DATAIO 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R20C_RESP 0x20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R21C_STATUS 0x21c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R2E0_INIT 0x2e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R2E4_STATUS_RESP 0x2e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R2F0_RESET 0x2f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define R224_MODE 0x224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define R226_BLOCKSIZE 0x226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define R228_POWER 0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define R230_DATA 0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* flags for the R21C_STATUS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STATUS_CMD_FINISHED 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STATUS_TRANSFER_FINISHED 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STATUS_CARD_INSERTED 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define STATUS_CARD_LOCKED 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STATUS_CMD_TIMEOUT 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define STATUS_READY_TO_READ 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define STATUS_READY_TO_WRITE 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STATUS_BUSY 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* timeouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SDRICOH_CMD_TIMEOUT_US 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SDRICOH_DATA_TIMEOUT_US 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* list of supported pcmcia devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const struct pcmcia_device_id pcmcia_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* vendor and device strings followed by their crc32 hashes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PCMCIA_DEVICE_PROD_ID12("RICOH", "Bay1Controller", 0xd9f522ed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0xc3901202),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PCMCIA_DEVICE_PROD_ID12("RICOH", "Bay Controller", 0xd9f522ed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0xace80909),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PCMCIA_DEVICE_NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MODULE_DEVICE_TABLE(pcmcia, pcmcia_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* mmc privdata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct sdricoh_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct mmc_host *mmc; /* MMC structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned char __iomem *iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int app_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /***************** register i/o helper functions *****************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline unsigned int sdricoh_readl(struct sdricoh_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int value = readl(host->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dev_vdbg(host->dev, "rl %x 0x%x\n", reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline void sdricoh_writel(struct sdricoh_host *host, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel(value, host->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dev_vdbg(host->dev, "wl %x 0x%x\n", reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline unsigned int sdricoh_readw(struct sdricoh_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int value = readw(host->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dev_vdbg(host->dev, "rb %x 0x%x\n", reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static inline void sdricoh_writew(struct sdricoh_host *host, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned short value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writew(value, host->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_vdbg(host->dev, "ww %x 0x%x\n", reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline unsigned int sdricoh_readb(struct sdricoh_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int value = readb(host->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_vdbg(host->dev, "rb %x 0x%x\n", reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static bool sdricoh_status_ok(struct sdricoh_host *host, unsigned int status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int wanted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) sdricoh_writel(host, R2E4_STATUS_RESP, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return status & wanted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int sdricoh_query_status(struct sdricoh_host *host, unsigned int wanted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct device *dev = host->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = read_poll_timeout(sdricoh_readl, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) sdricoh_status_ok(host, status, wanted),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 32, SDRICOH_DATA_TIMEOUT_US, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) host, R21C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_err(dev, "query_status: timeout waiting for %x\n", wanted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* do not do this check in the loop as some commands fail otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (status & 0x7F0000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_err(dev, "waiting for status bit %x failed\n", wanted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int sdricoh_mmc_cmd(struct sdricoh_host *host, struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int status, timeout_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned char opcode = cmd->opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* reset status reg? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) sdricoh_writel(host, R21C_STATUS, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* MMC_APP_CMDs need some special handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (host->app_cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) opcode |= 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) host->app_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } else if (opcode == MMC_APP_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) host->app_cmd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* fill parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) sdricoh_writel(host, R204_CMD_ARG, cmd->arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) sdricoh_writel(host, R200_CMD, (0x10000 << 8) | opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* wait for command completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) timeout_us = cmd->busy_timeout ? cmd->busy_timeout * 1000 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) SDRICOH_CMD_TIMEOUT_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = read_poll_timeout(sdricoh_readl, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) sdricoh_status_ok(host, status, STATUS_CMD_FINISHED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 32, timeout_us, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) host, R21C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Don't check for timeout status in the loop, as it's not always reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret || status & STATUS_CMD_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int sdricoh_reset(struct sdricoh_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_dbg(host->dev, "reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) sdricoh_writel(host, R2F0_RESET, 0x10001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) sdricoh_writel(host, R2E0_INIT, 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (sdricoh_readl(host, R2E0_INIT) != 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) sdricoh_writel(host, R2E0_INIT, 0x10007);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) sdricoh_writel(host, R224_MODE, 0x2000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) sdricoh_writel(host, R228_POWER, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* status register ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) sdricoh_writel(host, R21C_STATUS, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int sdricoh_blockio(struct sdricoh_host *host, int read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u8 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* wait until the data is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (sdricoh_query_status(host, STATUS_READY_TO_READ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) sdricoh_writel(host, R21C_STATUS, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* read data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) data = sdricoh_readl(host, R230_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) size = min(len, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) len -= size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) while (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *buf = data & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) data >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) size--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (sdricoh_query_status(host, STATUS_READY_TO_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) sdricoh_writel(host, R21C_STATUS, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) size = min(len, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) len -= size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) while (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) data >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) data |= (u32)*buf << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) size--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) sdricoh_writel(host, R230_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void sdricoh_request(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct sdricoh_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct mmc_command *cmd = mrq->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct mmc_data *data = cmd->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct device *dev = host->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_dbg(dev, "=============================\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_dbg(dev, "sdricoh_request opcode=%i\n", cmd->opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) sdricoh_writel(host, R21C_STATUS, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* read/write commands seem to require this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) sdricoh_writew(host, R226_BLOCKSIZE, data->blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) sdricoh_writel(host, R208_DATAIO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) cmd->error = sdricoh_mmc_cmd(host, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* read response buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* CRC is stripped so we need to do some shifting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) cmd->resp[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) sdricoh_readl(host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) R20C_RESP + (3 - i) * 4) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (i != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cmd->resp[i] |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) sdricoh_readb(host, R20C_RESP +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) (3 - i) * 4 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) cmd->resp[0] = sdricoh_readl(host, R20C_RESP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* transfer data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (data && cmd->error == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_dbg(dev, "transfer: blksz %i blocks %i sg_len %i "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "sg length %i\n", data->blksz, data->blocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) data->sg_len, data->sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* enter data reading mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) sdricoh_writel(host, R21C_STATUS, 0x837f031e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) for (i = 0; i < data->blocks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) size_t len = data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct page *page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) page = sg_page(data->sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) buf = kmap(page) + data->sg->offset + (len * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) result =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) sdricoh_blockio(host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) data->flags & MMC_DATA_READ, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) kunmap(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) flush_dcache_page(page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_err(dev, "sdricoh_request: cmd %i "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "block transfer failed\n", cmd->opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) cmd->error = result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) data->bytes_xfered += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) sdricoh_writel(host, R208_DATAIO, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (sdricoh_query_status(host, STATUS_TRANSFER_FINISHED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dev_err(dev, "sdricoh_request: transfer end error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) cmd->error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* FIXME check busy flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) mmc_request_done(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_dbg(dev, "=============================\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void sdricoh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct sdricoh_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_dbg(host->dev, "set_ios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ios->power_mode == MMC_POWER_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) sdricoh_writel(host, R228_POWER, 0xc0e0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (ios->bus_width == MMC_BUS_WIDTH_4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) sdricoh_writel(host, R224_MODE, 0x2000300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) sdricoh_writel(host, R228_POWER, 0x40e0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) sdricoh_writel(host, R224_MODE, 0x2000340);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) } else if (ios->power_mode == MMC_POWER_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) sdricoh_writel(host, R224_MODE, 0x2000320);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) sdricoh_writel(host, R228_POWER, 0xe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int sdricoh_get_ro(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct sdricoh_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) status = sdricoh_readl(host, R21C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) sdricoh_writel(host, R2E4_STATUS_RESP, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* some notebooks seem to have the locked flag switched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (switchlocked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return !(status & STATUS_CARD_LOCKED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return (status & STATUS_CARD_LOCKED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct mmc_host_ops sdricoh_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .request = sdricoh_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .set_ios = sdricoh_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .get_ro = sdricoh_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* initialize the control and register it to the mmc framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int sdricoh_init_mmc(struct pci_dev *pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct pcmcia_device *pcmcia_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) void __iomem *iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct sdricoh_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct device *dev = &pcmcia_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* map iomem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (pci_resource_len(pci_dev, SDRICOH_PCI_REGION) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) SDRICOH_PCI_REGION_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_dbg(dev, "unexpected pci resource len\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) iobase =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pci_iomap(pci_dev, SDRICOH_PCI_REGION, SDRICOH_PCI_REGION_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (!iobase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_err(dev, "unable to map iobase\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* check version? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (readl(iobase + R104_VERSION) != 0x4000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_dbg(dev, "no supported mmc controller found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) result = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) goto unmap_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* allocate privdata */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) mmc = pcmcia_dev->priv =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) mmc_alloc_host(sizeof(struct sdricoh_host), &pcmcia_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_err(dev, "mmc_alloc_host failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) result = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) goto unmap_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) host->iobase = iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) host->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) host->pci_dev = pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mmc->ops = &sdricoh_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* FIXME: frequency and voltage handling is done by the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mmc->f_min = 450000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mmc->f_max = 24000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mmc->caps |= MMC_CAP_4_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mmc->max_seg_size = 1024 * 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mmc->max_blk_size = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* reset the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (sdricoh_reset(host)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_dbg(dev, "could not reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) goto free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) result = mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (!result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_dbg(dev, "mmc host registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) free_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unmap_io:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pci_iounmap(pci_dev, iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* search for supported mmc controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int sdricoh_pcmcia_probe(struct pcmcia_device *pcmcia_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct pci_dev *pci_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_info(&pcmcia_dev->dev, "Searching MMC controller for pcmcia device"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) " %s %s ...\n", pcmcia_dev->prod_id[0], pcmcia_dev->prod_id[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* search pci cardbus bridge that contains the mmc controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* the io region is already claimed by yenta_socket... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) while ((pci_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pci_get_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pci_dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* try to init the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (!sdricoh_init_mmc(pci_dev, pcmcia_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev_info(&pcmcia_dev->dev, "MMC controller found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_err(&pcmcia_dev->dev, "No MMC controller was found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static void sdricoh_pcmcia_detach(struct pcmcia_device *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct mmc_host *mmc = link->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dev_dbg(&link->dev, "detach\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* remove mmc host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct sdricoh_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) mmc_remove_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) pci_iounmap(host->pci_dev, host->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pci_dev_put(host->pci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pcmcia_disable_device(link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int sdricoh_pcmcia_suspend(struct pcmcia_device *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_dbg(&link->dev, "suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int sdricoh_pcmcia_resume(struct pcmcia_device *link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct mmc_host *mmc = link->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_dbg(&link->dev, "resume\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) sdricoh_reset(mmc_priv(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define sdricoh_pcmcia_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define sdricoh_pcmcia_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static struct pcmcia_driver sdricoh_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .probe = sdricoh_pcmcia_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .remove = sdricoh_pcmcia_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .id_table = pcmcia_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .suspend = sdricoh_pcmcia_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .resume = sdricoh_pcmcia_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) module_pcmcia_driver(sdricoh_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) module_param(switchlocked, uint, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MODULE_AUTHOR("Sascha Sommer <saschasommer@freenet.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MODULE_DESCRIPTION("Ricoh PCMCIA Secure Digital Interface driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MODULE_PARM_DESC(switchlocked, "Switch the cards locked status."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) "Use this when unlocked cards are shown readonly (default 0)");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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