^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "cqhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* CTL_CFG Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CTL_CFG_2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CTL_CFG_3 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SLOTTYPE_MASK GENMASK(31, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SLOTTYPE_EMBEDDED BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TUNINGFORSDR50_MASK BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* PHY Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PHY_CTRL1 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PHY_CTRL2 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PHY_CTRL3 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PHY_CTRL4 0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PHY_CTRL5 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PHY_CTRL6 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PHY_STAT1 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PHY_STAT2 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IOMUX_ENABLE_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OTAPDLYENA_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OTAPDLYSEL_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OTAPDLYSEL_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define STRBSEL_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STRBSEL_4BIT_MASK GENMASK(27, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STRBSEL_8BIT_MASK GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SEL50_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SEL50_MASK BIT(SEL50_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SEL100_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SEL100_MASK BIT(SEL100_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FREQSEL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FREQSEL_MASK GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLKBUFSEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLKBUFSEL_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DLL_TRIM_ICP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DR_TY_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DR_TY_MASK GENMASK(22, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ENDLL_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ENDLL_MASK BIT(ENDLL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DLLRDY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PDB_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PDB_MASK BIT(PDB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CALDONE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CALDONE_MASK BIT(CALDONE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RETRIM_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RETRIM_MASK BIT(RETRIM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SELDLYTXCLK_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SELDLYRXCLK_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ITAPDLYSEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ITAPDLYSEL_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ITAPDLYENA_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ITAPCHGWIN_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DRIVER_STRENGTH_50_OHM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DRIVER_STRENGTH_33_OHM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DRIVER_STRENGTH_66_OHM 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DRIVER_STRENGTH_100_OHM 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DRIVER_STRENGTH_40_OHM 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLOCK_TOO_SLOW_HZ 50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Command Queue Host Controller Interface Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SDHCI_AM654_CQE_BASE_ADDR 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct regmap_config sdhci_am654_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct timing_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) const char *otap_binding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) const char *itap_binding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct timing_data td[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "ti,itap-del-sel-legacy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "ti,itap-del-sel-mmc-hs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MMC_CAP_MMC_HIGHSPEED},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "ti,itap-del-sel-sd-hs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MMC_CAP_SD_HIGHSPEED},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "ti,itap-del-sel-sdr12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MMC_CAP_UHS_SDR12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "ti,itap-del-sel-sdr25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MMC_CAP_UHS_SDR25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MMC_CAP_UHS_SDR50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MMC_CAP_UHS_SDR104},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MMC_CAP_UHS_DDR50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "ti,itap-del-sel-ddr52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MMC_CAP_DDR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MMC_CAP2_HS200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MMC_CAP2_HS400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct sdhci_am654_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct regmap *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool legacy_otapdly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int otap_del_sel[ARRAY_SIZE(td)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int itap_del_sel[ARRAY_SIZE(td)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int clkbuf_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int trm_icp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int drv_strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int strb_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct sdhci_am654_driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const struct sdhci_pltfm_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IOMUX_PRESENT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define FREQSEL_2_BIT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define STRBSEL_4_BIT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DLL_PRESENT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DLL_CALIB (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int sel50, sel100, freqsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Disable delay chain mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (sdhci_am654->flags & FREQSEL_2_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) case 200000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) sel50 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) sel100 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case 100000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) sel50 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) sel100 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) sel50 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) sel100 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Configure PHY DLL frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mask = SEL50_MASK | SEL100_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case 200000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) freqsel = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) freqsel = 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) freqsel << FREQSEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Configure DLL TRIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mask = DLL_TRIM_ICP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Configure DLL driver strength */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mask |= DR_TY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Enable DLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 0x1 << ENDLL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Poll for DLL ready. Use a one second timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * Works in all experiments done so far
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) val & DLLRDY_MASK, 1000, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 itapdly)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Set ITAPCHGWIN before writing to ITAPDLY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 1 << ITAPCHGWIN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) itapdly << ITAPDLYSEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned char timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) sdhci_am654_write_itapdly(sdhci_am654,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sdhci_am654->itap_del_sel[timing]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned char timing = host->mmc->ios.timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 otap_del_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 otap_del_ena;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) sdhci_set_clock(host, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Setup DLL Output TAP delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (sdhci_am654->legacy_otapdly)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) otap_del_sel = sdhci_am654->otap_del_sel[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) otap_del_sel = sdhci_am654->otap_del_sel[timing];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) val = (otap_del_ena << OTAPDLYENA_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) (otap_del_sel << OTAPDLYSEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Write to STRBSEL for HS400 speed mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (timing == MMC_TIMING_MMC_HS400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (sdhci_am654->flags & STRBSEL_4_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) mask |= STRBSEL_4BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mask |= STRBSEL_8BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) sdhci_am654_setup_dll(host, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) sdhci_am654_setup_delay_chain(sdhci_am654, timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) sdhci_am654->clkbuf_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned char timing = host->mmc->ios.timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 otap_del_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Setup DLL Output TAP delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (sdhci_am654->legacy_otapdly)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) otap_del_sel = sdhci_am654->otap_del_sel[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) otap_del_sel = sdhci_am654->otap_del_sel[timing];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) val = (0x1 << OTAPDLYENA_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) (otap_del_sel << OTAPDLYSEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) sdhci_am654->clkbuf_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) sdhci_set_clock(host, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) writeb(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) usleep_range(1000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return readb(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define MAX_POWER_ON_TIMEOUT 1500000 /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned char timing = host->mmc->ios.timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u8 pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (reg == SDHCI_HOST_CONTROL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) switch (timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * According to the data manual, HISPD bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * should not be set in these speed modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case MMC_TIMING_SD_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case MMC_TIMING_MMC_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case MMC_TIMING_UHS_SDR12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case MMC_TIMING_UHS_SDR25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) val &= ~SDHCI_CTRL_HISPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) writeb(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * Power on will not happen until the card detect debounce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * timer expires. Wait at least 1.5 seconds for the power on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * bit to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pwr & SDHCI_POWER_ON, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MAX_POWER_ON_TIMEOUT, false, host, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev_warn(mmc_dev(host->mmc), "Power on failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int err = sdhci_execute_tuning(mmc, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * Tuning data remains in the buffer after tuning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * Do a command and data reset to get rid of it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int cmd_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int data_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) cqhci_irq(host->mmc, intmask, cmd_error, data_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define ITAP_MAX 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 itap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Enable ITAPDLY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 1 << ITAPDLYENA_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) for (itap = 0; itap < ITAP_MAX; itap++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) sdhci_am654_write_itapdly(sdhci_am654, itap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) cur_val = !mmc_send_tuning(host->mmc, opcode, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (cur_val && !prev_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pass_window = itap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!cur_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) fail_len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) prev_val = cur_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Having determined the length of the failing window and start of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * the passing window calculate the length of the passing window and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * set the final value halfway through it considering the range as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * circular buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) pass_len = ITAP_MAX - fail_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) sdhci_am654_write_itapdly(sdhci_am654, itap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static struct sdhci_ops sdhci_am654_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .get_max_clock = sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .set_power = sdhci_set_power_and_bus_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .set_clock = sdhci_am654_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .write_b = sdhci_am654_write_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .irq = sdhci_am654_cqhci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const struct sdhci_pltfm_data sdhci_am654_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .ops = &sdhci_am654_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .pdata = &sdhci_am654_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) DLL_CALIB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .pdata = &sdhci_am654_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static struct sdhci_ops sdhci_j721e_8bit_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .get_max_clock = sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .set_power = sdhci_set_power_and_bus_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .set_clock = sdhci_am654_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .write_b = sdhci_am654_write_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .irq = sdhci_am654_cqhci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .ops = &sdhci_j721e_8bit_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .pdata = &sdhci_j721e_8bit_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .flags = DLL_PRESENT | DLL_CALIB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static struct sdhci_ops sdhci_j721e_4bit_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .get_max_clock = sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .set_power = sdhci_set_power_and_bus_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .set_clock = sdhci_j721e_4bit_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .write_b = sdhci_am654_write_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .irq = sdhci_am654_cqhci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .ops = &sdhci_j721e_4bit_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .pdata = &sdhci_j721e_4bit_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .flags = IOMUX_PRESENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct soc_device_attribute sdhci_am654_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) { .family = "AM65X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .revision = "SR1.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .data = &sdhci_am654_sr1_drvdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {/* sentinel */}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static void sdhci_am654_dumpregs(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) sdhci_dumpregs(mmc_priv(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const struct cqhci_host_ops sdhci_am654_cqhci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .enable = sdhci_cqe_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .disable = sdhci_cqe_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .dumpregs = sdhci_am654_dumpregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static int sdhci_am654_cqe_add_host(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct cqhci_host *cq_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!cq_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) cq_host->ops = &sdhci_am654_cqhci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) host->mmc->caps2 |= MMC_CAP2_CQE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = cqhci_init(cq_host, host->mmc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int sdhci_am654_get_otap_delay(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct sdhci_am654_data *sdhci_am654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct device *dev = mmc_dev(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * ti,otap-del-sel-legacy is mandatory, look for old binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * if not found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ret = device_property_read_u32(dev, "ti,otap-del-sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) &sdhci_am654->otap_del_sel[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dev_err(dev, "Couldn't find otap-del-sel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dev_info(dev, "Using legacy binding ti,otap-del-sel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) sdhci_am654->legacy_otapdly = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = device_property_read_u32(dev, td[i].otap_binding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) &sdhci_am654->otap_del_sel[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dev_dbg(dev, "Couldn't find %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) td[i].otap_binding);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Remove the corresponding capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * if an otap-del-sel value is not found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (i <= MMC_TIMING_MMC_DDR52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) host->mmc->caps &= ~td[i].capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) host->mmc->caps2 &= ~td[i].capability;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (td[i].itap_binding)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) device_property_read_u32(dev, td[i].itap_binding,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) &sdhci_am654->itap_del_sel[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int sdhci_am654_init(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u32 ctl_cfg_2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Reset OTAP to default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (sdhci_am654->flags & DLL_CALIB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) regmap_read(sdhci_am654->base, PHY_STAT1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (~val & CALDONE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Calibrate IO lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PDB_MASK, PDB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret = regmap_read_poll_timeout(sdhci_am654->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PHY_STAT1, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) val & CALDONE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Enable pins by setting IO mux to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (sdhci_am654->flags & IOMUX_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) IOMUX_ENABLE_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Set slot type based on SD or eMMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ctl_cfg_2 = SLOTTYPE_EMBEDDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ctl_cfg_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Enable tuning for SDR50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) TUNINGFORSDR50_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = sdhci_setup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = sdhci_am654_cqe_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) goto err_cleanup_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ret = sdhci_am654_get_otap_delay(host, sdhci_am654);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) goto err_cleanup_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ret = __sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) goto err_cleanup_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) err_cleanup_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) sdhci_cleanup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int sdhci_am654_get_of_property(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct sdhci_am654_data *sdhci_am654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int drv_strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (sdhci_am654->flags & DLL_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ret = device_property_read_u32(dev, "ti,trm-icp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) &sdhci_am654->trm_icp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = device_property_read_u32(dev, "ti,driver-strength-ohm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) &drv_strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) switch (drv_strength) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) case 50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) case 33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case 66:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) case 100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) case 40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dev_err(dev, "Invalid driver strength\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) device_property_read_u32(dev, "ti,clkbuf-sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) &sdhci_am654->clkbuf_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) sdhci_get_of_property(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static const struct of_device_id sdhci_am654_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .compatible = "ti,am654-sdhci-5.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .data = &sdhci_am654_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .compatible = "ti,j721e-sdhci-8bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .data = &sdhci_j721e_8bit_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .compatible = "ti,j721e-sdhci-4bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .data = &sdhci_j721e_4bit_drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int sdhci_am654_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) const struct sdhci_am654_driver_data *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) const struct soc_device_attribute *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct sdhci_am654_data *sdhci_am654;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct clk *clk_xin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) drvdata = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Update drvdata based on SoC revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) soc = soc_device_match(sdhci_am654_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (soc && soc->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) drvdata = soc->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) sdhci_am654->flags = drvdata->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) clk_xin = devm_clk_get(dev, "clk_xin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (IS_ERR(clk_xin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_err(dev, "clk_xin clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ret = PTR_ERR(clk_xin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) goto err_pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pltfm_host->clk = clk_xin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Clocks are enabled using pm_runtime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) goto pm_runtime_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) base = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) goto pm_runtime_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) sdhci_am654->base = devm_regmap_init_mmio(dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) &sdhci_am654_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (IS_ERR(sdhci_am654->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dev_err(dev, "Failed to initialize regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = PTR_ERR(sdhci_am654->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) goto pm_runtime_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ret = sdhci_am654_get_of_property(pdev, sdhci_am654);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) goto pm_runtime_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dev_err(dev, "parsing dt failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) goto pm_runtime_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ret = sdhci_am654_init(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) goto pm_runtime_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) pm_runtime_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) pm_runtime_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) err_pltfm_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static int sdhci_am654_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct sdhci_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) sdhci_remove_host(host, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static struct platform_driver sdhci_am654_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .name = "sdhci-am654",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .of_match_table = sdhci_am654_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .probe = sdhci_am654_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .remove = sdhci_am654_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) module_platform_driver(sdhci_am654_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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