^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Header file for Host Controller registers and I/O accessors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __SDHCI_HW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __SDHCI_HW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/android_kabi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Controller registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SDHCI_DMA_ADDRESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SDHCI_BLOCK_SIZE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SDHCI_BLOCK_COUNT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SDHCI_ARGUMENT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SDHCI_TRANSFER_MODE 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SDHCI_TRNS_DMA 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SDHCI_TRNS_BLK_CNT_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SDHCI_TRNS_AUTO_CMD12 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SDHCI_TRNS_AUTO_CMD23 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SDHCI_TRNS_AUTO_SEL 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SDHCI_TRNS_READ 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SDHCI_TRNS_MULTI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SDHCI_COMMAND 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SDHCI_CMD_RESP_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SDHCI_CMD_CRC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SDHCI_CMD_INDEX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SDHCI_CMD_DATA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SDHCI_CMD_ABORTCMD 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SDHCI_CMD_RESP_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SDHCI_CMD_RESP_LONG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SDHCI_CMD_RESP_SHORT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SDHCI_RESPONSE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SDHCI_BUFFER 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SDHCI_PRESENT_STATE 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SDHCI_CMD_INHIBIT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SDHCI_DATA_INHIBIT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SDHCI_DOING_WRITE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SDHCI_DOING_READ 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SDHCI_SPACE_AVAILABLE 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SDHCI_DATA_AVAILABLE 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SDHCI_CARD_PRESENT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SDHCI_CARD_PRES_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SDHCI_CD_STABLE 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SDHCI_CD_LVL 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SDHCI_CD_LVL_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SDHCI_WRITE_PROTECT 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SDHCI_DATA_LVL_MASK 0x00F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SDHCI_DATA_LVL_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SDHCI_DATA_0_LVL_MASK 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SDHCI_CMD_LVL 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SDHCI_HOST_CONTROL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SDHCI_CTRL_LED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SDHCI_CTRL_4BITBUS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SDHCI_CTRL_HISPD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SDHCI_CTRL_DMA_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SDHCI_CTRL_SDMA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SDHCI_CTRL_ADMA1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SDHCI_CTRL_ADMA32 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SDHCI_CTRL_ADMA64 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SDHCI_CTRL_ADMA3 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SDHCI_CTRL_8BITBUS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SDHCI_CTRL_CDTEST_INS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SDHCI_CTRL_CDTEST_EN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SDHCI_POWER_CONTROL 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SDHCI_POWER_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SDHCI_POWER_180 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SDHCI_POWER_300 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SDHCI_POWER_330 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SDHCI_BLOCK_GAP_CONTROL 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SDHCI_WAKE_UP_CONTROL 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SDHCI_WAKE_ON_INT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SDHCI_WAKE_ON_INSERT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SDHCI_WAKE_ON_REMOVE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SDHCI_CLOCK_CONTROL 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SDHCI_DIVIDER_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SDHCI_DIVIDER_HI_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SDHCI_DIV_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SDHCI_DIV_MASK_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SDHCI_DIV_HI_MASK 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SDHCI_PROG_CLOCK_MODE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SDHCI_CLOCK_CARD_EN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SDHCI_CLOCK_PLL_EN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SDHCI_CLOCK_INT_STABLE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SDHCI_CLOCK_INT_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SDHCI_TIMEOUT_CONTROL 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SDHCI_SOFTWARE_RESET 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SDHCI_RESET_ALL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SDHCI_RESET_CMD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SDHCI_RESET_DATA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SDHCI_INT_STATUS 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SDHCI_INT_ENABLE 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SDHCI_SIGNAL_ENABLE 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SDHCI_INT_RESPONSE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SDHCI_INT_DATA_END 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SDHCI_INT_BLK_GAP 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SDHCI_INT_DMA_END 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SDHCI_INT_SPACE_AVAIL 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SDHCI_INT_DATA_AVAIL 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SDHCI_INT_CARD_INSERT 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SDHCI_INT_CARD_REMOVE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SDHCI_INT_CARD_INT 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SDHCI_INT_RETUNE 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SDHCI_INT_CQE 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SDHCI_INT_ERROR 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SDHCI_INT_TIMEOUT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SDHCI_INT_CRC 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SDHCI_INT_END_BIT 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SDHCI_INT_INDEX 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SDHCI_INT_DATA_TIMEOUT 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SDHCI_INT_DATA_CRC 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SDHCI_INT_DATA_END_BIT 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SDHCI_INT_BUS_POWER 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SDHCI_INT_AUTO_CMD_ERR 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SDHCI_INT_ADMA_ERROR 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SDHCI_INT_NORMAL_MASK 0x00007FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SDHCI_INT_ERROR_MASK 0xFFFF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SDHCI_INT_AUTO_CMD_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SDHCI_INT_BLK_GAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SDHCI_CQE_INT_ERR_MASK ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SDHCI_AUTO_CMD_STATUS 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SDHCI_AUTO_CMD_TIMEOUT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SDHCI_AUTO_CMD_CRC 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SDHCI_AUTO_CMD_END_BIT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SDHCI_AUTO_CMD_INDEX 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SDHCI_HOST_CONTROL2 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SDHCI_CTRL_UHS_MASK 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SDHCI_CTRL_UHS_SDR12 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SDHCI_CTRL_UHS_SDR25 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SDHCI_CTRL_UHS_SDR50 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SDHCI_CTRL_UHS_SDR104 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SDHCI_CTRL_UHS_DDR50 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SDHCI_CTRL_VDD_180 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SDHCI_CTRL_DRV_TYPE_B 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SDHCI_CTRL_DRV_TYPE_A 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SDHCI_CTRL_DRV_TYPE_C 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SDHCI_CTRL_DRV_TYPE_D 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SDHCI_CTRL_EXEC_TUNING 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SDHCI_CTRL_TUNED_CLK 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SDHCI_CMD23_ENABLE 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SDHCI_CTRL_V4_MODE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SDHCI_CTRL_64BIT_ADDR 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SDHCI_CAPABILITIES 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SDHCI_MAX_BLOCK_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SDHCI_MAX_BLOCK_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SDHCI_CAN_DO_8BIT 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SDHCI_CAN_DO_ADMA2 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SDHCI_CAN_DO_ADMA1 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SDHCI_CAN_DO_HISPD 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SDHCI_CAN_DO_SDMA 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SDHCI_CAN_DO_SUSPEND 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SDHCI_CAN_VDD_330 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SDHCI_CAN_VDD_300 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SDHCI_CAN_VDD_180 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SDHCI_CAN_64BIT_V4 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SDHCI_CAN_64BIT 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SDHCI_CAPABILITIES_1 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SDHCI_SUPPORT_SDR50 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SDHCI_SUPPORT_SDR104 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SDHCI_SUPPORT_DDR50 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SDHCI_DRIVER_TYPE_A 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SDHCI_DRIVER_TYPE_C 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SDHCI_DRIVER_TYPE_D 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SDHCI_USE_SDR50_TUNING 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SDHCI_CAN_DO_ADMA3 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SDHCI_MAX_CURRENT 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SDHCI_MAX_CURRENT_LIMIT GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SDHCI_MAX_CURRENT_MULTIPLIER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* 4C-4F reserved for more max current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SDHCI_SET_ACMD12_ERROR 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SDHCI_SET_INT_ERROR 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SDHCI_ADMA_ERROR 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* 55-57 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SDHCI_ADMA_ADDRESS 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SDHCI_ADMA_ADDRESS_HI 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* 60-FB reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SDHCI_PRESET_FOR_HIGH_SPEED 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SDHCI_PRESET_FOR_SDR12 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SDHCI_PRESET_FOR_SDR25 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SDHCI_PRESET_FOR_SDR50 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SDHCI_PRESET_FOR_SDR104 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SDHCI_PRESET_FOR_DDR50 0x6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SDHCI_PRESET_CLKGEN_SEL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SDHCI_SLOT_INT_STATUS 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SDHCI_HOST_VERSION 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SDHCI_VENDOR_VER_MASK 0xFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SDHCI_VENDOR_VER_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SDHCI_SPEC_VER_MASK 0x00FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SDHCI_SPEC_VER_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SDHCI_SPEC_100 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SDHCI_SPEC_200 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SDHCI_SPEC_300 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SDHCI_SPEC_400 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SDHCI_SPEC_410 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SDHCI_SPEC_420 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * End of controller registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SDHCI_MAX_DIV_SPEC_200 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SDHCI_MAX_DIV_SPEC_300 2046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* ADMA2 32-bit DMA descriptor size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SDHCI_ADMA2_32_DESC_SZ 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* ADMA2 32-bit descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct sdhci_adma2_32_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) __le16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) __le16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } __packed __aligned(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* ADMA2 data alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SDHCI_ADMA2_ALIGN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * alignment for the descriptor table even in 32-bit DMA mode. Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * allocation is at least 8 byte aligned anyway, so just stipulate 8 always.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SDHCI_ADMA2_DESC_ALIGN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * ADMA2 64-bit DMA descriptor size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * According to SD Host Controller spec v4.10, there are two kinds of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Descriptor, if Host Version 4 Enable is set in the Host Control 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * register, 128-bit Descriptor will be selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct sdhci_adma2_64_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) __le16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) __le16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) __le32 addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) __le32 addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) } __packed __aligned(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ADMA2_TRAN_VALID 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define ADMA2_NOP_END_VALID 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define ADMA2_END 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Maximum segments assuming a 512KiB maximum requisition size and a minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * 4KiB page size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SDHCI_MAX_SEGS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Allow for a a command request and a data request at the same time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SDHCI_MAX_MRQS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * However since the start time of the command, the time between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * command and response, and the time between response and start of data is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * not known, set the command transfer time to 10ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) enum sdhci_cookie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) COOKIE_UNMAPPED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct sdhci_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Data set by hardware interface driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) const char *hw_name; /* Hardware bus name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int quirks; /* Deviations from spec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Controller doesn't honor resets unless we touch the clock register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Controller has bad caps bits, but really supports DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SDHCI_QUIRK_FORCE_DMA (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Controller doesn't like to be reset when there is no card inserted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Controller doesn't like clearing the power reg before a change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Controller has flaky internal state so reset it on each ios change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Controller has an unusable DMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SDHCI_QUIRK_BROKEN_DMA (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Controller has an unusable ADMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Controller can only DMA from 32-bit aligned addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Controller can only ADMA chunks that are a multiple of 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Controller needs to be reset after each request to stay stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Controller needs voltage and power writes to happen separately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Controller provides an incorrect timeout value for transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Controller has an issue with buffer bits for small transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Controller does not provide transfer-complete interrupt when not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Controller has unreliable card detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Controller reports inverted write-protect state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Controller has unusable command queue engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SDHCI_QUIRK_BROKEN_CQE (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Controller does not like fast PIO transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Controller does not have a LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define SDHCI_QUIRK_NO_LED (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Controller has to be forced to use block size of 2048 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Controller cannot do multi-block transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Controller can only handle 1-bit data transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Controller needs 10ms delay between applying power and clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Controller uses SDCLK instead of TMCLK for data timeouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Controller reports wrong base clock capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Controller cannot support End Attribute in NOP ADMA descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Controller is missing device caps. Use caps provided by host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define SDHCI_QUIRK_MISSING_CAPS (1<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Controller uses Auto CMD12 command to stop the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Controller treats ADMA descriptors with length 0000h incorrectly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned int quirks2; /* More deviations from spec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* The system physically doesn't support 1.8v, even if the host does */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define SDHCI_QUIRK2_NO_1_8_V (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Controller has a non-standard host control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Controller does not support HS200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Controller does not support DDR50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Controller does not support 64-bit DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* need clear transfer mode register before send cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Capability register bit-63 indicates HS400 support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* forced tuned clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* disable the block count for single block transactions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Controller broken with using ACMD23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Broken Clock divider zero in controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Controller has CRC in 136 bit Command Response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * Disable HW timeout if the requested timeout is more than the maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * obtainable timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * 32-bit block count may not support eMMC where upper bits of CMD23 are used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * for other purposes. Consequently we support 16-bit block count by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * block count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int irq; /* Device IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) void __iomem *ioaddr; /* Mapped address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) phys_addr_t mapbase; /* physical address base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) char *bounce_buffer; /* For packing SDMA reads/writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dma_addr_t bounce_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int bounce_buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) const struct sdhci_ops *ops; /* Low level hw interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Internal data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct mmc_host *mmc; /* MMC structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct mmc_host_ops mmc_host_ops; /* MMC host ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u64 dma_mask; /* custom DMA mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #if IS_ENABLED(CONFIG_LEDS_CLASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct led_classdev led; /* LED control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) char led_name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) spinlock_t lock; /* Mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int flags; /* Host attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unsigned int version; /* SDHCI spec. version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned int max_clk; /* Max possible freq (MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned int timeout_clk; /* Timeout freq (KHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned int clk_mul; /* Clock Muliplier value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned int clock; /* Current clock (MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u8 pwr; /* Current voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) bool runtime_suspended; /* Host is runtime suspended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) bool bus_on; /* Bus power prevents runtime suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) bool preset_enabled; /* Preset is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) bool pending_reset; /* Cmd/data reset is pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) bool irq_wake_enabled; /* IRQ wakeup is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) bool v4_mode; /* Host Version 4 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) bool use_external_dma; /* Host selects to use external DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) bool always_defer_done; /* Always defer to complete requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct mmc_command *cmd; /* Current command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct mmc_command *data_cmd; /* Current data command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct mmc_command *deferred_cmd; /* Deferred command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct mmc_data *data; /* Current data request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned int data_early:1; /* Data finished before cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct sg_mapping_iter sg_miter; /* SG state for PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unsigned int blocks; /* remaining PIO blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int sg_count; /* Mapped sg entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) void *adma_table; /* ADMA descriptor table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) void *align_buffer; /* Bounce buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) size_t adma_table_sz; /* ADMA descriptor table size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) size_t align_buffer_sz; /* Bounce buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dma_addr_t adma_addr; /* Mapped ADMA descr. table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dma_addr_t align_addr; /* Mapped bounce buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned int desc_sz; /* ADMA current descriptor size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct workqueue_struct *complete_wq; /* Request completion wq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct work_struct complete_work; /* Request completion work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct timer_list timer; /* Timer for timeouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct timer_list data_timer; /* Timer for data timeouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct dma_chan *rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct dma_chan *tx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 caps; /* CAPABILITY_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 caps1; /* CAPABILITY_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) bool read_caps; /* Capability flags have been read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) bool sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned int ocr_avail_sdio; /* OCR bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned int ocr_avail_sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned int ocr_avail_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 ocr_mask; /* available voltages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned timing; /* Current timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u32 thread_isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* cached registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) bool cqe_on; /* CQE is operating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 cqe_ier; /* CQE interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u32 cqe_err_ier; /* CQE error interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned int tuning_count; /* Timer count for re-tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned int tuning_mode; /* Re-tuning mode supported by host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) unsigned int tuning_err; /* Error code for re-tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define SDHCI_TUNING_MODE_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define SDHCI_TUNING_MODE_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define SDHCI_TUNING_MODE_3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Delay (ms) between tuning commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int tuning_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int tuning_loop_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* Host SDMA buffer boundary. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u32 sdma_boundary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Host ADMA table count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u32 adma_table_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u64 data_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ANDROID_KABI_RESERVE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned long private[] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct sdhci_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 (*read_l)(struct sdhci_host *host, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u16 (*read_w)(struct sdhci_host *host, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u8 (*read_b)(struct sdhci_host *host, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) void (*write_l)(struct sdhci_host *host, u32 val, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) void (*write_w)(struct sdhci_host *host, u16 val, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) void (*write_b)(struct sdhci_host *host, u8 val, int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) void (*set_clock)(struct sdhci_host *host, unsigned int clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) void (*set_power)(struct sdhci_host *host, unsigned char mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) unsigned short vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u32 (*irq)(struct sdhci_host *host, u32 intmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int (*set_dma_mask)(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int (*enable_dma)(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned int (*get_max_clock)(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned int (*get_min_clock)(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* get_timeout_clock should return clk rate in unit of Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) unsigned int (*get_timeout_clock)(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) void (*set_timeout)(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct mmc_command *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) void (*set_bus_width)(struct sdhci_host *host, int width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) void (*platform_send_init_74_clocks)(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u8 power_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) unsigned int (*get_ro)(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) void (*reset)(struct sdhci_host *host, u8 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) void (*hw_reset)(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) void (*adma_workaround)(struct sdhci_host *host, u32 intmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) void (*card_event)(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) void (*voltage_switch)(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) void (*adma_write_desc)(struct sdhci_host *host, void **desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dma_addr_t addr, int len, unsigned int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) void (*copy_to_bounce_buffer)(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) unsigned int length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) void (*request_done)(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct mmc_request *mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) void (*dump_vendor_regs)(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ANDROID_KABI_RESERVE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (unlikely(host->ops->write_l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) host->ops->write_l(host, val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) writel(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (unlikely(host->ops->write_w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) host->ops->write_w(host, val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) writew(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (unlikely(host->ops->write_b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) host->ops->write_b(host, val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) writeb(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (unlikely(host->ops->read_l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return host->ops->read_l(host, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return readl(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (unlikely(host->ops->read_w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return host->ops->read_w(host, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return readw(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (unlikely(host->ops->read_b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return host->ops->read_b(host, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return readb(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) writel(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) writew(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) writeb(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return readl(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return readw(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return readb(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) void sdhci_free_host(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static inline void *sdhci_priv(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return host->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) void sdhci_card_detect(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) const u32 *caps, const u32 *caps1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) int sdhci_setup_host(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) void sdhci_cleanup_host(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) int __sdhci_add_host(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int sdhci_add_host(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) void sdhci_remove_host(struct sdhci_host *host, int dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static inline void sdhci_read_caps(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) __sdhci_read_caps(host, NULL, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) unsigned int *actual_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) unsigned short vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) unsigned char mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) unsigned short vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) unsigned short vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) void sdhci_set_bus_width(struct sdhci_host *host, int width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) void sdhci_reset(struct sdhci_host *host, u8 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct mmc_ios *ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dma_addr_t addr, int len, unsigned int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) int sdhci_suspend_host(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int sdhci_resume_host(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int sdhci_runtime_suspend_host(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) void sdhci_cqe_enable(struct mmc_host *mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int *data_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) void sdhci_dumpregs(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) void sdhci_enable_v4_mode(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) void sdhci_start_tuning(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) void sdhci_end_tuning(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) void sdhci_reset_tuning(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) void sdhci_send_tuning(struct sdhci_host *host, u32 opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) void sdhci_switch_external_dma(struct sdhci_host *host, bool en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #endif /* __SDHCI_HW_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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