^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Marvell, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Hu Ziji <huziji@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Date: 2016-8-24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef SDHCI_XENON_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define SDHCI_XENON_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Register Offset of Xenon SDHC self-defined register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define XENON_SYS_CFG_INFO 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define XENON_SLOT_TYPE_SDIO_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define XENON_NR_SUPPORTED_SLOT_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define XENON_SYS_OP_CTRL 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define XENON_AUTO_CLKGATE_DISABLE_MASK BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define XENON_SLOT_ENABLE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define XENON_SYS_EXT_OP_CTRL 0x010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define XENON_MASK_CMD_CONFLICT_ERR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define XENON_SLOT_OP_STATUS_CTRL 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define XENON_TUN_CONSECUTIVE_TIMES_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define XENON_TUN_CONSECUTIVE_TIMES_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define XENON_TUN_CONSECUTIVE_TIMES 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define XENON_TUNING_STEP_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XENON_TUNING_STEP_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XENON_TUNING_STEP_DIVIDER BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define XENON_SLOT_EMMC_CTRL 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XENON_ENABLE_RESP_STROBE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define XENON_ENABLE_DATA_STROBE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define XENON_SLOT_RETUNING_REQ_CTRL 0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* retuning compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define XENON_RETUNING_COMPATIBLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define XENON_SLOT_EXT_PRESENT_STATE 0x014C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XENON_DLL_LOCK_STATE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define XENON_SLOT_DLL_CUR_DLY_VAL 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Tuning Parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define XENON_TMR_RETUN_NO_PRESENT 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XENON_DEF_TUNING_COUNT 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define XENON_DEFAULT_SDCLK_FREQ 400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define XENON_LOWEST_SDCLK_FREQ 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Xenon specific Mode Select value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define XENON_CTRL_HS200 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define XENON_CTRL_HS400 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct xenon_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned char tuning_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* idx of SDHC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 sdhc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * eMMC/SD/SDIO require different register settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Xenon driver has to recognize card type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * before mmc_host->card is not available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * This field records the card type during init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * It is updated in xenon_init_card().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * It is only valid during initialization after it is updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Do not access this variable in normal transfers after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * initialization completes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int init_card_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * The bus_width, timing, and clock fields in below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * record the current ios setting of Xenon SDHC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Driver will adjust PHY setting if any change to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * ios affects PHY timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned char bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned char timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct clk *axi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Contains board-specific PHY parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * passed from device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void *phy_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct xenon_emmc_phy_regs *emmc_phy_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) bool restore_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int xenon_phy_parse_dt(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) void xenon_soc_pad_ctrl(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned char signal_voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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