^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Marvell Xenon SDHC as a platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Marvell, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Hu Ziji <huziji@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Date: 2016-8-24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Inspired by Jisheng Zhang <jszhang@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Special thanks to Video BG4 project team.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "sdhci-xenon.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static int xenon_enable_internal_clk(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ktime_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) reg |= SDHCI_CLOCK_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Wait max 20 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) timeout = ktime_add_ms(ktime_get(), 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) bool timedout = ktime_after(ktime_get(), timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (reg & SDHCI_CLOCK_INT_STABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (timedout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) usleep_range(900, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Set SDCLK-off-while-idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned char sdhc_id, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Get the bit shift basing on the SDHC index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mask = (0x1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) reg |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) reg &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Enable/Disable the Auto Clock Gating function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void xenon_set_acg(struct sdhci_host *host, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) reg &= ~XENON_AUTO_CLKGATE_DISABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) reg |= XENON_AUTO_CLKGATE_DISABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Enable this SDHC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void xenon_enable_sdhc(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned char sdhc_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) reg |= (BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Force to clear BUS_TEST to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * skip bus_test_pre and bus_test_post
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Disable this SDHC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void xenon_disable_sdhc(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned char sdhc_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) reg = sdhci_readl(host, XENON_SYS_OP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) reg &= ~(BIT(sdhc_id) << XENON_SLOT_ENABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) sdhci_writel(host, reg, XENON_SYS_OP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Enable Parallel Transfer Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned char sdhc_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) reg |= BIT(sdhc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Mask command conflict error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void xenon_mask_cmd_conflict_err(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg |= XENON_MASK_CMD_CONFLICT_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) sdhci_writel(host, reg, XENON_SYS_EXT_OP_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void xenon_retune_setup(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Disable the Re-Tuning Request functionality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) reg &= ~XENON_RETUNING_COMPATIBLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) sdhci_writel(host, reg, XENON_SLOT_RETUNING_REQ_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Disable the Re-tuning Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) reg &= ~SDHCI_INT_RETUNE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) reg = sdhci_readl(host, SDHCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) reg &= ~SDHCI_INT_RETUNE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) sdhci_writel(host, reg, SDHCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Force to use Tuning Mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) host->tuning_mode = SDHCI_TUNING_MODE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Set re-tuning period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) host->tuning_count = 1 << (priv->tuning_count - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Operations inside struct sdhci_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void xenon_reset_exit(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned char sdhc_id, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Only SOFTWARE RESET ALL will clear the register setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!(mask & SDHCI_RESET_ALL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Disable tuning request and auto-retuning again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) xenon_retune_setup(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * The ACG should be turned off at the early init time, in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * to solve a possible issues with the 1.8V regulator stabilization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * The feature is enabled in later stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) xenon_set_acg(host, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) xenon_set_sdclk_off_idle(host, sdhc_id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) xenon_mask_cmd_conflict_err(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void xenon_reset(struct sdhci_host *host, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) sdhci_reset(host, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) xenon_reset_exit(host, priv->sdhc_id, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Xenon defines different values for HS200 and HS400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * in Host_Control_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void xenon_set_uhs_signaling(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u16 ctrl_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Select Bus Speed Mode for host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (timing == MMC_TIMING_MMC_HS200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ctrl_2 |= XENON_CTRL_HS200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) else if (timing == MMC_TIMING_UHS_SDR104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) else if (timing == MMC_TIMING_UHS_SDR12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) else if (timing == MMC_TIMING_UHS_SDR25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) else if (timing == MMC_TIMING_UHS_SDR50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) else if ((timing == MMC_TIMING_UHS_DDR50) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) (timing == MMC_TIMING_MMC_DDR52))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) else if (timing == MMC_TIMING_MMC_HS400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ctrl_2 |= XENON_CTRL_HS400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void xenon_set_power(struct sdhci_host *host, unsigned char mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned short vdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 pwr = host->pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) sdhci_set_power_noreg(host, mode, vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (host->pwr == pwr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (host->pwr == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) vdd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (!IS_ERR(mmc->supply.vmmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void xenon_voltage_switch(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Wait for 5ms after set 1.8V signal enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) usleep_range(5000, 5500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * For some reason the controller's Host Control2 register reports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * the bit representing 1.8V signaling as 0 when read after it was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * written as 1. Subsequent read reports 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Since this may cause some issues, do an empty read of the Host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * Control2 register here to circumvent this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct sdhci_ops sdhci_xenon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .voltage_switch = xenon_voltage_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .set_power = xenon_set_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .reset = xenon_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .set_uhs_signaling = xenon_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .get_max_clock = sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .ops = &sdhci_xenon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * Xenon Specific Operations in mmc_host_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * HS400/HS200/eMMC HS doesn't have Preset Value register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * However, sdhci_set_ios will read HS400/HS200 Preset register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * Disable Preset Value register for HS400/HS200.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * eMMC HS with preset_enabled set will trigger a bug in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * get_preset_value().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if ((ios->timing == MMC_TIMING_MMC_HS400) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) (ios->timing == MMC_TIMING_MMC_HS200) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) (ios->timing == MMC_TIMING_MMC_HS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) host->preset_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) host->flags &= ~SDHCI_PV_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) sdhci_set_ios(mmc, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) xenon_phy_adj(host, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (host->clock > XENON_DEFAULT_SDCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Before SD/SDIO set signal voltage, SD bus clock should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * disabled. However, sdhci_set_clock will also disable the Internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * clock in mmc_set_signal_voltage().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Thus here manually enable internal clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * After switch completes, it is unnecessary to disable internal clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * since keeping internal clock active obeys SD spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) xenon_enable_internal_clk(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) xenon_soc_pad_ctrl(host, ios->signal_voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * If Vqmmc is fixed on platform, vqmmc regulator should be unavailable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Thus SDHCI_CTRL_VDD_180 bit might not work then.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Skip the standard voltage switch to avoid any issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (PTR_ERR(mmc->supply.vqmmc) == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return sdhci_start_signal_voltage_switch(mmc, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Update card type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * priv->init_card_type will be used in PHY timing adjustment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Update card type*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) priv->init_card_type = card->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (host->timing == MMC_TIMING_UHS_DDR50 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) host->timing == MMC_TIMING_MMC_DDR52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Currently force Xenon driver back to support mode 1 only,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * even though Xenon might claim to support mode 2 or mode 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * It requires more time to test mode 2/mode 3 on more platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (host->tuning_mode != SDHCI_TUNING_MODE_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) xenon_retune_setup(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return sdhci_execute_tuning(mmc, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u8 sdhc_id = priv->sdhc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) sdhci_enable_sdio_irq(mmc, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Set SDIO Card Inserted indication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * to enable detecting SDIO async irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) reg |= (1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Clear SDIO Card Inserted indication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) reg = sdhci_readl(host, XENON_SYS_CFG_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) reg &= ~(1 << (sdhc_id + XENON_SLOT_TYPE_SDIO_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) sdhci_writel(host, reg, XENON_SYS_CFG_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static void xenon_replace_mmc_host_ops(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) host->mmc_host_ops.set_ios = xenon_set_ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) host->mmc_host_ops.start_signal_voltage_switch =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) xenon_start_signal_voltage_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) host->mmc_host_ops.init_card = xenon_init_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) host->mmc_host_ops.execute_tuning = xenon_execute_tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Parse Xenon specific DT properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * sdhc-id: the index of current SDHC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * Refer to XENON_SYS_CFG_INFO register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * tun-count: the interval between re-tuning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int xenon_probe_dt(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct sdhci_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 sdhc_id, nr_sdhc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 tuning_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Disable HS200 on Armada AP806 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (of_device_is_compatible(np, "marvell,armada-ap806-sdhci"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) sdhc_id = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) nr_sdhc = sdhci_readl(host, XENON_SYS_CFG_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) nr_sdhc &= XENON_NR_SUPPORTED_SLOT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (unlikely(sdhc_id > nr_sdhc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) sdhc_id, nr_sdhc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) priv->sdhc_id = sdhc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) tuning_count = XENON_DEF_TUNING_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (!of_property_read_u32(np, "marvell,xenon-tun-count",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) &tuning_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (unlikely(tuning_count >= XENON_TMR_RETUN_NO_PRESENT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) XENON_DEF_TUNING_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) tuning_count = XENON_DEF_TUNING_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) priv->tuning_count = tuning_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return xenon_phy_parse_dt(np, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int xenon_sdhc_prepare(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u8 sdhc_id = priv->sdhc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Enable SDHC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) xenon_enable_sdhc(host, sdhc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Enable ACG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) xenon_set_acg(host, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Enable Parallel Transfer Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) xenon_enable_sdhc_parallel_tran(host, sdhc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Disable SDCLK-Off-While-Idle before card init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) xenon_set_sdclk_off_idle(host, sdhc_id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) xenon_mask_cmd_conflict_err(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static void xenon_sdhc_unprepare(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u8 sdhc_id = priv->sdhc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* disable SDHC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) xenon_disable_sdhc(host, sdhc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int xenon_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct xenon_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) sizeof(struct xenon_priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Link Xenon specific mmc_host_ops function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * to replace standard ones in sdhci_ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) xenon_replace_mmc_host_ops(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (IS_ERR(pltfm_host->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) err = PTR_ERR(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) goto free_pltfm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) err = clk_prepare_enable(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) goto free_pltfm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) priv->axi_clk = devm_clk_get(&pdev->dev, "axi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (IS_ERR(priv->axi_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) err = PTR_ERR(priv->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (err == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) err = clk_prepare_enable(priv->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) err = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) goto err_clk_axi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) sdhci_get_of_property(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) xenon_set_acg(host, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Xenon specific dt parse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) err = xenon_probe_dt(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto err_clk_axi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) err = xenon_sdhc_prepare(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) goto err_clk_axi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pm_suspend_ignore_children(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) err = sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) goto remove_sdhc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pm_runtime_put_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) remove_sdhc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) xenon_sdhc_unprepare(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) err_clk_axi:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) clk_disable_unprepare(priv->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) clk_disable_unprepare(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) free_pltfm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int xenon_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct sdhci_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) sdhci_remove_host(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) xenon_sdhc_unprepare(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) clk_disable_unprepare(priv->axi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) clk_disable_unprepare(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int xenon_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) priv->restore_needed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int xenon_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) ret = sdhci_runtime_suspend_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (host->tuning_mode != SDHCI_TUNING_MODE_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) mmc_retune_needed(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) clk_disable_unprepare(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * Need to update the priv->clock here, or when runtime resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * back, phy don't aware the clock change and won't adjust phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * which will cause cmd err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) priv->clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int xenon_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ret = clk_prepare_enable(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dev_err(dev, "can't enable mainck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (priv->restore_needed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ret = xenon_sdhc_prepare(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) priv->restore_needed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ret = sdhci_runtime_resume_host(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) clk_disable_unprepare(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const struct dev_pm_ops sdhci_xenon_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) SET_SYSTEM_SLEEP_PM_OPS(xenon_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) SET_RUNTIME_PM_OPS(xenon_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) xenon_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const struct of_device_id sdhci_xenon_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { .compatible = "marvell,armada-ap806-sdhci",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { .compatible = "marvell,armada-cp110-sdhci",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) { .compatible = "marvell,armada-3700-sdhci",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static struct platform_driver sdhci_xenon_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .name = "xenon-sdhci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .of_match_table = sdhci_xenon_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .pm = &sdhci_xenon_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .probe = xenon_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .remove = xenon_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) module_platform_driver(sdhci_xenon_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags