^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support for SDHCI on STMicroelectronics SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 STMicroelectronics Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Contributors: Peter Griffin <peter.griffin@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on sdhci-cns3xxx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct st_mmc_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk *icnclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void __iomem *top_ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* MMCSS glue logic to setup the HC on some ST SoCs (e.g. STiH407 family) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ST_MMC_CCONFIG_REG_1 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ST_MMC_CCONFIG_ASYNC_WAKEUP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ST_MMC_CCONFIG_1_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ((ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) (ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) (ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ST_MMC_CCONFIG_REG_2 0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ST_MMC_CCONFIG_HIGH_SPEED BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ST_MMC_CCONFIG_ADMA2 BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ST_MMC_CCONFIG_8BIT BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ST_MMC_CCONFIG_MAX_BLK_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MAX_BLK_LEN_1024 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MAX_BLK_LEN_2048 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BASE_CLK_FREQ_200 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BASE_CLK_FREQ_100 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BASE_CLK_FREQ_50 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ST_MMC_CCONFIG_2_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) (ST_MMC_CCONFIG_HIGH_SPEED | ST_MMC_CCONFIG_ADMA2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ST_MMC_CCONFIG_8BIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) (MAX_BLK_LEN_1024 << ST_MMC_CCONFIG_MAX_BLK_LEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ST_MMC_CCONFIG_REG_3 0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ST_MMC_CCONFIG_EMMC_SLOT_TYPE BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ST_MMC_CCONFIG_64BIT BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ST_MMC_CCONFIG_1P8_VOLT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ST_MMC_CCONFIG_3P0_VOLT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ST_MMC_CCONFIG_3P3_VOLT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ST_MMC_CCONFIG_SUSP_RES_SUPPORT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ST_MMC_CCONFIG_SDMA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ST_MMC_CCONFIG_3_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) (ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ST_MMC_CCONFIG_3P3_VOLT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ST_MMC_CCONFIG_SUSP_RES_SUPPORT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ST_MMC_CCONFIG_SDMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ST_MMC_CCONFIG_REG_4 0x40c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ST_MMC_CCONFIG_D_DRIVER BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ST_MMC_CCONFIG_C_DRIVER BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ST_MMC_CCONFIG_A_DRIVER BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ST_MMC_CCONFIG_DDR50 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ST_MMC_CCONFIG_SDR104 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ST_MMC_CCONFIG_SDR50 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ST_MMC_CCONFIG_4_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ST_MMC_CCONFIG_REG_5 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ST_MMC_CCONFIG_TUNING_FOR_SDR50 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RETUNING_TIMER_CNT_MAX 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ST_MMC_CCONFIG_5_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* I/O configuration for Arasan IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ST_MMC_GP_OUTPUT 0x450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ST_MMC_GP_OUTPUT_CD BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ST_MMC_STATUS_R 0x460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ST_TOP_MMC_DLY_FIX_OFF(x) (x - 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* TOP config registers to manage static and dynamic delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ST_TOP_MMC_TX_CLK_DLY ST_TOP_MMC_DLY_FIX_OFF(0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ST_TOP_MMC_RX_CLK_DLY ST_TOP_MMC_DLY_FIX_OFF(0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* MMC delay control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ST_TOP_MMC_DLY_CTRL ST_TOP_MMC_DLY_FIX_OFF(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_CMD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_PH_SEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ST_TOP_MMC_DLY_CTRL_RX_DLL_ENABLE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ST_TOP_MMC_START_DLL_LOCK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* register to provide the phase-shift value for DLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ST_TOP_MMC_TX_DLL_STEP_DLY ST_TOP_MMC_DLY_FIX_OFF(0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ST_TOP_MMC_RX_DLL_STEP_DLY ST_TOP_MMC_DLY_FIX_OFF(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ST_TOP_MMC_RX_CMD_STEP_DLY ST_TOP_MMC_DLY_FIX_OFF(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* phase shift delay on the tx clk 2.188ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ST_TOP_MMC_TX_DLL_STEP_DLY_VALID 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ST_TOP_MMC_DLY_MAX 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ST_TOP_MMC_DYN_DLY_CONF \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) (ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ST_TOP_MMC_START_DLL_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * For clock speeds greater than 90MHz, we need to check that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * DLL procedure has finished before switching to ultra-speed modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_TO_CHECK_DLL_LOCK 90000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline void st_mmcss_set_static_delay(void __iomem *ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writel_relaxed(ST_TOP_MMC_DLY_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ioaddr + ST_TOP_MMC_TX_CLK_DLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * st_mmcss_cconfig: configure the Arasan HC inside the flashSS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @np: dt device node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @host: sdhci host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * Description: this function is to configure the Arasan host controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * On some ST SoCs, i.e. STiH407 family, the MMC devices inside a dedicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * flashSS sub-system which needs to be configured to be compliant to eMMC 4.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * or eMMC4.3. This has to be done before registering the sdhci host.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void st_mmcss_cconfig(struct device_node *np, struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct mmc_host *mhost = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 cconf2, cconf3, cconf4, cconf5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!of_device_is_compatible(np, "st,sdhci-stih407"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) cconf2 = ST_MMC_CCONFIG_2_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) cconf3 = ST_MMC_CCONFIG_3_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) cconf4 = ST_MMC_CCONFIG_4_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cconf5 = ST_MMC_CCONFIG_5_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) writel_relaxed(ST_MMC_CCONFIG_1_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) host->ioaddr + ST_MMC_CCONFIG_REG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Set clock frequency, default to 50MHz if max-frequency is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * provided */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) switch (mhost->f_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) case 200000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clk_set_rate(pltfm_host->clk, mhost->f_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) cconf2 |= BASE_CLK_FREQ_200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case 100000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) clk_set_rate(pltfm_host->clk, mhost->f_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) cconf2 |= BASE_CLK_FREQ_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) clk_set_rate(pltfm_host->clk, 50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) cconf2 |= BASE_CLK_FREQ_50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) writel_relaxed(cconf2, host->ioaddr + ST_MMC_CCONFIG_REG_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!mmc_card_is_removable(mhost))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cconf3 |= ST_MMC_CCONFIG_EMMC_SLOT_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* CARD _D ET_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writel_relaxed(ST_MMC_GP_OUTPUT_CD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) host->ioaddr + ST_MMC_GP_OUTPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (mhost->caps & MMC_CAP_UHS_SDR50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* use 1.8V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) cconf3 |= ST_MMC_CCONFIG_1P8_VOLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) cconf4 |= ST_MMC_CCONFIG_SDR50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Use tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) cconf5 |= ST_MMC_CCONFIG_TUNING_FOR_SDR50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Max timeout for retuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) cconf5 |= RETUNING_TIMER_CNT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (mhost->caps & MMC_CAP_UHS_SDR104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * SDR104 implies the HC can support HS200 mode, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * it's mandatory to use 1.8V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) cconf3 |= ST_MMC_CCONFIG_1P8_VOLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) cconf4 |= ST_MMC_CCONFIG_SDR104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Max timeout for retuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) cconf5 |= RETUNING_TIMER_CNT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (mhost->caps & MMC_CAP_UHS_DDR50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) cconf4 |= ST_MMC_CCONFIG_DDR50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) writel_relaxed(cconf3, host->ioaddr + ST_MMC_CCONFIG_REG_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) writel_relaxed(cconf4, host->ioaddr + ST_MMC_CCONFIG_REG_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel_relaxed(cconf5, host->ioaddr + ST_MMC_CCONFIG_REG_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static inline void st_mmcss_set_dll(void __iomem *ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel_relaxed(ST_TOP_MMC_DYN_DLY_CONF, ioaddr + ST_TOP_MMC_DLY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writel_relaxed(ST_TOP_MMC_TX_DLL_STEP_DLY_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ioaddr + ST_TOP_MMC_TX_DLL_STEP_DLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int st_mmcss_lock_dll(void __iomem *ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned long curr, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned long finish = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Checks if the DLL procedure is finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) curr = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) value = readl(ioaddr + ST_MMC_STATUS_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (value & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) } while (!time_after_eq(curr, finish));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct st_mmc_platform_data *pdata = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (host->clock > CLK_TO_CHECK_DLL_LOCK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) st_mmcss_set_dll(pdata->top_ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = st_mmcss_lock_dll(host->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void sdhci_st_set_uhs_signaling(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int uhs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct st_mmc_platform_data *pdata = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Select Bus Speed Mode for host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) switch (uhs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Set V18_EN -- UHS modes do not work without this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * does not change signaling voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case MMC_TIMING_UHS_SDR12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) st_mmcss_set_static_delay(pdata->top_ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ctrl_2 |= SDHCI_CTRL_UHS_SDR12 | SDHCI_CTRL_VDD_180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case MMC_TIMING_UHS_SDR25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) st_mmcss_set_static_delay(pdata->top_ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ctrl_2 |= SDHCI_CTRL_UHS_SDR25 | SDHCI_CTRL_VDD_180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case MMC_TIMING_UHS_SDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) st_mmcss_set_static_delay(pdata->top_ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = sdhci_st_set_dll_for_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case MMC_TIMING_UHS_SDR104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case MMC_TIMING_MMC_HS200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) st_mmcss_set_static_delay(pdata->top_ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = sdhci_st_set_dll_for_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case MMC_TIMING_UHS_DDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case MMC_TIMING_MMC_DDR52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) st_mmcss_set_static_delay(pdata->top_ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dev_warn(mmc_dev(host->mmc), "Error setting dll for clock "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "(uhs %d)\n", uhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case SDHCI_CAPABILITIES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = readl_relaxed(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Support 3.3V and 1.8V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret &= ~SDHCI_CAN_VDD_300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = readl_relaxed(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct sdhci_ops sdhci_st_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .get_max_clock = sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .read_l = sdhci_st_readl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .set_uhs_signaling = sdhci_st_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct sdhci_pltfm_data sdhci_st_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .ops = &sdhci_st_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) SDHCI_QUIRK_NO_HISPD_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) SDHCI_QUIRK2_STOP_WITH_TC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int sdhci_st_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct st_mmc_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct clk *clk, *icnclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u16 host_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) clk = devm_clk_get(&pdev->dev, "mmc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(&pdev->dev, "Peripheral clk not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* ICN clock isn't compulsory, but use it if it's provided. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) icnclk = devm_clk_get(&pdev->dev, "icn");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (IS_ERR(icnclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) icnclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (IS_ERR(rstc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) rstc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) reset_control_deassert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) host = sdhci_pltfm_init(pdev, &sdhci_st_pdata, sizeof(*pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (IS_ERR(host)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_err(&pdev->dev, "Failed sdhci_pltfm_init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) goto err_pltfm_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pdata = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pdata->rstc = rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dev_err(&pdev->dev, "Failed mmc_of_parse\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) goto err_of;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(&pdev->dev, "Failed to prepare clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto err_of;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = clk_prepare_enable(icnclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_err(&pdev->dev, "Failed to prepare icn clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) goto err_icnclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Configure the FlashSS Top registers for setting eMMC TX/RX delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "top-mmc-delay");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pdata->top_ioaddr = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (IS_ERR(pdata->top_ioaddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_warn(&pdev->dev, "FlashSS Top Dly registers not available");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pdata->top_ioaddr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pltfm_host->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pdata->icnclk = icnclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* Configure the Arasan HC inside the flashSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) st_mmcss_cconfig(np, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_info(&pdev->dev, "SDHCI ST Initialised: Host Version: 0x%x Vendor Version 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ((host_version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ((host_version & SDHCI_VENDOR_VER_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) SDHCI_VENDOR_VER_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) clk_disable_unprepare(icnclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) err_icnclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) err_of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) err_pltfm_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (rstc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) reset_control_assert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int sdhci_st_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct sdhci_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct st_mmc_platform_data *pdata = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct reset_control *rstc = pdata->rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = sdhci_pltfm_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) clk_disable_unprepare(pdata->icnclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (rstc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) reset_control_assert(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int sdhci_st_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct st_mmc_platform_data *pdata = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (host->tuning_mode != SDHCI_TUNING_MODE_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) mmc_retune_needed(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = sdhci_suspend_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (pdata->rstc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) reset_control_assert(pdata->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) clk_disable_unprepare(pdata->icnclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) clk_disable_unprepare(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int sdhci_st_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct st_mmc_platform_data *pdata = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = clk_prepare_enable(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ret = clk_prepare_enable(pdata->icnclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) clk_disable_unprepare(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (pdata->rstc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) reset_control_deassert(pdata->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) st_mmcss_cconfig(np, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return sdhci_resume_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static SIMPLE_DEV_PM_OPS(sdhci_st_pmops, sdhci_st_suspend, sdhci_st_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const struct of_device_id st_sdhci_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) { .compatible = "st,sdhci" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MODULE_DEVICE_TABLE(of, st_sdhci_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static struct platform_driver sdhci_st_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .probe = sdhci_st_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .remove = sdhci_st_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .name = "sdhci-st",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .pm = &sdhci_st_pmops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .of_match_table = of_match_ptr(st_sdhci_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) module_platform_driver(sdhci_st_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MODULE_DESCRIPTION("SDHCI driver for STMicroelectronics SoCs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MODULE_ALIAS("platform:sdhci-st");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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