^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Secure Digital Host Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2018 Spreadtrum, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "mmc_hsq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* SDHCI_ARGUMENT2 register high 16bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SDHCI_SPRD_REG_32_DLL_CFG 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SDHCI_SPRD_DLL_EN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SDHCI_SPRD_REG_32_DLL_DLY 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SDHCI_SPRD_REG_DEBOUNCE 0x28C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SDHCI_SPRD_BIT_DLL_BAK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SDHCI_SPRD_BIT_DLL_VAL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* SDHCI_HOST_CONTROL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SDHCI_SPRD_CTRL_HS200 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SDHCI_SPRD_CTRL_HS400 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SDHCI_SPRD_CTRL_HS400ES 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * reserved, and only used on Spreadtrum's design, the hardware cannot work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * if this bit is cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * 1 : normal work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * 0 : hardware reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SDHCI_HW_RESET_CARD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SDHCI_SPRD_MAX_CUR 0xFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SDHCI_SPRD_CLK_MAX_DIV 1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SDHCI_SPRD_CLK_DEF_RATE 26000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SDHCI_SPRD_PHY_DLL_CLK 52000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct sdhci_sprd_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clk *clk_sdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct clk *clk_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct clk *clk_2x_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct pinctrl_state *pins_uhs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 base_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int flags; /* backup of host attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 phy_delay[MMC_TIMING_MMC_HS400 + 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct sdhci_sprd_phy_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) const char *property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void sdhci_sprd_init_config(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* set dll backup mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (unlikely(reg == SDHCI_MAX_CURRENT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return SDHCI_SPRD_MAX_CUR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return readl_relaxed(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (unlikely(reg == SDHCI_MAX_CURRENT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel_relaxed(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (unlikely(reg == SDHCI_BLOCK_COUNT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) writew_relaxed(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * standard specification, sdhci_reset() write this register directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * without checking other reserved bits, that will clear BIT(3) which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * is defined as hardware reset on Spreadtrum's platform and clearing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * it by mistake will lead the card not work. So here we need to work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * around it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) val |= SDHCI_HW_RESET_CARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writeb_relaxed(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ctrl &= ~SDHCI_CLOCK_CARD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ctrl |= SDHCI_CLOCK_CARD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 dll_dly_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dll_dly_offset |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dll_dly_offset &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* select 2x clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (base_clk <= clk * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) div = (u32) (base_clk / (clk * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if ((base_clk / div) > (clk * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (div > SDHCI_SPRD_CLK_MAX_DIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) div = SDHCI_SPRD_CLK_MAX_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (div % 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) div = (div + 1) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) div = div / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 div, val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) sdhci_enable_clk(host, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* enable auto gate sdhc_enable_auto_gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (mask != (val & mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* wait 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) usleep_range(1000, 1250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* wait 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) usleep_range(1000, 1250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) tmp |= SDHCI_SPRD_DLL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* wait 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) usleep_range(1000, 1250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) bool en = false, clk_changed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (clock == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } else if (clock != host->clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sdhci_sprd_sd_clk_off(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) _sdhci_sprd_set_clock(host, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (clock <= 400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) en = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) clk_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) _sdhci_sprd_set_clock(host, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * According to the Spreadtrum SD host specification, when we changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * the clock to be more than 52M, we should enable the PHY DLL which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * is used to track the clock frequency to make the clock work more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * stable. Otherwise deviation may occur of the higher clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) sdhci_sprd_enable_phy_dll(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 *p = sprd_host->phy_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u16 ctrl_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (timing == host->timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Select Bus Speed Mode for host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) switch (timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case MMC_TIMING_UHS_SDR12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case MMC_TIMING_MMC_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case MMC_TIMING_SD_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case MMC_TIMING_UHS_SDR25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case MMC_TIMING_UHS_SDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case MMC_TIMING_UHS_SDR104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case MMC_TIMING_UHS_DDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case MMC_TIMING_MMC_DDR52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case MMC_TIMING_MMC_HS200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case MMC_TIMING_MMC_HS400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (!mmc->ios.enhanced_strobe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void sdhci_sprd_hw_reset(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * Note: don't use sdhci_writeb() API here since it is redirected to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * sdhci_sprd_writeb() in which we have a workaround for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * not be cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) val &= ~SDHCI_HW_RESET_CARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* wait for 10 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) val |= SDHCI_HW_RESET_CARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) usleep_range(300, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* The Spredtrum controller actual maximum timeout count is 1 << 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 1 << 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void sdhci_sprd_request_done(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Validate if the request was from software queue firstly. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (mmc_hsq_finalize_request(host->mmc, mrq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct sdhci_ops sdhci_sprd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .read_l = sdhci_sprd_readl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .write_l = sdhci_sprd_writel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .write_w = sdhci_sprd_writew,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .write_b = sdhci_sprd_writeb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .set_clock = sdhci_sprd_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .get_max_clock = sdhci_sprd_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .get_min_clock = sdhci_sprd_get_min_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .hw_reset = sdhci_sprd_hw_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .get_ro = sdhci_sprd_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .request_done = sdhci_sprd_request_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * From version 4.10 onward, ARGUMENT2 register is also as 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * block count register which doesn't support stuff bits of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * CMD23 argument on Spreadtrum's sd host controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (host->version >= SDHCI_SPEC_410 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) (host->flags & SDHCI_AUTO_CMD23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) host->flags &= ~SDHCI_AUTO_CMD23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) sdhci_sprd_check_auto_cmd23(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) sdhci_request(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int sdhci_sprd_request_atomic(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) sdhci_sprd_check_auto_cmd23(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return sdhci_request_atomic(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!IS_ERR(mmc->supply.vqmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ret = mmc_regulator_set_vqmmc(mmc, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pr_err("%s: Switching signalling voltage failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) mmc_hostname(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (IS_ERR(sprd_host->pinctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) switch (ios->signal_voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case MMC_SIGNAL_VOLTAGE_180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = pinctrl_select_state(sprd_host->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) sprd_host->pins_uhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pr_err("%s: failed to select uhs pin state\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) mmc_hostname(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) case MMC_SIGNAL_VOLTAGE_330:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = pinctrl_select_state(sprd_host->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) sprd_host->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pr_err("%s: failed to select default pin state\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) mmc_hostname(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* Wait for 300 ~ 500 us for pin state stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) usleep_range(300, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u32 *p = sprd_host->phy_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u16 ctrl_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!ios->enhanced_strobe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) sdhci_sprd_sd_clk_off(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Set HS400 enhanced strobe mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sdhci_sprd_sd_clk_on(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Set the PHY DLL delay value for HS400 enhanced strobe mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SDHCI_SPRD_REG_32_DLL_DLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 *p = sprd_host->phy_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int ret, i, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 val[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = of_property_read_u32_array(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) sdhci_sprd_phy_cfgs[i].property, val, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) index = sdhci_sprd_phy_cfgs[i].timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) SDHCI_QUIRK_MISSING_CAPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) SDHCI_QUIRK2_USE_32BIT_BLK_CNT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .ops = &sdhci_sprd_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int sdhci_sprd_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct sdhci_sprd_host *sprd_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct mmc_hsq *hsq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) host->dma_mask = DMA_BIT_MASK(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) pdev->dev.dma_mask = &host->dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) host->mmc_host_ops.request = sdhci_sprd_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) host->mmc_host_ops.hs400_enhanced_strobe =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) sdhci_sprd_hs400_enhanced_strobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * We can not use the standard ops to change and detect the voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * signal for Spreadtrum SD host controller, since our voltage regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * for I/O is fixed in hardware, that means we do not need control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * the standard SD host controller to change the I/O voltage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) host->mmc_host_ops.start_signal_voltage_switch =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) sdhci_sprd_voltage_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) MMC_CAP_WAIT_WHILE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ret = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) goto pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (!mmc_card_is_removable(host->mmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) host->always_defer_done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) sprd_host = TO_SPRD_HOST(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (!IS_ERR(sprd_host->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) sprd_host->pins_uhs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (IS_ERR(sprd_host->pins_uhs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ret = PTR_ERR(sprd_host->pins_uhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) goto pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) sprd_host->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) pinctrl_lookup_state(sprd_host->pinctrl, "default");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (IS_ERR(sprd_host->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ret = PTR_ERR(sprd_host->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) goto pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) clk = devm_clk_get(&pdev->dev, "sdio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) goto pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) sprd_host->clk_sdio = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (!sprd_host->base_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) clk = devm_clk_get(&pdev->dev, "enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) goto pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) sprd_host->clk_enable = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) clk = devm_clk_get(&pdev->dev, "2x_enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) sprd_host->clk_2x_enable = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = clk_prepare_enable(sprd_host->clk_sdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) goto pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret = clk_prepare_enable(sprd_host->clk_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret = clk_prepare_enable(sprd_host->clk_2x_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) goto clk_disable2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) sdhci_sprd_init_config(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) SDHCI_VENDOR_VER_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) pm_suspend_ignore_children(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) sdhci_enable_v4_mode(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * Supply the existing CAPS, but clear the UHS-I modes. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * will allow these modes to be specified only by device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * tree properties through mmc_of_parse().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) SDHCI_SUPPORT_DDR50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret = sdhci_setup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) goto pm_runtime_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) sprd_host->flags = host->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (!hsq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) goto err_cleanup_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = mmc_hsq_init(hsq, host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) goto err_cleanup_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ret = __sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) goto err_cleanup_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) pm_runtime_mark_last_busy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) pm_runtime_put_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) err_cleanup_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) sdhci_cleanup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) pm_runtime_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) clk_disable_unprepare(sprd_host->clk_2x_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) clk_disable2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) clk_disable_unprepare(sprd_host->clk_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) clk_disable_unprepare(sprd_host->clk_sdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) pltfm_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int sdhci_sprd_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct sdhci_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) sdhci_remove_host(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) clk_disable_unprepare(sprd_host->clk_sdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) clk_disable_unprepare(sprd_host->clk_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) clk_disable_unprepare(sprd_host->clk_2x_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const struct of_device_id sdhci_sprd_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) { .compatible = "sprd,sdhci-r11", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static int sdhci_sprd_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) mmc_hsq_suspend(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) sdhci_runtime_suspend_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) clk_disable_unprepare(sprd_host->clk_sdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) clk_disable_unprepare(sprd_host->clk_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) clk_disable_unprepare(sprd_host->clk_2x_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int sdhci_sprd_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ret = clk_prepare_enable(sprd_host->clk_2x_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ret = clk_prepare_enable(sprd_host->clk_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) goto clk_2x_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ret = clk_prepare_enable(sprd_host->clk_sdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) sdhci_runtime_resume_host(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mmc_hsq_resume(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) clk_disable_unprepare(sprd_host->clk_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) clk_2x_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) clk_disable_unprepare(sprd_host->clk_2x_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static const struct dev_pm_ops sdhci_sprd_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) sdhci_sprd_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static struct platform_driver sdhci_sprd_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .probe = sdhci_sprd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .remove = sdhci_sprd_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .name = "sdhci_sprd_r11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .of_match_table = of_match_ptr(sdhci_sprd_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .pm = &sdhci_sprd_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) module_platform_driver(sdhci_sprd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) MODULE_ALIAS("platform:sdhci-sprd-r11");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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