Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * SDHCI support for SiRF primaII and marco SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define SDHCI_CLK_DELAY_SETTING 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SDHCI_SIRF_8BITBUS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SIRF_TUNING_COUNT 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	u8 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	ctrl &= ~(SDHCI_CTRL_4BITBUS | SDHCI_SIRF_8BITBUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	 * CSR atlas7 and prima2 SD host version is not 3.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	 * 8bit-width enable bit of CSR SD hosts is 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	 * while stardard hosts use bit 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	if (width == MMC_BUS_WIDTH_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		ctrl |= SDHCI_SIRF_8BITBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	else if (width == MMC_BUS_WIDTH_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		ctrl |= SDHCI_CTRL_4BITBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static u32 sdhci_sirf_readl_le(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32 val = readl(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	if (unlikely((reg == SDHCI_CAPABILITIES_1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			(host->mmc->caps & MMC_CAP_UHS_SDR50))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		/* fake CAP_1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		val = SDHCI_SUPPORT_DDR50 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			SDHCI_SUPPORT_SDR50 | SDHCI_USE_SDR50_TUNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	if (unlikely(reg == SDHCI_SLOT_INT_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		u32 prss = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		/* fake chips as V3.0 host conreoller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		prss &= ~(0xFF << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		val = prss | (SDHCI_SPEC_300 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static u16 sdhci_sirf_readw_le(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u16 ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	ret = readw(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if (unlikely(reg == SDHCI_HOST_VERSION)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		ret = readw(host->ioaddr + SDHCI_HOST_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		ret |= SDHCI_SPEC_300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	int tuning_seq_cnt = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u8 tuned_phase_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	int rc = 0, longest_range = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int start = -1, end = 0, tuning_value = -1, range = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u16 clock_setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	clock_setting = sdhci_readw(host, SDHCI_CLK_DELAY_SETTING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	clock_setting &= ~0x3fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	phase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	tuned_phase_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		sdhci_writel(host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			clock_setting | phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			SDHCI_CLK_DELAY_SETTING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		if (!mmc_send_tuning(mmc, opcode, NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			/* Tuning is successful at this tuning point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			tuned_phase_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				 mmc_hostname(mmc), phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			if (start == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				start = phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			end = phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			range++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			if (phase == (SIRF_TUNING_COUNT - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				&& range > longest_range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				tuning_value = (start + end) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			dev_dbg(mmc_dev(mmc), "%s: Found bad phase = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				 mmc_hostname(mmc), phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			if (range > longest_range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				tuning_value = (start + end) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 				longest_range = range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			start = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			end = range = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	} while (++phase < SIRF_TUNING_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (tuned_phase_cnt && tuning_value > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		 * Finally set the selected phase in delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		 * line hw block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		phase = tuning_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		sdhci_writel(host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			clock_setting | phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			SDHCI_CLK_DELAY_SETTING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			 mmc_hostname(mmc), phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		if (--tuning_seq_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		/* Tuning failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		       mmc_hostname(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct sdhci_ops sdhci_sirf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.read_l = sdhci_sirf_readl_le,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.read_w = sdhci_sirf_readw_le,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.platform_execute_tuning = sdhci_sirf_execute_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.get_max_clock	= sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.set_bus_width = sdhci_sirf_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct sdhci_pltfm_data sdhci_sirf_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.ops = &sdhci_sirf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int sdhci_sirf_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		dev_err(&pdev->dev, "unable to get clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	host = sdhci_pltfm_init(pdev, &sdhci_sirf_pdata, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	pltfm_host->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	sdhci_get_of_property(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	ret = clk_prepare_enable(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		goto err_clk_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ret = sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		goto err_sdhci_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 * We must request the IRQ after sdhci_add_host(), as the tasklet only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * gets setup in sdhci_add_host() and we oops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ret = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		goto err_request_cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		mmc_gpiod_request_cd_irq(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) err_request_cd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	sdhci_remove_host(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) err_sdhci_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	clk_disable_unprepare(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) err_clk_prepare:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct of_device_id sdhci_sirf_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	{ .compatible = "sirf,prima2-sdhc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MODULE_DEVICE_TABLE(of, sdhci_sirf_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct platform_driver sdhci_sirf_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.name	= "sdhci-sirf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.of_match_table = sdhci_sirf_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		.pm	= &sdhci_pltfm_pmops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.probe		= sdhci_sirf_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.remove		= sdhci_pltfm_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) module_platform_driver(sdhci_sirf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MODULE_DESCRIPTION("SDHCI driver for SiRFprimaII/SiRFmarco");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_LICENSE("GPL v2");