Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2010 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *		Zhangfei Gao <zhangfei.gao@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *		Kevin Wang <dwang4@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *		Jun Nie <njun@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *		Qiming Wu <wuqm@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *		Philip Rakity <prakity@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mmc/card.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_data/pxa_sdhci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "sdhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SD_FIFO_PARAM		0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DIS_PAD_SD_CLK_GATE	0x0400 /* Turn on/off Dynamic SD Clock Gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CLK_GATE_ON		0x0200 /* Disable/enable Clock Gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CLK_GATE_CTL		0x0100 /* Clock Gate Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CLK_GATE_SETTING_BITS	(DIS_PAD_SD_CLK_GATE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		CLK_GATE_ON | CLK_GATE_CTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SD_CLOCK_BURST_SIZE_SETUP	0xe6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SDCLK_SEL_SHIFT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SDCLK_SEL_MASK		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SDCLK_DELAY_SHIFT	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SDCLK_DELAY_MASK	0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SD_CE_ATA_2		0xea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MMC_CARD		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MMC_WIDTH		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static void pxav2_reset(struct sdhci_host *host, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	sdhci_reset(host, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	if (mask == SDHCI_RESET_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		u16 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		 * tune timing of read data/command when crc error happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		 * no performance impact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		if (pdata && pdata->clk_delay_sel == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 			tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 				<< SDCLK_DELAY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			tmp = readw(host->ioaddr + SD_FIFO_PARAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			tmp &= ~CLK_GATE_SETTING_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			writew(tmp, host->ioaddr + SD_FIFO_PARAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			tmp = readw(host->ioaddr + SD_FIFO_PARAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			tmp &= ~CLK_GATE_SETTING_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			tmp |= CLK_GATE_SETTING_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			writew(tmp, host->ioaddr + SD_FIFO_PARAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u8 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	tmp = readw(host->ioaddr + SD_CE_ATA_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (width == MMC_BUS_WIDTH_8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		ctrl &= ~SDHCI_CTRL_4BITBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		tmp |= MMC_CARD | MMC_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		tmp &= ~(MMC_CARD | MMC_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		if (width == MMC_BUS_WIDTH_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			ctrl |= SDHCI_CTRL_4BITBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			ctrl &= ~SDHCI_CTRL_4BITBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	writew(tmp, host->ioaddr + SD_CE_ATA_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct sdhci_ops pxav2_sdhci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.set_clock     = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.set_bus_width = pxav2_mmc_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.reset         = pxav2_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct of_device_id sdhci_pxav2_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.compatible = "mrvl,pxav2-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct sdhci_pxa_platdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u32 bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u32 clk_delay_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (of_find_property(np, "non-removable", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		pdata->flags |= PXA_FLAG_CARD_PERMANENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	of_property_read_u32(np, "bus-width", &bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (bus_width == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (clk_delay_cycles > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		pdata->clk_delay_sel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		pdata->clk_delay_cycles = clk_delay_cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int sdhci_pxav2_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct sdhci_host *host = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	host = sdhci_pltfm_init(pdev, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	clk = devm_clk_get(dev, "PXA-SDHCLK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		dev_err(dev, "failed to get io clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	pltfm_host->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		dev_err(&pdev->dev, "failed to enable io clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	host->quirks = SDHCI_QUIRK_BROKEN_ADMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		| SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	match = of_match_device(of_match_ptr(sdhci_pxav2_of_match), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		pdata = pxav2_get_mmc_pdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			/* on-chip device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			host->mmc->caps |= MMC_CAP_NONREMOVABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		/* If slot design supports 8 bit data, indicate this to MMC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			host->mmc->caps |= MMC_CAP_8_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		if (pdata->quirks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			host->quirks |= pdata->quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		if (pdata->host_caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			host->mmc->caps |= pdata->host_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		if (pdata->pm_caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			host->mmc->pm_caps |= pdata->pm_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	host->ops = &pxav2_sdhci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	ret = sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static struct platform_driver sdhci_pxav2_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.name	= "sdhci-pxav2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		.of_match_table = of_match_ptr(sdhci_pxav2_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.pm	= &sdhci_pltfm_pmops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.probe		= sdhci_pxav2_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.remove		= sdhci_pltfm_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) module_platform_driver(sdhci_pxav2_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MODULE_DESCRIPTION("SDHCI driver for pxav2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MODULE_AUTHOR("Marvell International Ltd.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)