^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __SDHCI_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __SDHCI_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * PCI device IDs, sub IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define PCI_DEVICE_ID_O2_SDS0 0x8420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PCI_DEVICE_ID_O2_SDS1 0x8421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PCI_DEVICE_ID_O2_FUJIN2 0x8520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PCI_DEVICE_ID_O2_SEABIRD0 0x8620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PCI_DEVICE_ID_O2_SEABIRD1 0x8621
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa375
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCI_DEVICE_ID_INTEL_ICP_EMMC 0x34c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCI_DEVICE_ID_INTEL_ICP_SD 0x34f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCI_DEVICE_ID_INTEL_EHL_EMMC 0x4b47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCI_DEVICE_ID_INTEL_EHL_SD 0x4b48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCI_DEVICE_ID_INTEL_CML_EMMC 0x02c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCI_DEVICE_ID_INTEL_CML_SD 0x02f5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCI_DEVICE_ID_INTEL_CMLH_SD 0x06f5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCI_DEVICE_ID_INTEL_JSL_EMMC 0x4dc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCI_DEVICE_ID_INTEL_JSL_SD 0x4df8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCI_DEVICE_ID_INTEL_LKF_EMMC 0x98c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCI_DEVICE_ID_INTEL_LKF_SD 0x98f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCI_DEVICE_ID_INTEL_ADL_EMMC 0x54c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCI_DEVICE_ID_SYSKONNECT_8000 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCI_DEVICE_ID_VIA_95D0 0x95d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCI_DEVICE_ID_REALTEK_5250 0x5250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCI_SUBDEVICE_ID_NI_7884 0x7884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCI_SUBDEVICE_ID_NI_78E3 0x78e3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCI_VENDOR_ID_ARASAN 0x16e6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCI_DEVICE_ID_ARASAN_PHY_EMMC 0x0670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xc202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCI_DEVICE_ID_GLI_9755 0x9755
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCI_DEVICE_ID_GLI_9750 0x9750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCI_DEVICE_ID_GLI_9763E 0xe763
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * PCI device class and mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCI_CLASS_MASK 0xFFFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Macros for PCI device-description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .subvendor = _PCI_VEND(subvend), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .subdevice = _PCI_SUBDEV(subvend, subdev), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .class = (cl), .class_mask = (cl_msk), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * PCI registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PCI_SDHCI_IFPIO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PCI_SDHCI_IFDMA 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PCI_SDHCI_IFVENDOR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCI_SLOT_INFO 0x40 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MAX_SLOTS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct sdhci_pci_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct sdhci_pci_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct sdhci_pci_fixes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int quirks2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bool allow_runtime_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool own_cd_for_runtime_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int (*probe) (struct sdhci_pci_chip *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int (*probe_slot) (struct sdhci_pci_slot *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int (*add_host) (struct sdhci_pci_slot *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void (*remove_slot) (struct sdhci_pci_slot *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int (*suspend) (struct sdhci_pci_chip *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int (*resume) (struct sdhci_pci_chip *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int (*runtime_suspend) (struct sdhci_pci_chip *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int (*runtime_resume) (struct sdhci_pci_chip *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const struct sdhci_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) size_t priv_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct sdhci_pci_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct sdhci_pci_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct sdhci_pci_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int rst_n_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int cd_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int cd_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int cd_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bool cd_override_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void (*hw_reset)(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long private[] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct sdhci_pci_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int quirks2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bool allow_runtime_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) bool pm_retune;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) bool rpm_retune;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) const struct sdhci_pci_fixes *fixes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int num_slots; /* Slots on controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return (void *)slot->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int sdhci_pci_resume_host(struct sdhci_pci_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int sdhci_pci_enable_dma(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) extern const struct sdhci_pci_fixes sdhci_arasan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) extern const struct sdhci_pci_fixes sdhci_snps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) extern const struct sdhci_pci_fixes sdhci_o2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) extern const struct sdhci_pci_fixes sdhci_gl9750;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) extern const struct sdhci_pci_fixes sdhci_gl9755;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) extern const struct sdhci_pci_fixes sdhci_gl9763e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #endif /* __SDHCI_PCI_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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