^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 BayHub Technology Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Peter Guo <peter.guo@bayhubtech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Adam Lee <adam.lee@canonical.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Ernest Zhang <ernest.zhang@bayhubtech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "sdhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "sdhci-pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * O2Micro device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define O2_SD_MISC_REG5 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define O2_SD_LD0_CTRL 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define O2_SD_DEV_CTRL 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define O2_SD_LOCK_WP 0xD3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define O2_SD_TEST_REG 0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define O2_SD_FUNC_REG0 0xDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define O2_SD_MULTI_VCC3V 0xEE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define O2_SD_CLKREQ 0xEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define O2_SD_CAPS 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define O2_SD_ADMA1 0xE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define O2_SD_ADMA2 0xE7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define O2_SD_INF_MOD 0xF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define O2_SD_MISC_CTRL4 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define O2_SD_MISC_CTRL 0x1C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define O2_SD_PWR_FORCE_L0 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define O2_SD_TUNING_CTRL 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define O2_SD_PLL_SETTING 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define O2_SD_MISC_SETTING 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define O2_SD_CLK_SETTING 0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define O2_SD_CAP_REG2 0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define O2_SD_CAP_REG0 0x334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define O2_SD_UHS1_CAP_SETTING 0x33C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define O2_SD_DELAY_CTRL 0x350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define O2_SD_UHS2_L1_CTRL 0x35C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define O2_SD_FUNC_REG3 0x3E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define O2_SD_FUNC_REG4 0x3E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define O2_SD_LED_ENABLE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define O2_SD_FREG0_LEDOFF BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define O2_SD_VENDOR_SETTING 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define O2_SD_VENDOR_SETTING2 0x1C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define O2_SD_HW_TUNING_DISABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define O2_PLL_DLL_WDT_CONTROL1 0x1CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define O2_PLL_FORCE_ACTIVE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define O2_PLL_LOCK_STATUS BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define O2_PLL_SOFT_RESET BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define O2_DLL_LOCK_STATUS BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define O2_SD_DETECT_SETTING 0x324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const u32 dmdn_table[] = {0x2B1C0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0x2C1A0000, 0x371B0000, 0x35100000};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DMDN_SZ ARRAY_SIZE(dmdn_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct o2_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 dll_adjust_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ktime_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 scratch32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Wait max 50 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) timeout = ktime_add_ms(ktime_get(), 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bool timedout = ktime_after(ktime_get(), timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (timedout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pr_err("%s: Card Detect debounce never finished.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) sdhci_dumpregs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ktime_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u16 scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 scratch32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* PLL software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) scratch32 |= O2_PLL_SOFT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) scratch32 &= ~(O2_PLL_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* PLL force active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) scratch32 |= O2_PLL_FORCE_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Wait max 20 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) timeout = ktime_add_ms(ktime_get(), 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) bool timedout = ktime_after(ktime_get(), timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (scratch & O2_PLL_LOCK_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (timedout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) pr_err("%s: Internal clock never stabilised.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) sdhci_dumpregs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Wait for card detect finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) sdhci_o2_wait_card_detect_stable(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Cancel PLL force active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) scratch32 &= ~O2_PLL_FORCE_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int sdhci_o2_get_cd(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) sdhci_o2_enable_internal_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 scratch_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) O2_SD_PLL_SETTING, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) scratch_32 &= 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) scratch_32 |= value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pci_write_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) O2_SD_PLL_SETTING, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * This function is used to detect dll lock status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Since the dll lock status bit will toggle randomly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * with very short interval which needs to be polled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * as fast as possible. Set sleep_us as 1 microsecond.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 scratch32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* enable hardware tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) reg &= ~O2_SD_HW_TUNING_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) sdhci_send_tuning(host, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) for (i = 0; i < 150; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ctrl & SDHCI_CTRL_TUNED_CLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) host->tuning_done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pr_warn("%s: HW tuning failed !\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) sdhci_reset_tuning(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * This function is used to fix o2 dll shift issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * It isn't necessary to detect card present before recovery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Firstly, it is used by bht emmc card, which is embedded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Second, before call recovery card present will be detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * outside of the execute tuning function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int sdhci_o2_dll_recovery(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u8 scratch_8 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 scratch_32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct sdhci_pci_slot *slot = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct sdhci_pci_chip *chip = slot->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct o2_host *o2_host = sdhci_pci_priv(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* UnLock WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pci_read_config_byte(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) O2_SD_LOCK_WP, &scratch_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) scratch_8 &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Disable clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* PLL software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) scratch_32 |= O2_PLL_SOFT_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) O2_SD_FUNC_REG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Enable Base Clk setting change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Enable internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) scratch_8 = SDHCI_CLOCK_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (sdhci_o2_get_cd(host->mmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * need wait at least 5ms for dll status stable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * after enable internal clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (sdhci_o2_wait_dll_detect_lock(host)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) scratch_8 |= SDHCI_CLOCK_CARD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) sdhci_writeb(host, scratch_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mmc_hostname(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) o2_host->dll_adjust_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pr_err("%s: card present detect failed.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) o2_host->dll_adjust_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) pr_err("%s: DLL adjust over max times\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Lock WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pci_read_config_byte(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) O2_SD_LOCK_WP, &scratch_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) scratch_8 |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int current_bus_width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 scratch32 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u16 scratch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * This handler only implements the eMMC tuning that is specific to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * this controller. Fall back to the standard method for other TIMING.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if ((host->timing != MMC_TIMING_MMC_HS200) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) (host->timing != MMC_TIMING_UHS_SDR104))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return sdhci_execute_tuning(mmc, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) (opcode != MMC_SEND_TUNING_BLOCK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Force power mode enter L0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) scratch |= O2_SD_PWR_FORCE_L0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* wait DLL lock, timeout value 5ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Judge the tuning reason, whether caused by dll shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * If cause by dll shift, should call sdhci_o2_dll_recovery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!sdhci_o2_wait_dll_detect_lock(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (!sdhci_o2_dll_recovery(host)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pr_err("%s: o2 dll recovery failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * o2 sdhci host didn't support 8bit emmc tuning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) current_bus_width = mmc->ios.bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) mmc->ios.bus_width = MMC_BUS_WIDTH_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) sdhci_o2_set_tuning_mode(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) sdhci_start_tuning(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) __sdhci_o2_execute_tuning(host, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) sdhci_end_tuning(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (current_bus_width == MMC_BUS_WIDTH_8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mmc->ios.bus_width = MMC_BUS_WIDTH_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) sdhci_set_bus_width(host, current_bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Cancel force power mode enter L0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) scratch &= ~(O2_SD_PWR_FORCE_L0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) sdhci_reset(host, SDHCI_RESET_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) sdhci_reset(host, SDHCI_RESET_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) host->flags &= ~SDHCI_HS400_TUNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 scratch_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Set led of SD host function enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) O2_SD_FUNC_REG0, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) scratch_32 &= ~O2_SD_FREG0_LEDOFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pci_write_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) O2_SD_FUNC_REG0, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) O2_SD_TEST_REG, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) scratch_32 |= O2_SD_LED_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pci_write_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) O2_SD_TEST_REG, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u32 scratch_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Improve write performance for SD3.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Enable Link abnormal reset generating Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) scratch_32 &= ~((1 << 19) | (1 << 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) scratch_32 |= (1 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* set card power over current protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) scratch_32 |= (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* adjust the output delay for SD mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Set the output voltage setting of Aux 1.2v LDO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) scratch_32 &= ~(3 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Set Max power supply capability of SD host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) scratch_32 &= ~(0x01FE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) scratch_32 |= 0x00CC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Set DLL Tuning Window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ret = pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) O2_SD_TUNING_CTRL, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) scratch_32 &= ~(0x000000FF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) scratch_32 |= 0x00000066;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Set UHS2 T_EIDLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) O2_SD_UHS2_L1_CTRL, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) scratch_32 &= ~(0x000000FC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) scratch_32 |= 0x00000084;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Set UHS2 Termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) scratch_32 &= ~((1 << 21) | (1 << 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Set L1 Entrance Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) scratch_32 &= ~(0xf0000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) scratch_32 |= 0x30000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) O2_SD_MISC_CTRL4, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) scratch_32 &= ~(0x000f0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) scratch_32 |= 0x00080000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) pr_info("%s: unsupport msi, use INTx irq\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PCI_IRQ_MSI | PCI_IRQ_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pr_err("%s: enable PCI MSI failed, err=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) mmc_hostname(host->mmc), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) host->irq = pci_irq_vector(chip->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Enable internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) clk |= SDHCI_CLOCK_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) sdhci_o2_enable_internal_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (sdhci_o2_get_cd(host->mmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) clk |= SDHCI_CLOCK_CARD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u16 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u8 scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u32 scratch_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct sdhci_pci_slot *slot = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct sdhci_pci_chip *chip = slot->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) host->mmc->actual_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (clock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) scratch &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if ((scratch_32 & 0xFFFF0000) != 0x2c280000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) o2_pci_set_baseclk(chip, 0x2c280000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) scratch |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) sdhci_o2_enable_clk(host, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct sdhci_pci_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct o2_host *o2_host = sdhci_pci_priv(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 reg, caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) chip = slot->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) o2_host->dll_adjust_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) caps = sdhci_readl(host, SDHCI_CAPABILITIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * mmc_select_bus_width() will test the bus to determine the actual bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (caps & SDHCI_CAN_DO_8BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) host->mmc->caps |= MMC_CAP_8_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) switch (chip->pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case PCI_DEVICE_ID_O2_SDS0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case PCI_DEVICE_ID_O2_SEABIRD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case PCI_DEVICE_ID_O2_SEABIRD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case PCI_DEVICE_ID_O2_SDS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case PCI_DEVICE_ID_O2_FUJIN2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (reg & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) sdhci_pci_o2_enable_msi(chip, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ret = pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) O2_SD_MISC_SETTING, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (reg & (1 << 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) host->flags &= ~SDHCI_SIGNALING_330;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) host->flags |= SDHCI_SIGNALING_180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) host->mmc->caps2 |= MMC_CAP2_NO_SD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pci_write_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) O2_SD_DETECT_SETTING, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* set dll watch dog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) reg |= (1 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u8 scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 scratch_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) switch (chip->pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) case PCI_DEVICE_ID_O2_8220:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) case PCI_DEVICE_ID_O2_8221:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) case PCI_DEVICE_ID_O2_8320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case PCI_DEVICE_ID_O2_8321:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* This extra setup is required due to broken ADMA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ret = pci_read_config_byte(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) O2_SD_LOCK_WP, &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) scratch &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Set Multi 3 to VCC3V# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Disable CLK_REQ# support after media DET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = pci_read_config_byte(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) O2_SD_CLKREQ, &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) scratch |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* Choose capabilities, enable SDMA. We have to write 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * to the capabilities register first to unlock it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) scratch |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Disable ADMA1/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Disable the infinite transfer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = pci_read_config_byte(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) O2_SD_INF_MOD, &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) scratch |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Lock WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = pci_read_config_byte(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) O2_SD_LOCK_WP, &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) scratch |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case PCI_DEVICE_ID_O2_SDS0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case PCI_DEVICE_ID_O2_SDS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) case PCI_DEVICE_ID_O2_FUJIN2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* UnLock WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = pci_read_config_byte(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) O2_SD_LOCK_WP, &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) scratch &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ret = pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) O2_SD_FUNC_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Check Whether subId is 0x11 or 0x12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) scratch_32 = 0x25100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) o2_pci_set_baseclk(chip, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) O2_SD_FUNC_REG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* Enable Base Clk setting change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pci_write_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) O2_SD_FUNC_REG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* Set Tuning Window to 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) pci_write_config_byte(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) O2_SD_TUNING_CTRL, 0x44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Enable 8520 led function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) o2_pci_led_enable(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* Set timeout CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) O2_SD_CLK_SETTING, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) scratch_32 &= ~(0xFF00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) scratch_32 |= 0x07E0C800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) pci_write_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) O2_SD_CLK_SETTING, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ret = pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) O2_SD_CLKREQ, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) scratch_32 |= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ret = pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) O2_SD_PLL_SETTING, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) scratch_32 &= ~(0x1F3F070E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) scratch_32 |= 0x18270106;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) pci_write_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) O2_SD_PLL_SETTING, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Disable UHS1 funciton */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) O2_SD_CAP_REG2, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) scratch_32 &= ~(0xE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) pci_write_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) O2_SD_CAP_REG2, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) sdhci_pci_o2_fujin2_pci_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Lock WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret = pci_read_config_byte(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) O2_SD_LOCK_WP, &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) scratch |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case PCI_DEVICE_ID_O2_SEABIRD0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) case PCI_DEVICE_ID_O2_SEABIRD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* UnLock WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ret = pci_read_config_byte(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) O2_SD_LOCK_WP, &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) scratch &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret = pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) O2_SD_PLL_SETTING, &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if ((scratch_32 & 0xff000000) == 0x01000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) scratch_32 &= 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) scratch_32 |= 0x1F340000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pci_write_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) O2_SD_PLL_SETTING, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) scratch_32 &= 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) scratch_32 |= 0x25100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) pci_write_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) O2_SD_PLL_SETTING, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = pci_read_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) O2_SD_FUNC_REG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) &scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) scratch_32 |= (1 << 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) pci_write_config_dword(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) O2_SD_FUNC_REG4, scratch_32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* Set Tuning Windows to 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) pci_write_config_byte(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) O2_SD_TUNING_CTRL, 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* Lock WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ret = pci_read_config_byte(chip->pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) O2_SD_LOCK_WP, &scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) scratch |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) sdhci_pci_o2_probe(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return sdhci_pci_resume_host(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static const struct sdhci_ops sdhci_pci_o2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .set_clock = sdhci_pci_o2_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .enable_dma = sdhci_pci_enable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) const struct sdhci_pci_fixes sdhci_o2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .probe = sdhci_pci_o2_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .probe_slot = sdhci_pci_o2_probe_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .resume = sdhci_pci_o2_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .ops = &sdhci_pci_o2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .priv_size = sizeof(struct o2_host),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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