^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019 Genesys Logic, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Version: v0.9.0 (2019-08-08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "sdhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "sdhci-pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "cqhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Genesys Logic extra registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SDHCI_GLI_9750_WT 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SDHCI_GLI_9750_WT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GLI_9750_WT_EN_ON 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GLI_9750_WT_EN_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SDHCI_GLI_9750_DRIVING 0x860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GLI_9750_DRIVING_1_VALUE 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GLI_9750_DRIVING_2_VALUE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SDHCI_GLI_9750_SEL_1 BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SDHCI_GLI_9750_SEL_2 BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SDHCI_GLI_9750_PLL 0x864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SDHCI_GLI_9750_PLL_DIR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GLI_9750_PLL_TX2_INV_VALUE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GLI_9750_PLL_TX2_DLY_VALUE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SDHCI_GLI_9750_PLLSSC_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SDHCI_GLI_9750_PLLSSC 0x86C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SDHCI_GLI_9750_SW_CTRL 0x874
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GLI_9750_SW_CTRL_4_VALUE 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SDHCI_GLI_9750_MISC 0x878
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SDHCI_GLI_9750_MISC_RX_INV BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GLI_9750_MISC_TX1_INV_VALUE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GLI_9750_MISC_RX_INV_ON 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GLI_9750_MISC_RX_INV_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GLI_9750_MISC_TX1_DLY_VALUE 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SDHCI_GLI_9750_TUNING_CONTROL 0x540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GLI_9750_TUNING_CONTROL_EN_ON 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SDHCI_GLI_9763E_CTRL_HS400 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PCIE_GLI_9763E_VHS 0x884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GLI_9763E_VHS_REV GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GLI_9763E_VHS_REV_R 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GLI_9763E_VHS_REV_M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GLI_9763E_VHS_REV_W 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCIE_GLI_9763E_MB 0x888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GLI_9763E_MB_CMDQ_OFF BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCIE_GLI_9763E_SCR 0x8E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GLI_9763E_SCR_AXI_REQ BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SDHCI_TRNS_BLK_CNT_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SDHCI_TRNS_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PCI_GLI_9755_WT 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PCI_GLI_9755_WT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GLI_9755_WT_EN_ON 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GLI_9755_WT_EN_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCI_GLI_9755_PLL 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCI_GLI_9755_PLL_DIR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PCI_GLI_9755_PLLSSC_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCI_GLI_9755_PLLSSC 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GLI_MAX_TUNING_LOOP 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Genesys Logic chipset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline void gl9750_wt_on(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 wt_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 wt_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (wt_enable == GLI_9750_WT_EN_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) wt_value &= ~SDHCI_GLI_9750_WT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static inline void gl9750_wt_off(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 wt_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 wt_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (wt_enable == GLI_9750_WT_EN_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) wt_value &= ~SDHCI_GLI_9750_WT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void gli_set_9750(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 driving_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 pll_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 sw_ctrl_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 misc_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 parameter_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 control_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u16 ctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) gl9750_wt_on(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) GLI_9750_DRIVING_1_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) GLI_9750_DRIVING_2_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) driving_value |= SDHCI_GLI_9750_SEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) GLI_9750_SW_CTRL_4_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* reset the tuning flow after reinit and before starting tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) GLI_9750_PLL_TX2_INV_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) GLI_9750_PLL_TX2_DLY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) GLI_9750_MISC_TX1_INV_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) GLI_9750_MISC_RX_INV_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) GLI_9750_MISC_TX1_DLY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* disable tuned clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* enable tuning parameters control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) GLI_9750_TUNING_CONTROL_EN_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* write tuning parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* disable tuning parameters control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) GLI_9750_TUNING_CONTROL_EN_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* clear tuned clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) gl9750_wt_off(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 misc_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) gl9750_wt_on(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) GLI_9750_MISC_RX_INV_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) GLI_9750_MISC_RX_INV_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) gl9750_wt_off(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int rx_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) for (rx_inv = 0; rx_inv < 2; rx_inv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) gli_set_9750_rx_inv(host, !!rx_inv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sdhci_start_tuning(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) sdhci_send_tuning(host, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!host->tuning_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) sdhci_abort_tuning(host, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (ctrl & SDHCI_CTRL_TUNED_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0; /* Success! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!host->tuning_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) sdhci_reset_tuning(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) host->mmc->retune_period = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (host->tuning_mode == SDHCI_TUNING_MODE_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) host->mmc->retune_period = host->tuning_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) gli_set_9750(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) sdhci_end_tuning(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static void gl9750_disable_ssc_pll(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) gl9750_wt_on(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) gl9750_wt_off(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) gl9750_wt_on(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) SDHCI_GLI_9750_PLL_PDIV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) SDHCI_GLI_9750_PLL_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) gl9750_wt_off(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* wait for pll stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 ssc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) gl9750_wt_on(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SDHCI_GLI_9750_PLLSSC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) gl9750_wt_off(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* set pll to 205MHz and enable ssc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) gl9750_set_ssc(host, 0x1, 0x1F, 0xFFE7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) gl9750_set_pll(host, 0x1, 0x246, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct mmc_ios *ios = &host->mmc->ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u16 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) host->mmc->actual_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) gl9750_disable_ssc_pll(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (clock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) host->mmc->actual_clock = 205000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) gl9750_set_ssc_pll_205mhz(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) sdhci_enable_clk(host, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PCI_IRQ_MSI | PCI_IRQ_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pr_warn("%s: enable PCI MSI failed, error=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) mmc_hostname(slot->host->mmc), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static inline void gl9755_wt_on(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 wt_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 wt_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (wt_enable == GLI_9755_WT_EN_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) wt_value &= ~PCI_GLI_9755_WT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static inline void gl9755_wt_off(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 wt_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 wt_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (wt_enable == GLI_9755_WT_EN_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) wt_value &= ~PCI_GLI_9755_WT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) gl9755_wt_on(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) gl9755_wt_off(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u32 pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) gl9755_wt_on(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) pll &= ~(PCI_GLI_9755_PLL_LDIV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PCI_GLI_9755_PLL_PDIV |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PCI_GLI_9755_PLL_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) gl9755_wt_off(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* wait for pll stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u32 ssc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) gl9755_wt_on(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PCI_GLI_9755_PLLSSC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) gl9755_wt_off(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* set pll to 205MHz and enable ssc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) gl9755_set_ssc(pdev, 0x1, 0x1F, 0xFFE7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct sdhci_pci_slot *slot = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct mmc_ios *ios = &host->mmc->ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u16 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) pdev = slot->chip->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) host->mmc->actual_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) gl9755_disable_ssc_pll(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (clock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) host->mmc->actual_clock = 205000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) gl9755_set_ssc_pll_205mhz(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) sdhci_enable_clk(host, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct sdhci_host *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) gli_pcie_enable_msi(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) sdhci_enable_v4_mode(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct sdhci_host *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) gli_pcie_enable_msi(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) sdhci_enable_v4_mode(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void sdhci_gli_voltage_switch(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * According to Section 3.6.1 signal voltage switch procedure in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * (6) Set 1.8V Signal Enable in the Host Control 2 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * step (12).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * Wait 5ms after set 1.8V signal enable in Host Control 2 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * to ensure 1.8V signal enable bit is set by GL9750/GL9755.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * ...however, the controller in the NUC10i3FNK4 (a 9755) requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * slightly longer than 5ms before the control register reports that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * 1.8V is ready, and far longer still before the card will actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * work reliably.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) usleep_range(100000, 110000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) sdhci_reset(host, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) gli_set_9750(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) value = readl(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) value |= 0xc8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct sdhci_pci_slot *slot = chip->slots[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pci_free_irq_vectors(slot->chip->pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) gli_pcie_enable_msi(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return sdhci_pci_resume_host(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct sdhci_pci_slot *slot = chip->slots[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ret = sdhci_pci_gli_resume(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return cqhci_resume(slot->host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct sdhci_pci_slot *slot = chip->slots[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = cqhci_suspend(slot->host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return sdhci_suspend_host(slot->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ios->enhanced_strobe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) val |= SDHCI_GLI_9763E_HS400_ES_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) val &= ~SDHCI_GLI_9763E_HS400_ES_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) unsigned int timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u16 ctrl_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (timing == MMC_TIMING_MMC_HS200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) else if (timing == MMC_TIMING_MMC_HS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) else if (timing == MMC_TIMING_MMC_DDR52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) else if (timing == MMC_TIMING_MMC_HS400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) sdhci_dumpregs(mmc_priv(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct cqhci_host *cq_host = mmc->cqe_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) value = cqhci_readl(cq_host, CQHCI_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) value |= CQHCI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) cqhci_writel(cq_host, value, CQHCI_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) sdhci_cqe_enable(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int cmd_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) int data_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) cqhci_irq(host->mmc, intmask, cmd_error, data_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct cqhci_host *cq_host = mmc->cqe_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) value = cqhci_readl(cq_host, CQHCI_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) value &= ~CQHCI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) cqhci_writel(cq_host, value, CQHCI_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .enable = sdhci_gl9763e_cqe_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .disable = sdhci_cqe_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .dumpregs = sdhci_gl9763e_dumpregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .pre_enable = sdhci_gl9763e_cqe_pre_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .post_disable = sdhci_gl9763e_cqe_post_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int gl9763e_add_host(struct sdhci_pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct device *dev = &slot->chip->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct sdhci_host *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct cqhci_host *cq_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) bool dma64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = sdhci_setup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (!cq_host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) cq_host->ops = &sdhci_gl9763e_cqhci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (dma64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ret = cqhci_init(cq_host, host->mmc, dma64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ret = __sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) sdhci_cleanup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) host->mmc->cqe_private)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) cqhci_deactivate(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) sdhci_reset(host, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct pci_dev *pdev = slot->chip->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) value &= ~GLI_9763E_VHS_REV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) value |= GLI_9763E_SCR_AXI_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) value &= ~GLI_9763E_VHS_REV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct pci_dev *pdev = slot->chip->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct sdhci_host *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) host->mmc->caps |= MMC_CAP_8_BIT_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) MMC_CAP_1_8V_DDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) MMC_CAP_NONREMOVABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) MMC_CAP2_HS400_1_8V |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) MMC_CAP2_HS400_ES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) MMC_CAP2_NO_SDIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) MMC_CAP2_NO_SD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (!(value & GLI_9763E_MB_CMDQ_OFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) gli_pcie_enable_msi(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) host->mmc_host_ops.hs400_enhanced_strobe =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) gl9763e_hs400_enhanced_strobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) gli_set_gl9763e(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) sdhci_enable_v4_mode(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static const struct sdhci_ops sdhci_gl9755_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .set_clock = sdhci_gl9755_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .enable_dma = sdhci_pci_enable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .voltage_switch = sdhci_gli_voltage_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) const struct sdhci_pci_fixes sdhci_gl9755 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .probe_slot = gli_probe_slot_gl9755,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .ops = &sdhci_gl9755_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .resume = sdhci_pci_gli_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static const struct sdhci_ops sdhci_gl9750_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .read_l = sdhci_gl9750_readl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .set_clock = sdhci_gl9750_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .enable_dma = sdhci_pci_enable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .reset = sdhci_gl9750_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .voltage_switch = sdhci_gli_voltage_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .platform_execute_tuning = gl9750_execute_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) const struct sdhci_pci_fixes sdhci_gl9750 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .probe_slot = gli_probe_slot_gl9750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .ops = &sdhci_gl9750_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .resume = sdhci_pci_gli_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static const struct sdhci_ops sdhci_gl9763e_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .enable_dma = sdhci_pci_enable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .reset = sdhci_gl9763e_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .set_uhs_signaling = sdhci_set_gl9763e_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .voltage_switch = sdhci_gli_voltage_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .irq = sdhci_gl9763e_cqhci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) const struct sdhci_pci_fixes sdhci_gl9763e = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .probe_slot = gli_probe_slot_gl9763e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .ops = &sdhci_gl9763e_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .resume = sdhci_cqhci_gli_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .suspend = sdhci_cqhci_gli_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .add_host = gl9763e_add_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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