^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/mmc/host/sdhci-of-sparx5.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * MCHP Sparx5 SoC Secure Digital Host Controller Interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2019 Microchip Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Lars Povlsen <lars.povlsen@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CPU_REGS_GENERAL_CTRL (0x22 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MSHC_DLY_CC_MASK GENMASK(16, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MSHC_DLY_CC_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MSHC_DLY_CC_MAX 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CPU_REGS_PROC_CTRL (0x2C * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ACP_CACHE_FORCE_ENA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ACP_AWCACHE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ACP_ARCACHE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ACP_CACHE_MASK (ACP_CACHE_FORCE_ENA|ACP_AWCACHE|ACP_ARCACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MSHC2_VERSION 0x500 /* Off 0x140, reg 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MSHC2_EMMC_CTRL_EMMC_RST_N BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct sdhci_sparx5_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct regmap *cpu_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int delay_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BOUNDARY_OK(addr, len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * If DMA addr spans 128MB boundary, we split the DMA transfer into two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * so that each DMA transfer doesn't exceed the boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void sdhci_sparx5_adma_write_desc(struct sdhci_host *host, void **desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) dma_addr_t addr, int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int tmplen, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (likely(!len || BOUNDARY_OK(addr, len))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) sdhci_adma_write_desc(host, desc, addr, len, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pr_debug("%s: write_desc: splitting dma len %d, offset %pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mmc_hostname(host->mmc), len, &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) offset = addr & (SZ_128M - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) tmplen = SZ_128M - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) addr += tmplen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) len -= tmplen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) sdhci_adma_write_desc(host, desc, addr, len, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void sparx5_set_cacheable(struct sdhci_host *host, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Update ACP caching attributes in HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) regmap_update_bits(sdhci_sparx5->cpu_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) CPU_REGS_PROC_CTRL, ACP_CACHE_MASK, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void sparx5_set_delay(struct sdhci_host *host, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pr_debug("%s: Set DLY_CC = %u\n", mmc_hostname(host->mmc), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Update DLY_CC in HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) regmap_update_bits(sdhci_sparx5->cpu_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) CPU_REGS_GENERAL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MSHC_DLY_CC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (value << MSHC_DLY_CC_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void sdhci_sparx5_set_emmc(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!mmc_card_is_removable(host->mmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) value = sdhci_readb(host, MSHC2_EMMC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!(value & MSHC2_EMMC_CTRL_IS_EMMC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) value |= MSHC2_EMMC_CTRL_IS_EMMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_debug("%s: Set EMMC_CTRL: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mmc_hostname(host->mmc), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void sdhci_sparx5_reset_emmc(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pr_debug("%s: Toggle EMMC_CTRL.EMMC_RST_N\n", mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) value = sdhci_readb(host, MSHC2_EMMC_CTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ~MSHC2_EMMC_CTRL_EMMC_RST_N;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* For eMMC, minimum is 1us but give it 10us for good measure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) sdhci_writeb(host, value | MSHC2_EMMC_CTRL_EMMC_RST_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MSHC2_EMMC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* For eMMC, minimum is 200us but give it 300us for good measure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) usleep_range(300, 400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void sdhci_sparx5_reset(struct sdhci_host *host, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pr_debug("%s: *** RESET: mask %d\n", mmc_hostname(host->mmc), mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) sdhci_reset(host, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Be sure CARD_IS_EMMC stays set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) sdhci_sparx5_set_emmc(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct sdhci_ops sdhci_sparx5_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .get_max_clock = sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .reset = sdhci_sparx5_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .adma_write_desc = sdhci_sparx5_adma_write_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct sdhci_pltfm_data sdhci_sparx5_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .quirks = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .quirks2 = SDHCI_QUIRK2_HOST_NO_CMD23 | /* Controller issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SDHCI_QUIRK2_NO_1_8_V, /* No sdr104, ddr50, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .ops = &sdhci_sparx5_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int sdhci_sparx5_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) const char *syscon = "microchip,sparx5-cpu-syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct sdhci_sparx5_data *sdhci_sparx5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 extra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) host = sdhci_pltfm_init(pdev, &sdhci_sparx5_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) sizeof(*sdhci_sparx5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * extra adma table cnt for cross 128M boundary handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (extra > SDHCI_MAX_SEGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) extra = SDHCI_MAX_SEGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) host->adma_table_cnt += extra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) sdhci_sparx5->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (IS_ERR(pltfm_host->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = PTR_ERR(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_err(&pdev->dev, "failed to get core clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) goto free_pltfm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = clk_prepare_enable(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) goto free_pltfm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!of_property_read_u32(np, "microchip,clock-delay", &value) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) (value > 0 && value <= MSHC_DLY_CC_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) sdhci_sparx5->delay_clock = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) sdhci_get_of_property(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) sdhci_sparx5->cpu_ctrl = syscon_regmap_lookup_by_compatible(syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (IS_ERR(sdhci_sparx5->cpu_ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev_err(&pdev->dev, "No CPU syscon regmap !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = PTR_ERR(sdhci_sparx5->cpu_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (sdhci_sparx5->delay_clock >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) sparx5_set_delay(host, sdhci_sparx5->delay_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!mmc_card_is_removable(host->mmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Do a HW reset of eMMC card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) sdhci_sparx5_reset_emmc(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Update EMMC_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) sdhci_sparx5_set_emmc(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* If eMMC, disable SD and SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) host->mmc->caps2 |= (MMC_CAP2_NO_SDIO|MMC_CAP2_NO_SD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Set AXI bus master to use un-cached access (for DMA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) IS_ENABLED(CONFIG_DMA_DECLARE_COHERENT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) sparx5_set_cacheable(host, ACP_CACHE_FORCE_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pr_debug("%s: SDHC version: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pr_debug("%s: SDHC type: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) clk_disable_unprepare(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) free_pltfm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const struct of_device_id sdhci_sparx5_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { .compatible = "microchip,dw-sparx5-sdhci" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MODULE_DEVICE_TABLE(of, sdhci_sparx5_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static struct platform_driver sdhci_sparx5_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .name = "sdhci-sparx5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .of_match_table = sdhci_sparx5_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .pm = &sdhci_pltfm_pmops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .probe = sdhci_sparx5_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .remove = sdhci_pltfm_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) module_platform_driver(sdhci_sparx5_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_DESCRIPTION("Sparx5 SDHCI OF driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_AUTHOR("Lars Povlsen <lars.povlsen@microchip.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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