^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale eSDHC controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2009 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2020 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Authors: Xiaobo Xie <X.Xie@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Anton Vorontsov <avorontsov@ru.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "sdhci-esdhc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VENDOR_V_22 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VENDOR_V_23 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct esdhc_clk_fixup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) const unsigned int sd_dflt_max_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const unsigned int max_clk[MMC_TIMING_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct esdhc_clk_fixup ls1021a_esdhc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .sd_dflt_max_clk = 25000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .max_clk[MMC_TIMING_MMC_HS] = 46500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .max_clk[MMC_TIMING_SD_HS] = 46500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct esdhc_clk_fixup ls1046a_esdhc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .sd_dflt_max_clk = 25000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .max_clk[MMC_TIMING_MMC_HS200] = 167000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const struct esdhc_clk_fixup ls1012a_esdhc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .sd_dflt_max_clk = 25000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .max_clk[MMC_TIMING_UHS_SDR104] = 125000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .max_clk[MMC_TIMING_MMC_HS200] = 125000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct esdhc_clk_fixup p1010_esdhc_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .sd_dflt_max_clk = 20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .max_clk[MMC_TIMING_LEGACY] = 20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .max_clk[MMC_TIMING_MMC_HS] = 42000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .max_clk[MMC_TIMING_SD_HS] = 40000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct of_device_id sdhci_esdhc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { .compatible = "fsl,mpc8379-esdhc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { .compatible = "fsl,mpc8536-esdhc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { .compatible = "fsl,esdhc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct sdhci_esdhc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 vendor_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 spec_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) bool quirk_incorrect_hostver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) bool quirk_limited_clk_division;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bool quirk_unreliable_pulse_detection;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) bool quirk_tuning_erratum_type1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bool quirk_tuning_erratum_type2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bool quirk_ignore_data_inhibit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) bool quirk_delay_before_data_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) bool quirk_trans_complete_erratum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bool in_sw_tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int peripheral_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const struct esdhc_clk_fixup *clk_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 div_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * to make it compatible with SD spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @host: pointer to sdhci_host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @spec_reg: SD spec register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @value: 32bit eSDHC register value on spec_reg address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * registers are 32 bits. There are differences in register size, register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * address, register function, bit position and function between eSDHC spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * and SD spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Return a fixed up register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static u32 esdhc_readl_fixup(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int spec_reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * The bit of ADMA flag in eSDHC is not compatible with standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * supported by eSDHC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * And for many FSL eSDHC controller, the reset value of field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * only these vendor version is greater than 2.2/0x12 support ADMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (esdhc->vendor_ver > VENDOR_V_22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret = value | SDHCI_CAN_DO_ADMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * The DAT[3:0] line signal levels and the CMD line signal level are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * not compatible with standard SDHC register. The line signal levels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * DAT[7:0] are at bits 31:24 and the command line signal level is at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * bit 23. All other bits are the same as in the standard SDHC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (spec_reg == SDHCI_PRESENT_STATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = value & 0x000fffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret |= (value >> 4) & SDHCI_DATA_LVL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret |= (value << 1) & SDHCI_CMD_LVL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * DTS properties of mmc host are used to enable each speed mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * according to soc and board capability. So clean up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * SDR50/SDR104/DDR50 support bits here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (spec_reg == SDHCI_CAPABILITIES_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) SDHCI_SUPPORT_DDR50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Some controllers have unreliable Data Line Active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * bit for commands with busy signal. This affects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Command Inhibit (data) bit. Just ignore it since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * MMC core driver has already polled card status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * with CMD13 after any command with busy siganl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if ((spec_reg == SDHCI_PRESENT_STATE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) (esdhc->quirk_ignore_data_inhibit == true)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ret = value & ~SDHCI_DATA_INHIBIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static u16 esdhc_readw_fixup(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int spec_reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u16 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int shift = (spec_reg & 0x2) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (spec_reg == SDHCI_TRANSFER_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return pltfm_host->xfer_mode_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (spec_reg == SDHCI_HOST_VERSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = value & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = (value >> shift) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * vendor version and spec version information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if ((spec_reg == SDHCI_HOST_VERSION) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) (esdhc->quirk_incorrect_hostver))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static u8 esdhc_readb_fixup(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int spec_reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 dma_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int shift = (spec_reg & 0x3) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret = (value >> shift) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * "DMA select" locates at offset 0x28 in SD specification, but on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * P5020 or P3041, it locates at 0x29.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (spec_reg == SDHCI_HOST_CONTROL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* DMA select is 22,23 bits in Protocol Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* fixup the result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ret &= ~SDHCI_CTRL_DMA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret |= dma_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * esdhc_write*_fixup - Fixup the SD spec register value so that it could be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * written into eSDHC register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @host: pointer to sdhci_host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @spec_reg: SD spec register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @value: 8/16/32bit SD spec register value that would be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @old_value: 32bit eSDHC register value on spec_reg address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * registers are 32 bits. There are differences in register size, register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * address, register function, bit position and function between eSDHC spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * and SD spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Return a fixed up register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static u32 esdhc_writel_fixup(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int spec_reg, u32 value, u32 old_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * when SYSCTL[RSTD] is set for some special operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * No any impact on other operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (spec_reg == SDHCI_INT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = value | SDHCI_INT_BLK_GAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static u32 esdhc_writew_fixup(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int spec_reg, u16 value, u32 old_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int shift = (spec_reg & 0x2) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) switch (spec_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case SDHCI_TRANSFER_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Postpone this write, we must do it together with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * command write that is down below. Return old value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pltfm_host->xfer_mode_shadow = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return old_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case SDHCI_COMMAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = (value << 16) | pltfm_host->xfer_mode_shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = old_value & (~(0xffff << shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ret |= (value << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (spec_reg == SDHCI_BLOCK_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * Two last DMA bits are reserved, and first one is used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * non-standard blksz of 4096 bytes that we don't support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * yet. So clear the DMA boundary bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static u32 esdhc_writeb_fixup(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int spec_reg, u8 value, u32 old_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 dma_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int shift = (spec_reg & 0x3) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * eSDHC doesn't have a standard power control register, so we do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * nothing here to avoid incorrect operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (spec_reg == SDHCI_POWER_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return old_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * "DMA select" location is offset 0x28 in SD specification, but on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * P5020 or P3041, it's located at 0x29.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (spec_reg == SDHCI_HOST_CONTROL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * If host control register is not standard, exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return old_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* DMA select is 22,23 bits in Protocol Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) (old_value & SDHCI_CTRL_DMA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = (ret & (~0xff)) | tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret &= ~ESDHC_HOST_CONTROL_RES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = (old_value & (~(0xff << shift))) | (value << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (reg == SDHCI_CAPABILITIES_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) value = ioread32be(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = esdhc_readl_fixup(host, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (reg == SDHCI_CAPABILITIES_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) value = ioread32(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ret = esdhc_readl_fixup(host, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u16 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int base = reg & ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) value = ioread32be(host->ioaddr + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = esdhc_readw_fixup(host, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u16 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int base = reg & ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) value = ioread32(host->ioaddr + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = esdhc_readw_fixup(host, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u8 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int base = reg & ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) value = ioread32be(host->ioaddr + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret = esdhc_readb_fixup(host, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u8 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int base = reg & ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) value = ioread32(host->ioaddr + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ret = esdhc_readb_fixup(host, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) value = esdhc_writel_fixup(host, reg, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) iowrite32be(value, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) value = esdhc_writel_fixup(host, reg, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) iowrite32(value, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int base = reg & ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) value = ioread32be(host->ioaddr + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = esdhc_writew_fixup(host, reg, val, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (reg != SDHCI_TRANSFER_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) iowrite32be(ret, host->ioaddr + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Starting SW tuning requires ESDHC_SMPCLKSEL to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * 1us later after ESDHC_EXTN is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (base == ESDHC_SYSTEM_CONTROL_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) esdhc->in_sw_tuning) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret |= ESDHC_SMPCLKSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) iowrite32be(ret, host->ioaddr + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int base = reg & ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) value = ioread32(host->ioaddr + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = esdhc_writew_fixup(host, reg, val, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (reg != SDHCI_TRANSFER_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) iowrite32(ret, host->ioaddr + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Starting SW tuning requires ESDHC_SMPCLKSEL to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * 1us later after ESDHC_EXTN is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (base == ESDHC_SYSTEM_CONTROL_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (!(value & ESDHC_EXTN) && (ret & ESDHC_EXTN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) esdhc->in_sw_tuning) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret |= ESDHC_SMPCLKSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) iowrite32(ret, host->ioaddr + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int base = reg & ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) value = ioread32be(host->ioaddr + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret = esdhc_writeb_fixup(host, reg, val, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) iowrite32be(ret, host->ioaddr + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int base = reg & ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) value = ioread32(host->ioaddr + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = esdhc_writeb_fixup(host, reg, val, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) iowrite32(ret, host->ioaddr + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * and Block Gap Event(IRQSTAT[BGE]) are also set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * For Continue, apply soft reset for data(SYSCTL[RSTD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * and re-issue the entire read transaction from beginning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) bool applicable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dma_addr_t dmastart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dma_addr_t dmanow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) applicable = (intmask & SDHCI_INT_DATA_END) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) (intmask & SDHCI_INT_BLK_GAP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) (esdhc->vendor_ver == VENDOR_V_23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (!applicable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) host->data->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dmastart = sg_dma_address(host->data->sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dmanow = dmastart + host->data->bytes_xfered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * Force update to the next DMA block boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) SDHCI_DEFAULT_BOUNDARY_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) host->data->bytes_xfered = dmanow - dmastart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int esdhc_of_enable_dma(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct device *dev = mmc_dev(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (of_dma_is_coherent(dev->of_node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) value |= ESDHC_DMA_SNOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) value &= ~ESDHC_DMA_SNOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (esdhc->peripheral_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return esdhc->peripheral_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return pltfm_host->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) unsigned int clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (esdhc->peripheral_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) clock = esdhc->peripheral_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) clock = pltfm_host->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return clock / 256 / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static void esdhc_clock_enable(struct sdhci_host *host, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ktime_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u32 val, clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) clk_en = ESDHC_CLOCK_SDCLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * IPGEN/HCKEN/PEREN bits exist on eSDHC whose vendor version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * is 2.2 or lower.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (esdhc->vendor_ver <= VENDOR_V_22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) clk_en |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ESDHC_CLOCK_PEREN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) val |= clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) val &= ~clk_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * Wait max 20 ms. If vendor version is 2.2 or lower, do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * wait clock stable bit which does not exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) timeout = ktime_add_ms(ktime_get(), 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) while (esdhc->vendor_ver > VENDOR_V_22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) bool timedout = ktime_after(ktime_get(), timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (timedout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) pr_err("%s: Internal clock never stabilised.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static void esdhc_flush_async_fifo(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ktime_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) val |= ESDHC_FLUSH_ASYNC_FIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Wait max 20 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) timeout = ktime_add_ms(ktime_get(), 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) bool timedout = ktime_after(ktime_get(), timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ESDHC_FLUSH_ASYNC_FIFO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (timedout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) pr_err("%s: flushing asynchronous FIFO timeout.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) unsigned int pre_div = 1, div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) unsigned int clock_fixup = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ktime_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (clock == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) host->mmc->actual_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) esdhc_clock_enable(host, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Start pre_div at 2 for vendor version < 2.3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (esdhc->vendor_ver < VENDOR_V_23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) pre_div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* Fix clock value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (host->mmc->card && mmc_card_sd(host->mmc->card) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) clock_fixup = esdhc->clk_fixup->sd_dflt_max_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) else if (esdhc->clk_fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) clock_fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (clock_fixup == 0 || clock < clock_fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) clock_fixup = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Calculate pre_div and div. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) while (host->max_clk / pre_div / 16 > clock_fixup && pre_div < 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) pre_div *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) while (host->max_clk / pre_div / div > clock_fixup && div < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) esdhc->div_ratio = pre_div * div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Limit clock division for HS400 200MHz clock for quirk. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (esdhc->quirk_limited_clk_division &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) clock == MMC_HS200_MAX_DTR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) host->flags & SDHCI_HS400_TUNING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (esdhc->div_ratio <= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) pre_div = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) } else if (esdhc->div_ratio <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) pre_div = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) } else if (esdhc->div_ratio <= 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) pre_div = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) div = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) pr_warn("%s: using unsupported clock division.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) esdhc->div_ratio = pre_div * div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) host->mmc->actual_clock = host->max_clk / esdhc->div_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) clock, host->mmc->actual_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* Set clock division into register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) pre_div >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) div--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) esdhc_clock_enable(host, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) temp &= ~ESDHC_CLOCK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) temp |= ((div << ESDHC_DIVIDER_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) (pre_div << ESDHC_PREDIV_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * Wait max 20 ms. If vendor version is 2.2 or lower, do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * wait clock stable bit which does not exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) timeout = ktime_add_ms(ktime_get(), 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) while (esdhc->vendor_ver > VENDOR_V_22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) bool timedout = ktime_after(ktime_get(), timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (timedout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) pr_err("%s: Internal clock never stabilised.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Additional setting for HS400. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) clock == MMC_HS200_MAX_DTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) temp = sdhci_readl(host, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) temp = sdhci_readl(host, ESDHC_SDCLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) esdhc_clock_enable(host, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) temp = sdhci_readl(host, ESDHC_DLLCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) temp |= ESDHC_DLL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (host->mmc->actual_clock == MMC_HS200_MAX_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) temp |= ESDHC_DLL_FREQ_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) sdhci_writel(host, temp, ESDHC_DLLCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) temp |= ESDHC_DLL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) sdhci_writel(host, temp, ESDHC_DLLCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) temp &= ~ESDHC_DLL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) sdhci_writel(host, temp, ESDHC_DLLCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* Wait max 20 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (read_poll_timeout(sdhci_readl, temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) temp & ESDHC_DLL_STS_SLV_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 10, 20000, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) host, ESDHC_DLLSTAT0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) pr_err("%s: timeout for delay chain lock.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) temp = sdhci_readl(host, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) esdhc_clock_enable(host, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) esdhc_flush_async_fifo(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) esdhc_clock_enable(host, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ctrl = sdhci_readl(host, ESDHC_PROCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case MMC_BUS_WIDTH_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ctrl |= ESDHC_CTRL_8BITBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) case MMC_BUS_WIDTH_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ctrl |= ESDHC_CTRL_4BITBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) sdhci_writel(host, ctrl, ESDHC_PROCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static void esdhc_reset(struct sdhci_host *host, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u32 val, bus_width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * Add delay to make sure all the DMA transfers are finished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * for quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (esdhc->quirk_delay_before_data_reset &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) (mask & SDHCI_RESET_DATA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) (host->flags & SDHCI_REQ_USE_DMA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mdelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * Save bus-width for eSDHC whose vendor version is 2.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * or lower for data reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if ((mask & SDHCI_RESET_DATA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) (esdhc->vendor_ver <= VENDOR_V_22)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) val = sdhci_readl(host, ESDHC_PROCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) bus_width = val & ESDHC_CTRL_BUSWIDTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) sdhci_reset(host, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * Restore bus-width setting and interrupt registers for eSDHC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * whose vendor version is 2.2 or lower for data reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if ((mask & SDHCI_RESET_DATA) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) (esdhc->vendor_ver <= VENDOR_V_22)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) val = sdhci_readl(host, ESDHC_PROCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) val &= ~ESDHC_CTRL_BUSWIDTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) val |= bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) sdhci_writel(host, val, ESDHC_PROCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * Some bits have to be cleaned manually for eSDHC whose spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * version is higher than 3.0 for all reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if ((mask & SDHCI_RESET_ALL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) (esdhc->spec_ver >= SDHCI_SPEC_300)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) val = sdhci_readl(host, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) val &= ~ESDHC_TB_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) sdhci_writel(host, val, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * Initialize eSDHC_DLLCFG1[DLL_PD_PULSE_STRETCH_SEL] to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * 0 for quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (esdhc->quirk_unreliable_pulse_detection) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) val = sdhci_readl(host, ESDHC_DLLCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) sdhci_writel(host, val, ESDHC_DLLCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* The SCFG, Supplemental Configuration Unit, provides SoC specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * configuration and status registers for the device. There is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * SDHC IO VSEL control register on SCFG for some platforms. It's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * used to support SDHC IO voltage switching.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static const struct of_device_id scfg_device_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) { .compatible = "fsl,t1040-scfg", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) { .compatible = "fsl,ls1012a-scfg", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) { .compatible = "fsl,ls1046a-scfg", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* SDHC IO VSEL control register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define SCFG_SDHCIOVSELCR 0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define SDHCIOVSELCR_TGLEN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define SDHCIOVSELCR_VSELVAL 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define SDHCIOVSELCR_SDHC_VS 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static int esdhc_signal_voltage_switch(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct device_node *scfg_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) void __iomem *scfg_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u32 sdhciovselcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * Signal Voltage Switching is only applicable for Host Controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * v3.00 and above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (host->version < SDHCI_SPEC_300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) val = sdhci_readl(host, ESDHC_PROCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) switch (ios->signal_voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case MMC_SIGNAL_VOLTAGE_330:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) val &= ~ESDHC_VOLT_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) sdhci_writel(host, val, ESDHC_PROCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) case MMC_SIGNAL_VOLTAGE_180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) scfg_node = of_find_matching_node(NULL, scfg_device_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (scfg_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) scfg_base = of_iomap(scfg_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (scfg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) sdhciovselcr = SDHCIOVSELCR_TGLEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) SDHCIOVSELCR_VSELVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) iowrite32be(sdhciovselcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) scfg_base + SCFG_SDHCIOVSELCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) val |= ESDHC_VOLT_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) sdhci_writel(host, val, ESDHC_PROCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) mdelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) sdhciovselcr = SDHCIOVSELCR_TGLEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) SDHCIOVSELCR_SDHC_VS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) iowrite32be(sdhciovselcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) scfg_base + SCFG_SDHCIOVSELCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) iounmap(scfg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) val |= ESDHC_VOLT_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) sdhci_writel(host, val, ESDHC_PROCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static struct soc_device_attribute soc_tuning_erratum_type1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) { .family = "QorIQ T1023", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) { .family = "QorIQ T1040", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) { .family = "QorIQ T2080", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) { .family = "QorIQ LS1021A", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static struct soc_device_attribute soc_tuning_erratum_type2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) { .family = "QorIQ LS1012A", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) { .family = "QorIQ LS1043A", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) { .family = "QorIQ LS1046A", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) { .family = "QorIQ LS1080A", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) { .family = "QorIQ LS2080A", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) { .family = "QorIQ LA1575A", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) esdhc_clock_enable(host, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) esdhc_flush_async_fifo(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) val = sdhci_readl(host, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) val |= ESDHC_TB_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) val &= ~ESDHC_TB_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) sdhci_writel(host, val, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) esdhc_clock_enable(host, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static void esdhc_tuning_window_ptr(struct sdhci_host *host, u8 *window_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u8 *window_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* Write TBCTL[11:8]=4'h8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) val = sdhci_readl(host, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) val &= ~(0xf << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) val |= 8 << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) sdhci_writel(host, val, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* Read TBCTL[31:0] register and rewrite again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) val = sdhci_readl(host, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) sdhci_writel(host, val, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* Read the TBSTAT[31:0] register twice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) val = sdhci_readl(host, ESDHC_TBSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) val = sdhci_readl(host, ESDHC_TBSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) *window_end = val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) *window_start = (val >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static void esdhc_prepare_sw_tuning(struct sdhci_host *host, u8 *window_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) u8 *window_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) u8 start_ptr, end_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (esdhc->quirk_tuning_erratum_type1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) *window_start = 5 * esdhc->div_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) *window_end = 3 * esdhc->div_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) esdhc_tuning_window_ptr(host, &start_ptr, &end_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* Reset data lines by setting ESDHCCTL[RSTD] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) sdhci_reset(host, SDHCI_RESET_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* Write 32'hFFFF_FFFF to IRQSTAT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) sdhci_writel(host, 0xFFFFFFFF, SDHCI_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* If TBSTAT[15:8]-TBSTAT[7:0] > (4 * div_ratio) + 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * or TBSTAT[7:0]-TBSTAT[15:8] > (4 * div_ratio) + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * then program TBPTR[TB_WNDW_END_PTR] = 4 * div_ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * and program TBPTR[TB_WNDW_START_PTR] = 8 * div_ratio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (abs(start_ptr - end_ptr) > (4 * esdhc->div_ratio + 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) *window_start = 8 * esdhc->div_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) *window_end = 4 * esdhc->div_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) *window_start = 5 * esdhc->div_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) *window_end = 3 * esdhc->div_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static int esdhc_execute_sw_tuning(struct mmc_host *mmc, u32 opcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) u8 window_start, u8 window_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* Program TBPTR[TB_WNDW_END_PTR] and TBPTR[TB_WNDW_START_PTR] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) val = ((u32)window_start << ESDHC_WNDW_STRT_PTR_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ESDHC_WNDW_STRT_PTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) val |= window_end & ESDHC_WNDW_END_PTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) sdhci_writel(host, val, ESDHC_TBPTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* Program the software tuning mode by setting TBCTL[TB_MODE]=2'h3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) val = sdhci_readl(host, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) val &= ~ESDHC_TB_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) val |= ESDHC_TB_MODE_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) sdhci_writel(host, val, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) esdhc->in_sw_tuning = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret = sdhci_execute_tuning(mmc, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) esdhc->in_sw_tuning = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) u8 window_start, window_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int ret, retries = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) bool hs400_tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) unsigned int clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* For tuning mode, the sd clock divisor value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * must be larger than 3 according to reference manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) clk = esdhc->peripheral_clock / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (host->clock > clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) esdhc_of_set_clock(host, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) esdhc_tuning_block_enable(host, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * The eSDHC controller takes the data timeout value into account
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * during tuning. If the SD card is too slow sending the response, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * timer will expire and a "Buffer Read Ready" interrupt without data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * is triggered. This leads to tuning errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * Just set the timeout to the maximum value because the core will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * already take care of it in sdhci_send_tuning().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) hs400_tuning = host->flags & SDHCI_HS400_TUNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (esdhc->quirk_limited_clk_division &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) hs400_tuning)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) esdhc_of_set_clock(host, host->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* Do HW tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) val = sdhci_readl(host, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) val &= ~ESDHC_TB_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) val |= ESDHC_TB_MODE_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) sdhci_writel(host, val, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ret = sdhci_execute_tuning(mmc, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* For type2 affected platforms of the tuning erratum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * tuning may succeed although eSDHC might not have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * tuned properly. Need to check tuning window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (esdhc->quirk_tuning_erratum_type2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) !host->tuning_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) esdhc_tuning_window_ptr(host, &window_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) &window_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (abs(window_start - window_end) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) (4 * esdhc->div_ratio + 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) host->tuning_err = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /* If HW tuning fails and triggers erratum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * try workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ret = host->tuning_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (ret == -EAGAIN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) (esdhc->quirk_tuning_erratum_type1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) esdhc->quirk_tuning_erratum_type2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* Recover HS400 tuning flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (hs400_tuning)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) host->flags |= SDHCI_HS400_TUNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) pr_info("%s: Hold on to use fixed sampling clock. Try SW tuning!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) mmc_hostname(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* Do SW tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) esdhc_prepare_sw_tuning(host, &window_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) &window_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ret = esdhc_execute_sw_tuning(mmc, opcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) window_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) window_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /* Retry both HW/SW tuning with reduced clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret = host->tuning_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (ret == -EAGAIN && retries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Recover HS400 tuning flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (hs400_tuning)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) host->flags |= SDHCI_HS400_TUNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) clk = host->max_clk / (esdhc->div_ratio + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) esdhc_of_set_clock(host, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pr_info("%s: Hold on to use fixed sampling clock. Try tuning with reduced clock!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) mmc_hostname(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) } while (retries--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) esdhc_tuning_block_enable(host, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) } else if (hs400_tuning) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) val |= ESDHC_FLW_CTL_BG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static void esdhc_set_uhs_signaling(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) unsigned int timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * There are specific registers setting for HS400 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * Clean all of them if controller is in HS400 mode to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * exit HS400 mode before re-setting any speed mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) val = sdhci_readl(host, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (val & ESDHC_HS400_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) val = sdhci_readl(host, ESDHC_SDTIMNGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) val &= ~ESDHC_FLW_CTL_BG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) sdhci_writel(host, val, ESDHC_SDTIMNGCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) val = sdhci_readl(host, ESDHC_SDCLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) val &= ~ESDHC_CMD_CLK_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) sdhci_writel(host, val, ESDHC_SDCLKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) esdhc_clock_enable(host, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) val = sdhci_readl(host, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) val &= ~ESDHC_HS400_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) sdhci_writel(host, val, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) esdhc_clock_enable(host, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) val = sdhci_readl(host, ESDHC_DLLCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) val &= ~(ESDHC_DLL_ENABLE | ESDHC_DLL_FREQ_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) sdhci_writel(host, val, ESDHC_DLLCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) val = sdhci_readl(host, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) val &= ~ESDHC_HS400_WNDW_ADJUST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) sdhci_writel(host, val, ESDHC_TBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) esdhc_tuning_block_enable(host, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (timing == MMC_TIMING_MMC_HS400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) esdhc_tuning_block_enable(host, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) sdhci_set_uhs_signaling(host, timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static u32 esdhc_irq(struct sdhci_host *host, u32 intmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) u32 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (esdhc->quirk_trans_complete_erratum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) command = SDHCI_GET_CMD(sdhci_readw(host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) SDHCI_COMMAND));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (command == MMC_WRITE_MULTIPLE_BLOCK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) sdhci_readw(host, SDHCI_BLOCK_COUNT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) intmask & SDHCI_INT_DATA_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) intmask &= ~SDHCI_INT_DATA_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) sdhci_writel(host, SDHCI_INT_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) SDHCI_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static u32 esdhc_proctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static int esdhc_of_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (host->tuning_mode != SDHCI_TUNING_MODE_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) mmc_retune_needed(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return sdhci_suspend_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static int esdhc_of_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) int ret = sdhci_resume_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) /* Isn't this already done by sdhci_resume_host() ? --rmk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) esdhc_of_enable_dma(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) esdhc_of_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) esdhc_of_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static const struct sdhci_ops sdhci_esdhc_be_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .read_l = esdhc_be_readl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .read_w = esdhc_be_readw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .read_b = esdhc_be_readb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .write_l = esdhc_be_writel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .write_w = esdhc_be_writew,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .write_b = esdhc_be_writeb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .set_clock = esdhc_of_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .enable_dma = esdhc_of_enable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .get_max_clock = esdhc_of_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .get_min_clock = esdhc_of_get_min_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .adma_workaround = esdhc_of_adma_workaround,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .set_bus_width = esdhc_pltfm_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .reset = esdhc_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .set_uhs_signaling = esdhc_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .irq = esdhc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static const struct sdhci_ops sdhci_esdhc_le_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .read_l = esdhc_le_readl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .read_w = esdhc_le_readw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .read_b = esdhc_le_readb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .write_l = esdhc_le_writel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .write_w = esdhc_le_writew,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .write_b = esdhc_le_writeb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .set_clock = esdhc_of_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .enable_dma = esdhc_of_enable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .get_max_clock = esdhc_of_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .get_min_clock = esdhc_of_get_min_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .adma_workaround = esdhc_of_adma_workaround,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .set_bus_width = esdhc_pltfm_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .reset = esdhc_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .set_uhs_signaling = esdhc_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .irq = esdhc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .quirks = ESDHC_DEFAULT_QUIRKS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #ifdef CONFIG_PPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) SDHCI_QUIRK_BROKEN_CARD_DETECTION |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) SDHCI_QUIRK_NO_CARD_NO_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .ops = &sdhci_esdhc_be_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .quirks = ESDHC_DEFAULT_QUIRKS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) SDHCI_QUIRK_NO_CARD_NO_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .ops = &sdhci_esdhc_le_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static struct soc_device_attribute soc_incorrect_hostver[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) { .family = "QorIQ T4240", .revision = "1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) { .family = "QorIQ T4240", .revision = "2.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) { .family = "QorIQ LX2160A", .revision = "1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) { .family = "QorIQ LX2160A", .revision = "2.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) { .family = "QorIQ LS1028A", .revision = "1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static struct soc_device_attribute soc_unreliable_pulse_detection[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) { .family = "QorIQ LX2160A", .revision = "1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) { .family = "QorIQ LX2160A", .revision = "2.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) { .family = "QorIQ LS1028A", .revision = "1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct sdhci_esdhc *esdhc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) u16 host_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) SDHCI_VENDOR_VER_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (soc_device_match(soc_incorrect_hostver))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) esdhc->quirk_incorrect_hostver = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) esdhc->quirk_incorrect_hostver = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (soc_device_match(soc_fixup_sdhc_clkdivs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) esdhc->quirk_limited_clk_division = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) esdhc->quirk_limited_clk_division = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (soc_device_match(soc_unreliable_pulse_detection))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) esdhc->quirk_unreliable_pulse_detection = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) esdhc->quirk_unreliable_pulse_detection = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) esdhc->clk_fixup = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) esdhc->quirk_delay_before_data_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) esdhc->quirk_trans_complete_erratum = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * esdhc->peripheral_clock would be assigned with a value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * which is eSDHC base clock when use periperal clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * For some platforms, the clock value got by common clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * API is peripheral clock while the eSDHC base clock is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * 1/2 peripheral clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) of_device_is_compatible(np, "fsl,ls1028a-esdhc") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) of_device_is_compatible(np, "fsl,ls1088a-esdhc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) esdhc->peripheral_clock = clk_get_rate(clk) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) esdhc->peripheral_clock = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) esdhc_clock_enable(host, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) val = sdhci_readl(host, ESDHC_DMA_SYSCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * This bit is not able to be reset by SDHCI_RESET_ALL. Need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * initialize it as 1 or 0 once, to override the different value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * which may be configured in bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (esdhc->peripheral_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) val |= ESDHC_PERIPHERAL_CLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) val &= ~ESDHC_PERIPHERAL_CLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) sdhci_writel(host, val, ESDHC_DMA_SYSCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) esdhc_clock_enable(host, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) esdhc_tuning_block_enable(mmc_priv(mmc), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static int sdhci_esdhc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) struct sdhci_esdhc *esdhc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (of_property_read_bool(np, "little-endian"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) sizeof(struct sdhci_esdhc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) sizeof(struct sdhci_esdhc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) host->mmc_host_ops.start_signal_voltage_switch =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) esdhc_signal_voltage_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) host->mmc_host_ops.execute_tuning = esdhc_execute_tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) host->tuning_delay = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) esdhc_init(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) sdhci_get_of_property(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) esdhc = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (soc_device_match(soc_tuning_erratum_type1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) esdhc->quirk_tuning_erratum_type1 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) esdhc->quirk_tuning_erratum_type1 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (soc_device_match(soc_tuning_erratum_type2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) esdhc->quirk_tuning_erratum_type2 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) esdhc->quirk_tuning_erratum_type2 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (esdhc->vendor_ver == VENDOR_V_22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (esdhc->vendor_ver > VENDOR_V_22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) host->quirks |= SDHCI_QUIRK_RESET_AFTER_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) of_device_is_compatible(np, "fsl,p5020-esdhc") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) of_device_is_compatible(np, "fsl,p4080-esdhc") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) of_device_is_compatible(np, "fsl,p1020-esdhc") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) of_device_is_compatible(np, "fsl,t1040-esdhc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) esdhc->quirk_ignore_data_inhibit = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) * Freescale messed up with P2020 as it has a non-standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) * host control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) esdhc->quirk_ignore_data_inhibit = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* call to generic mmc_of_parse to support additional capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ret = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) mmc_of_parse_voltage(np, &host->ocr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) ret = sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static struct platform_driver sdhci_esdhc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .name = "sdhci-esdhc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .of_match_table = sdhci_esdhc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .pm = &esdhc_of_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .probe = sdhci_esdhc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .remove = sdhci_pltfm_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) module_platform_driver(sdhci_esdhc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) "Anton Vorontsov <avorontsov@ru.mvista.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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