Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Atmel SDMMC controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015 Atmel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *		 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SDMMC_MC1R	0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define		SDMMC_MC1R_DDR		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define		SDMMC_MC1R_FCD		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SDMMC_CACR	0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define		SDMMC_CACR_CAPWREN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define		SDMMC_CACR_KEY		(0x46 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SDMMC_CALCR	0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define		SDMMC_CALCR_EN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define		SDMMC_CALCR_ALWYSON	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SDHCI_AT91_PRESET_COMMON_CONF	0x400 /* drv type B, programmable clock mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct sdhci_at91_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	const struct sdhci_pltfm_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	bool baseclk_is_generated_internally;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	unsigned int divider_for_baseclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct sdhci_at91_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	const struct sdhci_at91_soc_data *soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct clk *hclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct clk *gck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct clk *mainck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	bool restore_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	bool cal_always_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u8 mc1r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	mc1r = readb(host->ioaddr + SDMMC_MC1R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	mc1r |= SDMMC_MC1R_FCD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	writeb(mc1r, host->ioaddr + SDMMC_MC1R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u16 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	host->mmc->actual_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 * There is no requirement to disable the internal clock before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	 * changing the SD clock configuration. Moreover, disabling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * internal clock, changing the configuration and re-enabling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 * internal clock causes some bugs. It can prevent to get the internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 * clock stable flag ready and an unexpected switch to the base clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 * when using presets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	clk &= SDHCI_CLOCK_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (clock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	clk |= SDHCI_CLOCK_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	/* Wait max 20 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (read_poll_timeout(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			      1000, 20000, false, host, SDHCI_CLOCK_CONTROL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		pr_err("%s: Internal clock never stabilised.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		       mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	clk |= SDHCI_CLOCK_CARD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 					 unsigned int timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if (timing == MMC_TIMING_MMC_DDR52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	sdhci_set_uhs_signaling(host, timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	sdhci_reset(host, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	    || mmc_gpio_get_cd(host->mmc) >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		sdhci_at91_set_force_card_detect(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (priv->cal_always_on && (mask & SDHCI_RESET_ALL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		u32 calcr = sdhci_readl(host, SDMMC_CALCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		sdhci_writel(host, calcr | SDMMC_CALCR_ALWYSON | SDMMC_CALCR_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			     SDMMC_CALCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		if (read_poll_timeout(sdhci_readl, tmp, !(tmp & SDMMC_CALCR_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				      10, 20000, false, host, SDMMC_CALCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			dev_err(mmc_dev(host->mmc), "Failed to calibrate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.set_clock		= sdhci_at91_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.set_bus_width		= sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.reset			= sdhci_at91_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.set_uhs_signaling	= sdhci_at91_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.set_power		= sdhci_set_power_and_bus_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.ops = &sdhci_at91_sama5d2_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct sdhci_at91_soc_data soc_data_sama5d2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.pdata = &sdhci_sama5d2_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.baseclk_is_generated_internally = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct sdhci_at91_soc_data soc_data_sam9x60 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.pdata = &sdhci_sama5d2_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.baseclk_is_generated_internally = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.divider_for_baseclk = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct of_device_id sdhci_at91_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	{ .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	{ .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int sdhci_at91_set_clks_presets(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	unsigned int			caps0, caps1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	unsigned int			clk_base, clk_mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	unsigned int			gck_rate, clk_base_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	unsigned int			preset_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	clk_prepare_enable(priv->hclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	gck_rate = clk_get_rate(priv->gck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (priv->soc_data->baseclk_is_generated_internally)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		clk_base_rate = clk_get_rate(priv->mainck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	clk_base = clk_base_rate / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	clk_mul = gck_rate / clk_base_rate - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	caps0 &= ~SDHCI_CLOCK_V3_BASE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	caps0 |= FIELD_PREP(SDHCI_CLOCK_V3_BASE_MASK, clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	caps1 &= ~SDHCI_CLOCK_MUL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	caps1 |= FIELD_PREP(SDHCI_CLOCK_MUL_MASK, clk_mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* Set capabilities in r/w mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	writel(caps0, host->ioaddr + SDHCI_CAPABILITIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/* Set capabilities in ro mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	writel(0, host->ioaddr + SDMMC_CACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	dev_dbg(dev, "update clk mul to %u as gck rate is %u Hz and clk base is %u Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		clk_mul, gck_rate, clk_base_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	 * We have to set preset values because it depends on the clk_mul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	 * value. Moreover, SDR104 is supported in a degraded mode since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	 * maximum sd clock value is 120 MHz instead of 208 MHz. For that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 * reason, we need to use presets to support SDR104.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	preset_div = DIV_ROUND_UP(gck_rate, 24000000) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	       host->ioaddr + SDHCI_PRESET_FOR_SDR12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	       host->ioaddr + SDHCI_PRESET_FOR_SDR25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	       host->ioaddr + SDHCI_PRESET_FOR_SDR50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	       host->ioaddr + SDHCI_PRESET_FOR_SDR104);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	       host->ioaddr + SDHCI_PRESET_FOR_DDR50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	clk_prepare_enable(priv->mainck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	clk_prepare_enable(priv->gck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int sdhci_at91_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	ret = pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	priv->restore_needed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int sdhci_at91_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ret = sdhci_runtime_suspend_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		mmc_retune_needed(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	clk_disable_unprepare(priv->gck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	clk_disable_unprepare(priv->hclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	clk_disable_unprepare(priv->mainck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int sdhci_at91_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (priv->restore_needed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		ret = sdhci_at91_set_clks_presets(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		priv->restore_needed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	ret = clk_prepare_enable(priv->mainck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		dev_err(dev, "can't enable mainck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	ret = clk_prepare_enable(priv->hclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		dev_err(dev, "can't enable hclock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	ret = clk_prepare_enable(priv->gck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		dev_err(dev, "can't enable gck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return sdhci_runtime_resume_host(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			   sdhci_at91_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			   NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int sdhci_at91_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	const struct of_device_id	*match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	const struct sdhci_at91_soc_data	*soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct sdhci_host		*host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	struct sdhci_pltfm_host		*pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	struct sdhci_at91_priv		*priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	int				ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	soc_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	priv->soc_data = soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (IS_ERR(priv->mainck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		if (soc_data->baseclk_is_generated_internally) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			priv->mainck = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			dev_err(&pdev->dev, "failed to get baseclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			ret = PTR_ERR(priv->mainck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			goto sdhci_pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	priv->hclock = devm_clk_get(&pdev->dev, "hclock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (IS_ERR(priv->hclock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		dev_err(&pdev->dev, "failed to get hclock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		ret = PTR_ERR(priv->hclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		goto sdhci_pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	priv->gck = devm_clk_get(&pdev->dev, "multclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (IS_ERR(priv->gck)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		dev_err(&pdev->dev, "failed to get multclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		ret = PTR_ERR(priv->gck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		goto sdhci_pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	ret = sdhci_at91_set_clks_presets(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		goto sdhci_pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	priv->restore_needed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	 * if SDCAL pin is wrongly connected, we must enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	 * the analog calibration cell permanently.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	priv->cal_always_on =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		device_property_read_bool(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 					  "microchip,sdcal-inverted");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	ret = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		goto clocks_disable_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	sdhci_get_of_property(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	/* HS200 is broken at this moment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	ret = sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		goto pm_runtime_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	 * the assumption that all the clocks of the controller are disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	 * It means we can't get irq from it when it is runtime suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	 * For that reason, it is not planned to wake-up on a card detect irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	 * from the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	 * If we want to use runtime PM and to be able to wake-up on card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	 * insertion, we have to use a GPIO for the card detection or we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	 * use polling. Be aware that using polling will resume/suspend the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	 * controller between each attempt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	 * to enable polling via device tree with broken-cd property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	if (mmc_card_is_removable(host->mmc) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	    mmc_gpio_get_cd(host->mmc) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		host->mmc->caps |= MMC_CAP_NEEDS_POLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	 * If the device attached to the MMC bus is not removable, it is safer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	 * to set the Force Card Detect bit. People often don't connect the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	 * card detect signal and use this pin for another purpose. If the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	 * detect pin is not muxed to SDHCI controller, a default value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	 * used. This value can be different from a SoC revision to another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	 * one. Problems come when this default value is not card present. To
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	 * avoid this case, if the device is non removable then the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	 * detection procedure using the SDMCC_CD signal is bypassed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	 * This bit is reset when a software reset for all command is performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	 * so we need to implement our own reset function to set back this bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	 * WA: SAMA5D2 doesn't drive CMD if using CD GPIO line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	if ((host->mmc->caps & MMC_CAP_NONREMOVABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	    || mmc_gpio_get_cd(host->mmc) >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		sdhci_at91_set_force_card_detect(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	pm_runtime_put_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pm_runtime_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) clocks_disable_unprepare:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	clk_disable_unprepare(priv->gck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	clk_disable_unprepare(priv->mainck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	clk_disable_unprepare(priv->hclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) sdhci_pltfm_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int sdhci_at91_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	struct sdhci_host	*host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	struct sdhci_pltfm_host	*pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	struct sdhci_at91_priv	*priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	struct clk *gck = priv->gck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	struct clk *hclock = priv->hclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	struct clk *mainck = priv->mainck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	sdhci_pltfm_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	clk_disable_unprepare(gck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	clk_disable_unprepare(hclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	clk_disable_unprepare(mainck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static struct platform_driver sdhci_at91_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		.name	= "sdhci-at91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		.of_match_table = sdhci_at91_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		.pm	= &sdhci_at91_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	.probe		= sdhci_at91_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	.remove		= sdhci_at91_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) module_platform_driver(sdhci_at91_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MODULE_DESCRIPTION("SDHCI driver for at91");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MODULE_LICENSE("GPL v2");