^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Arasan Secure Digital Host Controller Interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2012 Wind River Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2013 Pengutronix e.K.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2013 Xilinx Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on sdhci-of-esdhc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 2007 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (c) 2009 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Authors: Xiaobo Xie <X.Xie@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Anton Vorontsov <avorontsov@ru.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/firmware/xlnx-zynqmp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "cqhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SDHCI_ARASAN_VENDOR_REGISTER 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VENDOR_ENHANCED_STROBE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PHY_CLK_TOO_SLOW_HZ 400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SDHCI_ITAPDLY_CHGWIN 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SDHCI_ITAPDLY_ENABLE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SDHCI_OTAPDLY_ENABLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Default settings for ZynqMP Clock Phases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * On some SoCs the syscon area has a feature where the upper 16-bits of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * each 32-bit register act as a write mask for the lower 16-bits. This allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * atomic updates of the register without locking. This macro is used on SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * that have that feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HIWORD_UPDATE(val, mask, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ((val) << (shift) | (mask) << ((shift) + 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @reg: Offset within the syscon of the register containing this field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @width: Number of bits for this field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @shift: Bit offset within @reg of this field (or -1 if not avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct sdhci_arasan_soc_ctl_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) s16 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @baseclkfreq: Where to find corecfg_baseclkfreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @clockmultiplier: Where to find corecfg_clockmultiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @support64b: Where to find SUPPORT64B bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * It's up to the licensee of the Arsan IP block to make these available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * somewhere if needed. Presumably these will be scattered somewhere that's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * accessible via the syscon API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct sdhci_arasan_soc_ctl_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct sdhci_arasan_soc_ctl_field baseclkfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct sdhci_arasan_soc_ctl_field clockmultiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct sdhci_arasan_soc_ctl_field support64b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) bool hiword_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @sdcardclk_ops: The output clock related operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @sampleclk_ops: The sample clock related operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct sdhci_arasan_clk_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const struct clk_ops *sdcardclk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const struct clk_ops *sampleclk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @sampleclk_hw: Struct for the clock we might provide to a PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @set_clk_delays: Function pointer for setting Clock Delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @clk_of_data: Platform specific runtime clock data storage pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct sdhci_arasan_clk_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct clk_hw sdcardclk_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct clk *sdcardclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct clk_hw sampleclk_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct clk *sampleclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void (*set_clk_delays)(struct sdhci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void *clk_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * struct sdhci_arasan_data - Arasan Controller Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @host: Pointer to the main SDHCI host structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @clk_ahb: Pointer to the AHB clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @phy: Pointer to the generic phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @is_phy_on: True if the PHY is on; false if not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @has_cqe: True if controller has command queuing engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @clk_data: Struct for the Arasan Controller Clock Data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @clk_ops: Struct for the Arasan Controller Clock Operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @soc_ctl_map: Map to get offsets into soc_ctl registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @quirks: Arasan deviations from spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct sdhci_arasan_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct clk *clk_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bool is_phy_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bool has_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct sdhci_arasan_clk_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const struct sdhci_arasan_clk_ops *clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct regmap *soc_ctl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Controller does not have CD wired and will not function normally without */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * internal clock even when the clock isn't stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Some of the Arasan variations might not have timing requirements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * met at 25MHz for Default Speed mode, those controllers work at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * 19MHz instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct sdhci_arasan_of_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) const struct sdhci_pltfm_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) const struct sdhci_arasan_clk_ops *clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .hiword_update = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .hiword_update = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .hiword_update = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .hiword_update = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @host: The sdhci_host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @fld: The field to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @val: The value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Note that if a field is specified as not available (shift < 0) then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * this function will silently return an error code. It will be noisy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * and print errors for any other (unexpected) errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int sdhci_arasan_syscon_write(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) const struct sdhci_arasan_soc_ctl_field *fld,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 reg = fld->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u16 width = fld->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) s16 shift = fld->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Silently return errors for shift < 0 so caller doesn't have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * to check for fields which are optional. For fields that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * are required then caller needs to do something special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (shift < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (sdhci_arasan->soc_ctl_map->hiword_update)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = regmap_write(soc_ctl_base, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) HIWORD_UPDATE(val, GENMASK(width, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = regmap_update_bits(soc_ctl_base, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) GENMASK(shift + width, shift),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) val << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Yell about (unexpected) regmap errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pr_warn("%s: Regmap write fail: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mmc_hostname(host->mmc), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) bool ctrl_phy = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (!IS_ERR(sdhci_arasan->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * If PHY off, set clock to max speed and power PHY on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Although PHY docs apparently suggest power cycling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * when changing the clock the PHY doesn't like to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * powered on while at low speeds like those used in ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * mode. Even worse is powering the PHY on while the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * clock is off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * To workaround the PHY limitations, the best we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * do is to power it on at a faster speed and then slam
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * through low speeds without power cycling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) sdhci_set_clock(host, host->max_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (phy_power_on(sdhci_arasan->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pr_err("%s: Cannot power on phy.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) sdhci_arasan->is_phy_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * We'll now fall through to the below case with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * ctrl_phy = false (so we won't turn off/on). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * sdhci_set_clock() will set the real clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * At higher clock speeds the PHY is fine being power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * cycled and docs say you _should_ power cycle when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * changing clock speeds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ctrl_phy = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ctrl_phy && sdhci_arasan->is_phy_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) phy_power_off(sdhci_arasan->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) sdhci_arasan->is_phy_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Some of the Arasan variations might not have timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * requirements met at 25MHz for Default Speed mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * those controllers work at 19MHz instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (clock == DEFAULT_SPEED_MAX_DTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Set the Input and Output Clock Phase Delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (clk_data->set_clk_delays)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) clk_data->set_clk_delays(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) sdhci_set_clock(host, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * after enabling the clock even though the clock is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * stable. Trying to use a clock without waiting here results
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * in EILSEQ while detecting some older/slower cards. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * chosen delay is the maximum delay from sdhci_set_clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ctrl_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (phy_power_on(sdhci_arasan->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pr_err("%s: Cannot power on phy.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) sdhci_arasan->is_phy_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ios->enhanced_strobe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) vendor |= VENDOR_ENHANCED_STROBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) vendor &= ~VENDOR_ENHANCED_STROBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u8 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) sdhci_reset(host, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) switch (ios->signal_voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case MMC_SIGNAL_VOLTAGE_180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * Plese don't switch to 1V8 as arasan,5.1 doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * actually refer to this setting to indicate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * signal voltage and the state machine will be broken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * actually if we force to enable 1V8. That's something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * like broken quirk but we could work around here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case MMC_SIGNAL_VOLTAGE_330:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case MMC_SIGNAL_VOLTAGE_120:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* We don't support 3V3 and 1V2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const struct sdhci_ops sdhci_arasan_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .set_clock = sdhci_arasan_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .get_max_clock = sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .reset = sdhci_arasan_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .set_power = sdhci_set_power_and_bus_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int cmd_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int data_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) cqhci_irq(host->mmc, intmask, cmd_error, data_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) sdhci_dumpregs(mmc_priv(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) while (reg & SDHCI_DATA_AVAILABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) sdhci_readl(host, SDHCI_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) sdhci_cqe_enable(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .enable = sdhci_arasan_cqe_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .disable = sdhci_cqe_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .dumpregs = sdhci_arasan_dumpregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static const struct sdhci_ops sdhci_arasan_cqe_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .set_clock = sdhci_arasan_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .get_max_clock = sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .reset = sdhci_arasan_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .set_power = sdhci_set_power_and_bus_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .irq = sdhci_arasan_cqhci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .ops = &sdhci_arasan_cqe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * sdhci_arasan_suspend - Suspend method for the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * @dev: Address of the device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Put the device in a low power state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int sdhci_arasan_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (host->tuning_mode != SDHCI_TUNING_MODE_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mmc_retune_needed(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (sdhci_arasan->has_cqe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ret = cqhci_suspend(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ret = sdhci_suspend_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ret = phy_power_off(sdhci_arasan->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_err(dev, "Cannot power off phy.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (sdhci_resume_host(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_err(dev, "Cannot resume host.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) sdhci_arasan->is_phy_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) clk_disable(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) clk_disable(sdhci_arasan->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * sdhci_arasan_resume - Resume method for the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * @dev: Address of the device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * Resume operation after suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int sdhci_arasan_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = clk_enable(sdhci_arasan->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_err(dev, "Cannot enable AHB clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = clk_enable(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev_err(dev, "Cannot enable SD clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ret = phy_power_on(sdhci_arasan->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dev_err(dev, "Cannot power on phy.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) sdhci_arasan->is_phy_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = sdhci_resume_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dev_err(dev, "Cannot resume host.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (sdhci_arasan->has_cqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return cqhci_resume(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #endif /* ! CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) sdhci_arasan_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * @hw: Pointer to the hardware clock structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * @parent_rate: The parent rate (should be rate of clk_xin).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * Return the current actual rate of the SD card clock. This can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * to communicate with out PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * Return: The card clock rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct sdhci_arasan_clk_data *clk_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct sdhci_arasan_data *sdhci_arasan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) container_of(clk_data, struct sdhci_arasan_data, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct sdhci_host *host = sdhci_arasan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return host->mmc->actual_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static const struct clk_ops arasan_sdcardclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * @hw: Pointer to the hardware clock structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * @parent_rate: The parent rate (should be rate of clk_xin).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * Return the current actual rate of the sampling clock. This can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * to communicate with out PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Return: The sample clock rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct sdhci_arasan_clk_data *clk_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct sdhci_arasan_data *sdhci_arasan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) container_of(clk_data, struct sdhci_arasan_data, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct sdhci_host *host = sdhci_arasan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return host->mmc->actual_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const struct clk_ops arasan_sampleclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * @hw: Pointer to the hardware clock structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * @degrees: The clock phase shift between 0 - 359.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * Set the SD Output Clock Tap Delays for Output path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct sdhci_arasan_clk_data *clk_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct sdhci_arasan_data *sdhci_arasan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) container_of(clk_data, struct sdhci_arasan_data, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct sdhci_host *host = sdhci_arasan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) const char *clk_name = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u8 tap_delay, tap_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* This is applicable for SDHCI_SPEC_300 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (host->version < SDHCI_SPEC_300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) switch (host->timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) case MMC_TIMING_MMC_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) case MMC_TIMING_SD_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) case MMC_TIMING_UHS_SDR25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case MMC_TIMING_UHS_DDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) case MMC_TIMING_MMC_DDR52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* For 50MHz clock, 30 Taps are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) tap_max = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case MMC_TIMING_UHS_SDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* For 100MHz clock, 15 Taps are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) tap_max = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case MMC_TIMING_UHS_SDR104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case MMC_TIMING_MMC_HS200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* For 200MHz clock, 8 Taps are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) tap_max = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) tap_delay = (degrees * tap_max) / 360;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* Set the Clock Phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) pr_err("Error setting Output Tap Delay\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Release DLL Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static const struct clk_ops zynqmp_sdcardclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .set_phase = sdhci_zynqmp_sdcardclk_set_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * @hw: Pointer to the hardware clock structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * @degrees: The clock phase shift between 0 - 359.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * Set the SD Input Clock Tap Delays for Input path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct sdhci_arasan_clk_data *clk_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct sdhci_arasan_data *sdhci_arasan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) container_of(clk_data, struct sdhci_arasan_data, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct sdhci_host *host = sdhci_arasan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) const char *clk_name = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u8 tap_delay, tap_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* This is applicable for SDHCI_SPEC_300 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (host->version < SDHCI_SPEC_300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* Assert DLL Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) switch (host->timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case MMC_TIMING_MMC_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) case MMC_TIMING_SD_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) case MMC_TIMING_UHS_SDR25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) case MMC_TIMING_UHS_DDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) case MMC_TIMING_MMC_DDR52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* For 50MHz clock, 120 Taps are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) tap_max = 120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case MMC_TIMING_UHS_SDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* For 100MHz clock, 60 Taps are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) tap_max = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) case MMC_TIMING_UHS_SDR104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) case MMC_TIMING_MMC_HS200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* For 200MHz clock, 30 Taps are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) tap_max = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) tap_delay = (degrees * tap_max) / 360;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Set the Clock Phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) pr_err("Error setting Input Tap Delay\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const struct clk_ops zynqmp_sampleclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .set_phase = sdhci_zynqmp_sampleclk_set_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * @hw: Pointer to the hardware clock structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * @degrees: The clock phase shift between 0 - 359.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * Set the SD Output Clock Tap Delays for Output path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct sdhci_arasan_clk_data *clk_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct sdhci_arasan_data *sdhci_arasan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) container_of(clk_data, struct sdhci_arasan_data, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct sdhci_host *host = sdhci_arasan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u8 tap_delay, tap_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* This is applicable for SDHCI_SPEC_300 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (host->version < SDHCI_SPEC_300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) switch (host->timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) case MMC_TIMING_MMC_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) case MMC_TIMING_SD_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) case MMC_TIMING_UHS_SDR25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) case MMC_TIMING_UHS_DDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case MMC_TIMING_MMC_DDR52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* For 50MHz clock, 30 Taps are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) tap_max = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) case MMC_TIMING_UHS_SDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* For 100MHz clock, 15 Taps are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) tap_max = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) case MMC_TIMING_UHS_SDR104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) case MMC_TIMING_MMC_HS200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* For 200MHz clock, 8 Taps are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) tap_max = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) tap_delay = (degrees * tap_max) / 360;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* Set the Clock Phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (tap_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) regval |= SDHCI_OTAPDLY_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) regval |= tap_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static const struct clk_ops versal_sdcardclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .set_phase = sdhci_versal_sdcardclk_set_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * @hw: Pointer to the hardware clock structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * @degrees: The clock phase shift between 0 - 359.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * Set the SD Input Clock Tap Delays for Input path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct sdhci_arasan_clk_data *clk_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct sdhci_arasan_data *sdhci_arasan =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) container_of(clk_data, struct sdhci_arasan_data, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct sdhci_host *host = sdhci_arasan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u8 tap_delay, tap_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* This is applicable for SDHCI_SPEC_300 and above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (host->version < SDHCI_SPEC_300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) switch (host->timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case MMC_TIMING_MMC_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) case MMC_TIMING_SD_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) case MMC_TIMING_UHS_SDR25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case MMC_TIMING_UHS_DDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) case MMC_TIMING_MMC_DDR52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* For 50MHz clock, 120 Taps are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) tap_max = 120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case MMC_TIMING_UHS_SDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* For 100MHz clock, 60 Taps are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) tap_max = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) case MMC_TIMING_UHS_SDR104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case MMC_TIMING_MMC_HS200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* For 200MHz clock, 30 Taps are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) tap_max = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) tap_delay = (degrees * tap_max) / 360;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* Set the Clock Phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (tap_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) regval |= SDHCI_ITAPDLY_CHGWIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) regval |= SDHCI_ITAPDLY_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) regval |= tap_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) regval &= ~SDHCI_ITAPDLY_CHGWIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static const struct clk_ops versal_sampleclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .set_phase = sdhci_versal_sampleclk_set_phase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u16 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* Issue DLL Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) sdhci_enable_clk(host, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) const char *clk_name = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) NODE_SD_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) arasan_zynqmp_dll_reset(host, device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) err = sdhci_execute_tuning(mmc, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) arasan_zynqmp_dll_reset(host, device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * @host: The sdhci_host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * @value: The value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * The corecfg_clockmultiplier is supposed to contain clock multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * value of programmable clock generator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * NOTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * - Many existing devices don't seem to do this and work fine. To keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * compatibility for old hardware where the device tree doesn't provide a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * register map, this function is a noop if a soc_ctl_map hasn't been provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * for this platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * - The value of corecfg_clockmultiplier should sync with that of corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * value reading from sdhci_capability_register. So this function is called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * once at probe time and never called again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) sdhci_arasan->soc_ctl_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* Having a map is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (!soc_ctl_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* If we have a map, we expect to have a syscon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (!sdhci_arasan->soc_ctl_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * @host: The sdhci_host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * function can be used to make that happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * NOTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * - Many existing devices don't seem to do this and work fine. To keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * compatibility for old hardware where the device tree doesn't provide a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * register map, this function is a noop if a soc_ctl_map hasn't been provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * for this platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * to achieve lower clock rates. That means that this function is called once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * at probe time and never called again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) sdhci_arasan->soc_ctl_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* Having a map is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (!soc_ctl_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* If we have a map, we expect to have a syscon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (!sdhci_arasan->soc_ctl_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static void sdhci_arasan_set_clk_delays(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) clk_set_phase(clk_data->sampleclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) clk_data->clk_phase_in[host->timing]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) clk_set_phase(clk_data->sdcardclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) clk_data->clk_phase_out[host->timing]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static void arasan_dt_read_clk_phase(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct sdhci_arasan_clk_data *clk_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) unsigned int timing, const char *prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) int clk_phase[2] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * Read Tap Delay values from DT, if the DT does not contain the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * Tap Values then use the pre-defined values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (of_property_read_variable_u32_array(np, prop, &clk_phase[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) 2, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) prop, clk_data->clk_phase_in[timing],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) clk_data->clk_phase_out[timing]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* The values read are Input and Output Clock Delays in order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) clk_data->clk_phase_in[timing] = clk_phase[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) clk_data->clk_phase_out[timing] = clk_phase[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * @dev: Pointer to our struct device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * @clk_data: Pointer to the Clock Data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * Called at initialization to parse the values of Clock Delays.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static void arasan_dt_parse_clk_phases(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct sdhci_arasan_clk_data *clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) u32 mio_bank = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * This has been kept as a pointer and is assigned a function here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * So that different controller variants can assign their own handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ZYNQMP_ICLK_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ZYNQMP_OCLK_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (mio_bank == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) VERSAL_ICLK_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) VERSAL_OCLK_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) clk_data->clk_phase_in[i] = versal_iclk_phase[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) clk_data->clk_phase_out[i] = versal_oclk_phase[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) "clk-phase-legacy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) "clk-phase-mmc-hs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) "clk-phase-sd-hs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) "clk-phase-uhs-sdr12");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) "clk-phase-uhs-sdr25");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) "clk-phase-uhs-sdr50");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "clk-phase-uhs-sdr104");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) "clk-phase-uhs-ddr50");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) "clk-phase-mmc-ddr52");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) "clk-phase-mmc-hs200");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) "clk-phase-mmc-hs400");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .ops = &sdhci_arasan_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) SDHCI_QUIRK2_STOP_WITH_TC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static const struct sdhci_arasan_clk_ops arasan_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .sdcardclk_ops = &arasan_sdcardclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .sampleclk_ops = &arasan_sampleclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .pdata = &sdhci_arasan_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .clk_ops = &arasan_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .ops = &sdhci_arasan_cqe_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) SDHCI_QUIRK_NO_LED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) SDHCI_QUIRK_32BIT_DMA_ADDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) SDHCI_QUIRK_32BIT_DMA_SIZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) SDHCI_QUIRK_32BIT_ADMA_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) SDHCI_QUIRK2_STOP_WITH_TC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .ops = &sdhci_arasan_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) SDHCI_QUIRK_NO_LED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) SDHCI_QUIRK_32BIT_DMA_ADDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) SDHCI_QUIRK_32BIT_DMA_SIZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) SDHCI_QUIRK_32BIT_ADMA_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) SDHCI_QUIRK2_STOP_WITH_TC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .ops = &sdhci_arasan_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) SDHCI_QUIRK_NO_LED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) SDHCI_QUIRK_32BIT_DMA_ADDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) SDHCI_QUIRK_32BIT_DMA_SIZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) SDHCI_QUIRK_32BIT_ADMA_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) SDHCI_QUIRK2_HOST_OFF_CARD_ON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .soc_ctl_map = &rk3399_soc_ctl_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .pdata = &sdhci_arasan_cqe_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .clk_ops = &arasan_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .pdata = &sdhci_arasan_cqe_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .clk_ops = &arasan_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .pdata = &sdhci_arasan_cqe_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .clk_ops = &arasan_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .ops = &sdhci_arasan_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) SDHCI_QUIRK2_STOP_WITH_TC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .sdcardclk_ops = &zynqmp_sdcardclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .sampleclk_ops = &zynqmp_sampleclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .pdata = &sdhci_arasan_zynqmp_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .clk_ops = &zynqmp_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static const struct sdhci_arasan_clk_ops versal_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .sdcardclk_ops = &versal_sdcardclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .sampleclk_ops = &versal_sampleclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .pdata = &sdhci_arasan_zynqmp_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .clk_ops = &versal_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .soc_ctl_map = &intel_keembay_soc_ctl_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .pdata = &sdhci_keembay_emmc_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .clk_ops = &arasan_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static struct sdhci_arasan_of_data intel_keembay_sd_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .soc_ctl_map = &intel_keembay_soc_ctl_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .pdata = &sdhci_keembay_sd_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .clk_ops = &arasan_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .soc_ctl_map = &intel_keembay_soc_ctl_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .pdata = &sdhci_keembay_sdio_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .clk_ops = &arasan_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static const struct of_device_id sdhci_arasan_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /* SoC-specific compatible strings w/ soc_ctl_map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .compatible = "rockchip,rk3399-sdhci-5.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .data = &sdhci_arasan_rk3399_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .compatible = "intel,lgm-sdhci-5.1-emmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .data = &intel_lgm_emmc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .compatible = "intel,lgm-sdhci-5.1-sdxc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .data = &intel_lgm_sdxc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .compatible = "intel,keembay-sdhci-5.1-emmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .data = &intel_keembay_emmc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .compatible = "intel,keembay-sdhci-5.1-sd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .data = &intel_keembay_sd_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .compatible = "intel,keembay-sdhci-5.1-sdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .data = &intel_keembay_sdio_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* Generic compatible below here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .compatible = "arasan,sdhci-8.9a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .data = &sdhci_arasan_generic_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .compatible = "arasan,sdhci-5.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .data = &sdhci_arasan_generic_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .compatible = "arasan,sdhci-4.9a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .data = &sdhci_arasan_generic_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .compatible = "xlnx,zynqmp-8.9a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .data = &sdhci_arasan_zynqmp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .compatible = "xlnx,versal-8.9a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .data = &sdhci_arasan_versal_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * @sdhci_arasan: Our private data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * @clk_xin: Pointer to the functional clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * @dev: Pointer to our struct device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * Some PHY devices need to know what the actual card clock is. In order for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * them to find out, we'll provide a clock through the common clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * for them to query.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) struct clk *clk_xin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct clk_init_data sdcardclk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) const char *parent_clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) ret = of_property_read_string_index(np, "clock-output-names", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) &sdcardclk_init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) parent_clk_name = __clk_get_name(clk_xin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) sdcardclk_init.parent_names = &parent_clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) sdcardclk_init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) clk_data->sdcardclk_hw.init = &sdcardclk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) clk_data->sdcardclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) devm_clk_register(dev, &clk_data->sdcardclk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (IS_ERR(clk_data->sdcardclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return PTR_ERR(clk_data->sdcardclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) clk_data->sdcardclk_hw.init = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ret = of_clk_add_provider(np, of_clk_src_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) clk_data->sdcardclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) dev_err(dev, "Failed to add sdcard clock provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * @sdhci_arasan: Our private data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * @clk_xin: Pointer to the functional clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * @dev: Pointer to our struct device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * Some PHY devices need to know what the actual card clock is. In order for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * them to find out, we'll provide a clock through the common clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * for them to query.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct clk *clk_xin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct clk_init_data sampleclk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) const char *parent_clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret = of_property_read_string_index(np, "clock-output-names", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) &sampleclk_init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) parent_clk_name = __clk_get_name(clk_xin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) sampleclk_init.parent_names = &parent_clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) sampleclk_init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) clk_data->sampleclk_hw.init = &sampleclk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) clk_data->sampleclk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) devm_clk_register(dev, &clk_data->sampleclk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (IS_ERR(clk_data->sampleclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return PTR_ERR(clk_data->sampleclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) clk_data->sampleclk_hw.init = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ret = of_clk_add_provider(np, of_clk_src_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) clk_data->sampleclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) dev_err(dev, "Failed to add sample clock provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * @dev: Pointer to our struct device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * returned success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static void sdhci_arasan_unregister_sdclk(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (!of_find_property(np, "#clock-cells", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) of_clk_del_provider(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) * This should be set based on the System Address Bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) * 0: the Core supports only 32-bit System Address Bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * 1: the Core supports 64-bit System Address Bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * NOTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) * - For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * Keem Bay does not support 64-bit access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * @host: The sdhci_host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * @value: The value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) sdhci_arasan->soc_ctl_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* Having a map is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (!soc_ctl_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* If we have a map, we expect to have a syscon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (!sdhci_arasan->soc_ctl_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * @sdhci_arasan: Our private data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) * @clk_xin: Pointer to the functional clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) * @dev: Pointer to our struct device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) * Some PHY devices need to know what the actual card clock is. In order for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * them to find out, we'll provide a clock through the common clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * for them to query.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * Note: without seriously re-architecting SDHCI's clock code and testing on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * all platforms, there's no way to create a totally beautiful clock here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * with all clock ops implemented. Instead, we'll just create a clock that can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * framework that we're doing things behind its back. This should be sufficient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * to create nice clean device tree bindings and later (if needed) we can try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * re-architecting SDHCI if we see some benefit to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * Return: 0 on success and error value on error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) struct clk *clk_xin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) u32 num_clks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /* Providing a clock to the PHY is optional; no error if missing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (num_clks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) sdhci_arasan_unregister_sdclk(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) struct sdhci_host *host = sdhci_arasan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) struct cqhci_host *cq_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) bool dma64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (!sdhci_arasan->has_cqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) ret = sdhci_setup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) cq_host = devm_kzalloc(host->mmc->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) sizeof(*cq_host), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (!cq_host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) cq_host->ops = &sdhci_arasan_cqhci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (dma64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) ret = cqhci_init(cq_host, host->mmc, dma64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) ret = __sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) sdhci_cleanup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static int sdhci_arasan_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) struct clk *clk_xin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) struct sdhci_arasan_data *sdhci_arasan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) const struct sdhci_arasan_of_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) sdhci_arasan->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) sdhci_arasan->soc_ctl_map = data->soc_ctl_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) sdhci_arasan->clk_ops = data->clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ret = dev_err_probe(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) PTR_ERR(sdhci_arasan->soc_ctl_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) "Can't get syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) goto err_pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) if (IS_ERR(sdhci_arasan->clk_ahb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) dev_err(&pdev->dev, "clk_ahb clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) ret = PTR_ERR(sdhci_arasan->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) goto err_pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) if (IS_ERR(clk_xin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) dev_err(&pdev->dev, "clk_xin clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) ret = PTR_ERR(clk_xin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) goto err_pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) goto err_pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) ret = clk_prepare_enable(clk_xin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) dev_err(&pdev->dev, "Unable to enable SD clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) goto clk_dis_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) sdhci_get_of_property(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) pltfm_host->clk = clk_xin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (of_device_is_compatible(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) "rockchip,rk3399-sdhci-5.1"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) sdhci_arasan_update_clockmultiplier(host, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) sdhci_arasan_update_clockmultiplier(host, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) sdhci_arasan_update_support64b(host, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) sdhci_arasan_update_baseclkfreq(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) goto clk_disable_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) host->mmc_host_ops.execute_tuning =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) arasan_zynqmp_execute_tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) ret = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) goto unreg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) sdhci_arasan->phy = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) if (of_device_is_compatible(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) "arasan,sdhci-5.1")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) sdhci_arasan->phy = devm_phy_get(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) "phy_arasan");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (IS_ERR(sdhci_arasan->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ret = PTR_ERR(sdhci_arasan->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) goto unreg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) ret = phy_init(sdhci_arasan->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) dev_err(&pdev->dev, "phy_init err.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) goto unreg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) host->mmc_host_ops.hs400_enhanced_strobe =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) sdhci_arasan_hs400_enhanced_strobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) host->mmc_host_ops.start_signal_voltage_switch =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) sdhci_arasan_voltage_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (!of_property_read_bool(np, "disable-cqe")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) sdhci_arasan->has_cqe = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) host->mmc->caps2 |= MMC_CAP2_CQE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (!of_property_read_bool(np, "disable-cqe-dcmd"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) ret = sdhci_arasan_add_host(sdhci_arasan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) goto err_add_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) err_add_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (!IS_ERR(sdhci_arasan->phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) phy_exit(sdhci_arasan->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) unreg_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) sdhci_arasan_unregister_sdclk(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) clk_disable_all:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) clk_disable_unprepare(clk_xin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) clk_dis_ahb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) clk_disable_unprepare(sdhci_arasan->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) err_pltfm_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) static int sdhci_arasan_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) struct sdhci_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) struct clk *clk_ahb = sdhci_arasan->clk_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (!IS_ERR(sdhci_arasan->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (sdhci_arasan->is_phy_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) phy_power_off(sdhci_arasan->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) phy_exit(sdhci_arasan->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) sdhci_arasan_unregister_sdclk(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) ret = sdhci_pltfm_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) clk_disable_unprepare(clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) static struct platform_driver sdhci_arasan_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .name = "sdhci-arasan",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .of_match_table = sdhci_arasan_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .pm = &sdhci_arasan_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .probe = sdhci_arasan_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .remove = sdhci_arasan_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) module_platform_driver(sdhci_arasan_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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