^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/qcom_scm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interconnect.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "cqhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CORE_MCI_VERSION 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CORE_VERSION_MAJOR_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CORE_VERSION_MINOR_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CORE_MCI_GENERICS 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HC_MODE_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CORE_POWER 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CORE_SW_RST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FF_CLK_SW_RST_DIS BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CORE_PWRCTL_BUS_OFF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CORE_PWRCTL_BUS_ON BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CORE_PWRCTL_IO_LOW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CORE_PWRCTL_IO_HIGH BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CORE_PWRCTL_BUS_FAIL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CORE_PWRCTL_IO_SUCCESS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CORE_PWRCTL_IO_FAIL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REQ_BUS_OFF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REQ_BUS_ON BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REQ_IO_LOW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REQ_IO_HIGH BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define INT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MAX_PHASES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CORE_DLL_LOCK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CORE_DDR_DLL_LOCK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CORE_DLL_EN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CORE_CDR_EN BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CORE_CK_OUT_EN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CORE_CDR_EXT_EN BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CORE_DLL_PDN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CORE_DLL_RST BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CORE_CMD_DAT_TRACK_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CORE_DDR_CAL_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CORE_FLL_CYCLE_CNT BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CORE_DLL_CLOCK_DISABLE BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DLL_USR_CTL_POR_VAL 0x10800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ENABLE_DLL_LOCK_STATUS BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FINE_TUNE_MODE_EN BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BIAS_OK_SIGNAL BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DLL_CONFIG_3_LOW_FREQ_VAL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DLL_CONFIG_3_HIGH_FREQ_VAL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CORE_VENDOR_SPEC_POR_VAL 0xa9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CORE_CLK_PWRSAVE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CORE_HC_MCLK_SEL_MASK (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CORE_IO_PAD_PWR_SWITCH_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CORE_IO_PAD_PWR_SWITCH BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CORE_HC_SELECT_IN_EN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CORE_HC_SELECT_IN_HS400 (6 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CORE_HC_SELECT_IN_MASK (7 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CORE_3_0V_SUPPORT BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CORE_1_8V_SUPPORT BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CORE_CSR_CDC_CTLR_CFG0 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CORE_SW_TRIG_FULL_CALIB BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CORE_HW_AUTOCAL_ENA BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CORE_CSR_CDC_CTLR_CFG1 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CORE_TIMER_ENA BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CORE_CDC_OFFSET_CFG 0x14C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CORE_CSR_CDC_DELAY_CFG 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CORE_CDC_SLAVE_DDA_CFG 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CORE_CSR_CDC_STATUS0 0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CORE_CALIBRATION_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CORE_CDC_ERROR_CODE_MASK 0x7000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CORE_CSR_CDC_GEN_CFG 0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CORE_CDC_SWITCH_RC_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CORE_CDC_T4_DLY_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CORE_CMDIN_RCLK_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CORE_START_CDC_TRAFFIC BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CORE_PWRSAVE_DLL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DDR_CONFIG_POR_VAL 0x80040873
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define INVALID_TUNING_PHASE -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SDHCI_MSM_MIN_CLOCK 400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CDR_SELEXT_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CMUX_SHIFT_PHASE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Timeout value to avoid infinite waiting for pwr_irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MSM_PWR_IRQ_TIMEOUT_MS 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Max load for eMMC Vdd-io supply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MMC_VQMMC_MAX_LOAD_UA 325000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define msm_host_readl(msm_host, host, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) msm_host->var_ops->msm_readl_relaxed(host, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define msm_host_writel(msm_host, val, host, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) msm_host->var_ops->msm_writel_relaxed(val, host, offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* CQHCI vendor specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CQHCI_VENDOR_CFG1 0xA00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct sdhci_msm_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 core_hc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 core_mci_data_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 core_mci_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 core_mci_fifo_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 core_mci_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 core_generics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 core_testbus_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 core_testbus_sel2_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 core_testbus_ena;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 core_testbus_sel2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 core_pwrctl_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 core_pwrctl_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 core_pwrctl_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 core_pwrctl_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 core_sdcc_debug_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 core_dll_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 core_dll_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 core_vendor_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 core_vendor_spec_adma_err_addr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 core_vendor_spec_adma_err_addr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 core_vendor_spec_func2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 core_vendor_spec_capabilities0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 core_ddr_200_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 core_vendor_spec3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 core_dll_config_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 core_dll_config_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 core_ddr_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 core_dll_usr_ctl; /* Present on SDCC5.1 onwards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .core_mci_data_cnt = 0x35c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .core_mci_status = 0x324,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .core_mci_fifo_cnt = 0x308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .core_mci_version = 0x318,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .core_generics = 0x320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .core_testbus_config = 0x32c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .core_testbus_sel2_bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .core_testbus_ena = (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .core_testbus_sel2 = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .core_pwrctl_status = 0x240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .core_pwrctl_mask = 0x244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .core_pwrctl_clear = 0x248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .core_pwrctl_ctl = 0x24c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .core_sdcc_debug_reg = 0x358,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .core_dll_config = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .core_dll_status = 0x208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .core_vendor_spec = 0x20c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .core_vendor_spec_adma_err_addr0 = 0x214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .core_vendor_spec_adma_err_addr1 = 0x218,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .core_vendor_spec_func2 = 0x210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .core_vendor_spec_capabilities0 = 0x21c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .core_ddr_200_cfg = 0x224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .core_vendor_spec3 = 0x250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .core_dll_config_2 = 0x254,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .core_dll_config_3 = 0x258,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .core_ddr_config = 0x25c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .core_dll_usr_ctl = 0x388,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .core_hc_mode = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .core_mci_data_cnt = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .core_mci_status = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .core_mci_fifo_cnt = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .core_mci_version = 0x050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .core_generics = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .core_testbus_config = 0x0cc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .core_testbus_sel2_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .core_testbus_ena = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .core_testbus_sel2 = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .core_pwrctl_status = 0xdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .core_pwrctl_mask = 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .core_pwrctl_clear = 0xe4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .core_pwrctl_ctl = 0xe8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .core_sdcc_debug_reg = 0x124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .core_dll_config = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .core_dll_status = 0x108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .core_vendor_spec = 0x10c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .core_vendor_spec_adma_err_addr0 = 0x114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .core_vendor_spec_adma_err_addr1 = 0x118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .core_vendor_spec_func2 = 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .core_vendor_spec_capabilities0 = 0x11c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .core_ddr_200_cfg = 0x184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .core_vendor_spec3 = 0x1b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .core_dll_config_2 = 0x1b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .core_ddr_config_old = 0x1b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .core_ddr_config = 0x1bc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct sdhci_msm_variant_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * From V5, register spaces have changed. Wrap this info in a structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * and choose the data_structure based on version info mentioned in DT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct sdhci_msm_variant_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) bool mci_removed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) bool restore_dll_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bool uses_tassadar_dll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) const struct sdhci_msm_variant_ops *var_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) const struct sdhci_msm_offset *offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct sdhci_msm_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) void __iomem *core_mem; /* MSM SDCC mapped address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) void __iomem *ice_mem; /* MSM ICE mapped address (if available) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int pwr_irq; /* power irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct clk *bus_clk; /* SDHC bus voter clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* core, iface, cal, sleep, and ice clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct clk_bulk_data bulk_clks[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct opp_table *opp_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) bool use_14lpp_dll_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) bool tuning_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) bool calibration_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u8 saved_tuning_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) bool use_cdclp533;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 curr_pwr_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 curr_io_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) wait_queue_head_t pwr_irq_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) bool pwr_irq_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 caps_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) bool mci_removed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) bool restore_dll_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) const struct sdhci_msm_variant_ops *var_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) const struct sdhci_msm_offset *offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) bool use_cdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 transfer_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) bool updated_ddr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) bool uses_tassadar_dll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 dll_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 ddr_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) bool vqmmc_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return msm_host->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * APIs to read/write to vendor specific registers which were there in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * core_mem region before MCI was removed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return readl_relaxed(msm_host->core_mem + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return readl_relaxed(host->ioaddr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct sdhci_host *host, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) writel_relaxed(val, msm_host->core_mem + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct sdhci_host *host, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) writel_relaxed(val, host->ioaddr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct mmc_ios ios = host->mmc->ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * The SDHC requires internal clock frequency to be double the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * actual clock that will be set for DDR mode. The controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * uses the faster clock(100/400MHz) for some of its parts and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * send the actual required clock (50/200MHz) to the card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ios.timing == MMC_TIMING_UHS_DDR50 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ios.timing == MMC_TIMING_MMC_DDR52 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ios.timing == MMC_TIMING_MMC_HS400 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) host->flags & SDHCI_HS400_TUNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) clock *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct mmc_ios curr_ios = host->mmc->ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct clk *core_clk = msm_host->bulk_clks[0].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) clock = msm_get_clock_rate_for_bus_mode(host, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pr_err("%s: Failed to set clock at rate %u at timing %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) mmc_hostname(host->mmc), clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) curr_ios.timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) msm_host->clk_rate = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pr_debug("%s: Setting clock at rate %lu at timing %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mmc_hostname(host->mmc), clk_get_rate(core_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) curr_ios.timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Platform specific tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 wait_cnt = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u8 ck_out_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) const struct sdhci_msm_offset *msm_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) sdhci_priv_msm_offset(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Poll for CK_OUT_EN bit. max. poll time = 50us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ck_out_en = !!(readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) msm_offset->core_dll_config) & CORE_CK_OUT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) while (ck_out_en != poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (--wait_cnt == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mmc_hostname(mmc), poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ck_out_en = !!(readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) msm_offset->core_dll_config) & CORE_CK_OUT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const u8 grey_coded_phase_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) const struct sdhci_msm_offset *msm_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) sdhci_priv_msm_offset(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (phase > 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) rc = msm_dll_poll_ck_out_en(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Write the selected DLL clock output phase (0 ... 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * to CDR_SELEXT bit field of DLL_CONFIG register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) config &= ~CDR_SELEXT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) config |= CORE_CK_OUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) rc = msm_dll_poll_ck_out_en(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) config |= CORE_CDR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) config &= ~CORE_CDR_EXT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) mmc_hostname(mmc), phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Find out the greatest range of consecuitive selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * DLL clock output phases that can be used as sampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * setting for SD3.0 UHS-I card read operation (in SDR104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * timing mode) or for eMMC4.5 card read operation (in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * HS400/HS200 timing mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * Select the 3/4 of the range and configure the DLL with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * selected DLL clock output phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int msm_find_most_appropriate_phase(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u8 *phase_table, u8 total_phases)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u8 phases_per_row[MAX_PHASES] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) bool phase_0_found = false, phase_15_found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (!total_phases || (total_phases > MAX_PHASES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mmc_hostname(mmc), total_phases);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) for (cnt = 0; cnt < total_phases; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ranges[row_index][col_index] = phase_table[cnt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) phases_per_row[row_index] += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) col_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if ((cnt + 1) == total_phases) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* check if next phase in phase_table is consecutive or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) row_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) col_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (row_index >= MAX_PHASES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Check if phase-0 is present in first valid window? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!ranges[0][0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) phase_0_found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) phase_0_raw_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Check if cycle exist between 2 valid windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) for (cnt = 1; cnt <= row_index; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (phases_per_row[cnt]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) for (i = 0; i < phases_per_row[cnt]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (ranges[cnt][i] == 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) phase_15_found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) phase_15_raw_index = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* If 2 valid windows form cycle then merge them as single window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (phase_0_found && phase_15_found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* number of phases in raw where phase 0 is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 phases_0 = phases_per_row[phase_0_raw_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* number of phases in raw where phase 15 is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u8 phases_15 = phases_per_row[phase_15_raw_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (phases_0 + phases_15 >= MAX_PHASES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * If there are more than 1 phase windows then total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * number of phases in both the windows should not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * more than or equal to MAX_PHASES.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Merge 2 cyclic windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) i = phases_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) for (cnt = 0; cnt < phases_0; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ranges[phase_15_raw_index][i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ranges[phase_0_raw_index][cnt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (++i >= MAX_PHASES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) phases_per_row[phase_0_raw_index] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) for (cnt = 0; cnt <= row_index; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (phases_per_row[cnt] > curr_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) curr_max = phases_per_row[cnt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) selected_row_index = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) i = (curr_max * 3) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) i--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = ranges[selected_row_index][i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (ret >= MAX_PHASES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mmc_hostname(mmc), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u32 mclk_freq = 0, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) const struct sdhci_msm_offset *msm_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) sdhci_priv_msm_offset(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Program the MCLK value to MCLK_FREQ bit field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (host->clock <= 112000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) mclk_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) else if (host->clock <= 125000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) mclk_freq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) else if (host->clock <= 137000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) mclk_freq = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) else if (host->clock <= 150000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mclk_freq = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) else if (host->clock <= 162000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mclk_freq = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) else if (host->clock <= 175000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) mclk_freq = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) else if (host->clock <= 187000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mclk_freq = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) else if (host->clock <= 200000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mclk_freq = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) config &= ~CMUX_SHIFT_PHASE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Initialize the DLL (Programmable Delay Line) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int msm_init_cm_dll(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int wait_cnt = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned long flags, xo_clk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) const struct sdhci_msm_offset *msm_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) msm_host->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) xo_clk = clk_get_rate(msm_host->xo_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * Make sure that clock is always enabled when DLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * tuning is in progress. Keeping PWRSAVE ON may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * turn off the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) config &= ~CORE_CLK_PWRSAVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (msm_host->dll_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) writel_relaxed(msm_host->dll_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) host->ioaddr + msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (msm_host->use_14lpp_dll_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) config &= ~CORE_CK_OUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) msm_offset->core_dll_config_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) config |= CORE_DLL_CLOCK_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) msm_offset->core_dll_config_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) config |= CORE_DLL_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) config |= CORE_DLL_PDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!msm_host->dll_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) msm_cm_dll_set_freq(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (msm_host->use_14lpp_dll_reset &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) !IS_ERR_OR_NULL(msm_host->xo_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u32 mclk_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) msm_offset->core_dll_config_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) config &= CORE_FLL_CYCLE_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) xo_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) xo_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) msm_offset->core_dll_config_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) config &= ~(0xFF << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) config |= mclk_freq << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) msm_offset->core_dll_config_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* wait for 5us before enabling DLL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) config &= ~CORE_DLL_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) config &= ~CORE_DLL_PDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (msm_host->use_14lpp_dll_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (!msm_host->dll_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) msm_cm_dll_set_freq(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) msm_offset->core_dll_config_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) config &= ~CORE_DLL_CLOCK_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) msm_offset->core_dll_config_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * Configure DLL user control register to enable DLL status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * This setting is applicable to SDCC v5.1 onwards only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (msm_host->uses_tassadar_dll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) config = DLL_USR_CTL_POR_VAL | FINE_TUNE_MODE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) msm_offset->core_dll_usr_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) msm_offset->core_dll_config_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) config &= ~0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (msm_host->clk_rate < 150000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) config |= DLL_CONFIG_3_LOW_FREQ_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) config |= DLL_CONFIG_3_HIGH_FREQ_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) msm_offset->core_dll_config_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) config |= CORE_DLL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) config |= CORE_CK_OUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) CORE_DLL_LOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* max. wait for 50us sec for LOCK bit to be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (--wait_cnt == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mmc_hostname(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static void msm_hc_select_default(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) const struct sdhci_msm_offset *msm_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) msm_host->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (!msm_host->use_cdclp533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) msm_offset->core_vendor_spec3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) config &= ~CORE_PWRSAVE_DLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) msm_offset->core_vendor_spec3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) config &= ~CORE_HC_MCLK_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) config |= CORE_HC_MCLK_SEL_DFLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * Disable HC_SELECT_IN to be able to use the UHS mode select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * configuration from Host Control2 register for all other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * in VENDOR_SPEC_FUNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) config &= ~CORE_HC_SELECT_IN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) config &= ~CORE_HC_SELECT_IN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * Make sure above writes impacting free running MCLK are completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * before changing the clk_rate at GCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static void msm_hc_select_hs400(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct mmc_ios ios = host->mmc->ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u32 config, dll_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) const struct sdhci_msm_offset *msm_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) msm_host->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* Select the divided clock (free running MCLK/2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) config &= ~CORE_HC_MCLK_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) config |= CORE_HC_MCLK_SEL_HS400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if ((msm_host->tuning_done || ios.enhanced_strobe) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) !msm_host->calibration_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) config |= CORE_HC_SELECT_IN_HS400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) config |= CORE_HC_SELECT_IN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * core_dll_status to be set. This should get set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * within 15 us at 200 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) rc = readl_relaxed_poll_timeout(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) msm_offset->core_dll_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dll_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) (dll_lock &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) (CORE_DLL_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) CORE_DDR_DLL_LOCK)), 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (rc == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) mmc_hostname(host->mmc), dll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * Make sure above writes impacting free running MCLK are completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * before changing the clk_rate at GCC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * sdhci_msm_hc_select_mode :- In general all timing modes are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * controlled via UHS mode select in Host Control2 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * eMMC specific HS200/HS400 doesn't have their respective modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * defined here, hence we use these values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * HS200 - SDR104 (Since they both are equivalent in functionality)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * HS400 - This involves multiple configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * Initially SDR104 - when tuning is required as HS200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * Then when switching to DDR @ 400MHz (HS400) we use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * the vendor specific HC_SELECT_IN to control the mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * In addition to controlling the modes we also need to select the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * correct input clock for DLL depending on the mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * HS400 - divided clock (free running MCLK/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * All other modes - default (free running MCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct mmc_ios ios = host->mmc->ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (ios.timing == MMC_TIMING_MMC_HS400 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) host->flags & SDHCI_HS400_TUNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) msm_hc_select_hs400(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) msm_hc_select_default(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u32 config, calib_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) const struct sdhci_msm_offset *msm_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) msm_host->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * Retuning in HS400 (DDR mode) will fail, just reset the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * tuning block and restore the saved tuning phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ret = msm_init_cm_dll(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* Set the selected phase in delay line hw block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) config |= CORE_CMD_DAT_TRACK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) config &= ~CORE_CDC_T4_DLY_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) config |= CORE_CDC_SWITCH_RC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) config &= ~CORE_START_CDC_TRAFFIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* Perform CDC Register Initialization Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* CDC HW Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) config |= CORE_SW_TRIG_FULL_CALIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) config &= ~CORE_SW_TRIG_FULL_CALIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) config |= CORE_HW_AUTOCAL_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) config |= CORE_TIMER_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) calib_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) (calib_done & CORE_CALIBRATION_DONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) 1, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (ret == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) pr_err("%s: %s: CDC calibration was not completed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) mmc_hostname(host->mmc), __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) & CORE_CDC_ERROR_CODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) pr_err("%s: %s: CDC error code %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) mmc_hostname(host->mmc), __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) config |= CORE_START_CDC_TRAFFIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u32 dll_status, config, ddr_cfg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) const struct sdhci_msm_offset *msm_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) sdhci_priv_msm_offset(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * Currently the core_ddr_config register defaults to desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * configuration on reset. Currently reprogramming the power on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * reset (POR) value in case it might have been modified by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * bootloaders. In the future, if this changes, then the desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * values will need to be programmed appropriately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (msm_host->updated_ddr_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ddr_cfg_offset = msm_offset->core_ddr_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ddr_cfg_offset = msm_offset->core_ddr_config_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (mmc->ios.enhanced_strobe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) msm_offset->core_ddr_200_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) config |= CORE_CMDIN_RCLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) msm_offset->core_ddr_200_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) config |= CORE_DDR_CAL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ret = readl_relaxed_poll_timeout(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) msm_offset->core_dll_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dll_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) (dll_status & CORE_DDR_DLL_LOCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) 10, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (ret == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) mmc_hostname(host->mmc), __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * When MCLK is gated OFF, it is not gated for less than 0.5us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * and MCLK must be switched on for at-least 1us before DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * starts coming. Controllers with 14lpp and later tech DLL cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * guarantee above requirement. So PWRSAVE_DLL should not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * turned on for host controllers using this DLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (!msm_host->use_14lpp_dll_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) msm_offset->core_vendor_spec3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) config |= CORE_PWRSAVE_DLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) msm_offset->core_vendor_spec3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * Drain writebuffer to ensure above DLL calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * and PWRSAVE DLL is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) const struct sdhci_msm_offset *msm_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) msm_host->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * Retuning in HS400 (DDR mode) will fail, just reset the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * tuning block and restore the saved tuning phase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) ret = msm_init_cm_dll(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (!mmc->ios.enhanced_strobe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /* Set the selected phase in delay line hw block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ret = msm_config_cm_dll_phase(host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) msm_host->saved_tuning_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) config |= CORE_CMD_DAT_TRACK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (msm_host->use_cdclp533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ret = sdhci_msm_cdclp533_calibration(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ret = sdhci_msm_cm_dll_sdc4_calibration(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct mmc_ios *ios = &host->mmc->ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * Tuning is required for SDR104, HS200 and HS400 cards and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * if clock frequency is greater than 100MHz in these modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (host->clock <= CORE_FREQ_100MHZ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) !(ios->timing == MMC_TIMING_MMC_HS400 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ios->timing == MMC_TIMING_MMC_HS200 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ios->timing == MMC_TIMING_UHS_SDR104) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ios->enhanced_strobe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * SDR DLL comes into picture only for timing modes which needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * tuning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (!sdhci_msm_is_tuning_needed(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* Reset the tuning block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ret = msm_init_cm_dll(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Restore the tuning block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) u32 config, oldconfig = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) config = oldconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) config |= CORE_CDR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) config &= ~CORE_CDR_EXT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) config &= ~CORE_CDR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) config |= CORE_CDR_EXT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (config != oldconfig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) int tuning_seq_cnt = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct mmc_ios ios = host->mmc->ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (!sdhci_msm_is_tuning_needed(host)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) msm_host->use_cdr = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) sdhci_msm_set_cdr(host, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) msm_host->use_cdr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * Clear tuning_done flag before tuning to ensure proper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * HS400 settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) msm_host->tuning_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * For HS400 tuning in HS200 timing requires:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * - select MCLK/2 in VENDOR_SPEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * - program MCLK to 400MHz (or nearest supported) in GCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (host->flags & SDHCI_HS400_TUNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) sdhci_msm_hc_select_mode(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) msm_set_clock_rate_for_bus_mode(host, ios.clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) host->flags &= ~SDHCI_HS400_TUNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* First of all reset the tuning block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) rc = msm_init_cm_dll(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) phase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /* Set the phase in delay line hw block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) rc = msm_config_cm_dll_phase(host, phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) rc = mmc_send_tuning(mmc, opcode, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* Tuning is successful at this tuning point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) tuned_phases[tuned_phase_cnt++] = phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) mmc_hostname(mmc), phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) } while (++phase < ARRAY_SIZE(tuned_phases));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (tuned_phase_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (tuned_phase_cnt == ARRAY_SIZE(tuned_phases)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * All phases valid is _almost_ as bad as no phases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * valid. Probably all phases are not really reliable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * but we didn't detect where the unreliable place is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * That means we'll essentially be guessing and hoping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * we get a good phase. Better to try a few times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) dev_dbg(mmc_dev(mmc), "%s: All phases valid; try again\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) mmc_hostname(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (--tuning_seq_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) tuned_phase_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) rc = msm_find_most_appropriate_phase(host, tuned_phases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) tuned_phase_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) phase = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * Finally set the selected phase in delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * line hw block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) rc = msm_config_cm_dll_phase(host, phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) msm_host->saved_tuning_phase = phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) mmc_hostname(mmc), phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (--tuning_seq_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* Tuning failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) mmc_hostname(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) msm_host->tuning_done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * This needs to be done for both tuning and enhanced_strobe mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) * fixed feedback clock is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (host->clock > CORE_FREQ_100MHZ &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) (msm_host->tuning_done || ios->enhanced_strobe) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) !msm_host->calibration_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ret = sdhci_msm_hs400_dll_calibration(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) msm_host->calibration_done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) mmc_hostname(host->mmc), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) unsigned int uhs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) u16 ctrl_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) const struct sdhci_msm_offset *msm_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) msm_host->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* Select Bus Speed Mode for host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) switch (uhs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) case MMC_TIMING_UHS_SDR12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) case MMC_TIMING_UHS_SDR25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) case MMC_TIMING_UHS_SDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) case MMC_TIMING_MMC_HS400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) case MMC_TIMING_MMC_HS200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) case MMC_TIMING_UHS_SDR104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) case MMC_TIMING_UHS_DDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) case MMC_TIMING_MMC_DDR52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * When clock frequency is less than 100MHz, the feedback clock must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * provided and DLL must not be used so that tuning can be skipped. To
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * provide feedback clock, the mode selection can be any value less
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (host->clock <= CORE_FREQ_100MHZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (uhs == MMC_TIMING_MMC_HS400 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) uhs == MMC_TIMING_MMC_HS200 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) uhs == MMC_TIMING_UHS_SDR104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * DLL is not required for clock <= 100MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * Thus, make sure DLL it is disabled when not required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) config |= CORE_DLL_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) config |= CORE_DLL_PDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) msm_offset->core_dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * The DLL needs to be restored and CDCLP533 recalibrated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * when the clock frequency is set back to 400MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) msm_host->calibration_done = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) sdhci_msm_hs400(host, &mmc->ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct platform_device *pdev = msm_host->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) ret = pinctrl_pm_select_default_state(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) ret = pinctrl_pm_select_sleep_state(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static int sdhci_msm_set_vmmc(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (IS_ERR(mmc->supply.vmmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct mmc_host *mmc, bool level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) struct mmc_ios ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (msm_host->vqmmc_enabled == level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /* Set the IO voltage regulator to default voltage level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (msm_host->caps_0 & CORE_3_0V_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ios.signal_voltage = MMC_SIGNAL_VOLTAGE_330;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) else if (msm_host->caps_0 & CORE_1_8V_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ios.signal_voltage = MMC_SIGNAL_VOLTAGE_180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) ret = mmc_regulator_set_vqmmc(mmc, &ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) dev_err(mmc_dev(mmc), "%s: vqmmc set volgate failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) mmc_hostname(mmc), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ret = regulator_enable(mmc->supply.vqmmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ret = regulator_disable(mmc->supply.vqmmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) dev_err(mmc_dev(mmc), "%s: vqmm %sable failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) mmc_hostname(mmc), level ? "en":"dis", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) msm_host->vqmmc_enabled = level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) struct mmc_host *mmc, bool hpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) int load, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) load = hpm ? MMC_VQMMC_MAX_LOAD_UA : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) ret = regulator_set_load(mmc->supply.vqmmc, load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) dev_err(mmc_dev(mmc), "%s: vqmmc set load failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) mmc_hostname(mmc), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) struct mmc_host *mmc, bool level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) bool always_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (IS_ERR(mmc->supply.vqmmc) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) (mmc->ios.power_mode == MMC_POWER_UNDEFINED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * For eMMC don't turn off Vqmmc, Instead just configure it in LPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * and HPM modes by setting the corresponding load.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * Till eMMC is initialized (i.e. always_on == 0), just turn on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * Vqmmc. Vqmmc gets turned off only if init fails and mmc_power_off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * gets invoked. Once eMMC is initialized (i.e. always_on == 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * Vqmmc should remain ON, So just set the load instead of turning it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) * off/on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) always_on = !mmc_card_is_removable(mmc) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) mmc->card && mmc_card_mmc(mmc->card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (always_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) ret = msm_config_vqmmc_mode(msm_host, mmc, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) ret = msm_toggle_vqmmc(msm_host, mmc, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) init_waitqueue_head(&msm_host->pwr_irq_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static inline void sdhci_msm_complete_pwr_irq_wait(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) struct sdhci_msm_host *msm_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) wake_up(&msm_host->pwr_irq_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * sdhci_msm_check_power_status API should be called when registers writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) * To what state the register writes will change the IO lines should be passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) * as the argument req_type. This API will check whether the IO line's state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) * is already the expected state and will wait for power irq only if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) * power irq is expected to be triggered based on the current IO line state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) * and expected IO line state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) bool done = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) const struct sdhci_msm_offset *msm_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) msm_host->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) mmc_hostname(host->mmc), __func__, req_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) msm_host->curr_pwr_state, msm_host->curr_io_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) * The power interrupt will not be generated for signal voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) * Since sdhci-msm-v5, this bit has been removed and SW must consider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) * it as always set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (!msm_host->mci_removed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) val = msm_host_readl(msm_host, host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) msm_offset->core_generics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * The IRQ for request type IO High/LOW will be generated when -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * there is a state change in 1.8V enable bit (bit 3) of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) * which indicates 3.3V IO voltage. So, when MMC core layer tries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * to set it to 3.3V before card detection happens, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * IRQ doesn't get triggered as there is no state change in this bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * The driver already handles this case by changing the IO voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) * level to high as part of controller power up sequence. Hence, check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) * for host->pwr to handle a case where IO voltage high request is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) * issued even before controller power up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if ((req_type & REQ_IO_HIGH) && !host->pwr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) mmc_hostname(host->mmc), req_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if ((req_type & msm_host->curr_pwr_state) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) (req_type & msm_host->curr_io_level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * This is needed here to handle cases where register writes will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * not change the current bus state or io level of the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * In this case, no power irq will be triggerred and we should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * not wait.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (!done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (!wait_event_timeout(msm_host->pwr_irq_wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) msm_host->pwr_irq_flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) dev_warn(&msm_host->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) "%s: pwr_irq for req: (%d) timed out\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) mmc_hostname(host->mmc), req_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) __func__, req_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) const struct sdhci_msm_offset *msm_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) msm_host->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) mmc_hostname(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) u32 irq_status, irq_ack = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) int retry = 10, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) u32 pwr_state = 0, io_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) const struct sdhci_msm_offset *msm_offset = msm_host->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) irq_status = msm_host_readl(msm_host, host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) msm_offset->core_pwrctl_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) irq_status &= INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) msm_host_writel(msm_host, irq_status, host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) msm_offset->core_pwrctl_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) * There is a rare HW scenario where the first clear pulse could be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) * lost when actual reset and clear/read of status register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) * happening at a time. Hence, retry for at least 10 times to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) * sure status register is cleared. Otherwise, this will result in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) * a spurious power IRQ resulting in system instability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) while (irq_status & msm_host_readl(msm_host, host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) msm_offset->core_pwrctl_status)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (retry == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) mmc_hostname(host->mmc), irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) sdhci_msm_dump_pwr_ctrl_regs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) msm_host_writel(msm_host, irq_status, host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) msm_offset->core_pwrctl_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) retry--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /* Handle BUS ON/OFF*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (irq_status & CORE_PWRCTL_BUS_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) pwr_state = REQ_BUS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) io_level = REQ_IO_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (irq_status & CORE_PWRCTL_BUS_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) pwr_state = REQ_BUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) io_level = REQ_IO_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (pwr_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) ret = sdhci_msm_set_vmmc(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) ret = sdhci_msm_set_vqmmc(msm_host, mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) pwr_state & REQ_BUS_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) ret = sdhci_msm_set_pincfg(msm_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) pwr_state & REQ_BUS_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) irq_ack |= CORE_PWRCTL_BUS_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) /* Handle IO LOW/HIGH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (irq_status & CORE_PWRCTL_IO_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) io_level = REQ_IO_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (irq_status & CORE_PWRCTL_IO_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) io_level = REQ_IO_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (io_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) irq_ack |= CORE_PWRCTL_IO_SUCCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) dev_err(mmc_dev(mmc), "%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) mmc_hostname(mmc), ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) mmc->ios.signal_voltage, mmc->ios.vdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) irq_ack |= CORE_PWRCTL_IO_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) * The driver has to acknowledge the interrupt, switch voltages and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * report back if it succeded or not to this register. The voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * switches are handled by the sdhci core, so just report success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) msm_host_writel(msm_host, irq_ack, host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) msm_offset->core_pwrctl_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) * If we don't have info regarding the voltage levels supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) * regulators, don't change the IO PAD PWR SWITCH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) u32 new_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) * We should unset IO PAD PWR switch only if the register write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) * can set IO lines high and the regulator also switches to 3 V.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) * Else, we should keep the IO PAD PWR switch set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) * This is applicable to certain targets where eMMC vccq supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) * IO PAD PWR switch must be kept set to reflect actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) * regulator voltage. This way, during initialization of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) * controllers with only 1.8V, we will set the IO PAD bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) * without waiting for a REQ_IO_LOW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) new_config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if ((io_level & REQ_IO_HIGH) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) (msm_host->caps_0 & CORE_3_0V_SUPPORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) new_config &= ~CORE_IO_PAD_PWR_SWITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) else if ((io_level & REQ_IO_LOW) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) (msm_host->caps_0 & CORE_1_8V_SUPPORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) new_config |= CORE_IO_PAD_PWR_SWITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (config ^ new_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) writel_relaxed(new_config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (pwr_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) msm_host->curr_pwr_state = pwr_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (io_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) msm_host->curr_io_level = io_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) dev_dbg(mmc_dev(mmc), "%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) irq_ack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) struct sdhci_host *host = (struct sdhci_host *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) sdhci_msm_handle_pwr_irq(host, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) msm_host->pwr_irq_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) sdhci_msm_complete_pwr_irq_wait(msm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) struct clk *core_clk = msm_host->bulk_clks[0].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) return clk_round_rate(core_clk, ULONG_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) return SDHCI_MSM_MIN_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) * __sdhci_msm_set_clock - sdhci_msm clock control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) * Description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) * MSM controller does not use internal divider and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) * instead directly control the GCC clock as per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) * HW recommendation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) u16 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * Keep actual_clock as zero -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * - since there is no divider used so no need of having actual_clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * - MSM controller uses SDCLK for data timeout calculation. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * actual_clock is zero, host->clock is taken for calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) host->mmc->actual_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (clock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) * MSM controller do not use clock divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * Thus read SDHCI_CLOCK_CONTROL and only enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) * clock with no divider value programmed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) sdhci_enable_clk(host, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (!clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) msm_host->clk_rate = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) sdhci_msm_hc_select_mode(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) msm_set_clock_rate_for_bus_mode(host, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) __sdhci_msm_set_clock(host, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) /*****************************************************************************\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) * Inline Crypto Engine (ICE) support *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) \*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) #ifdef CONFIG_MMC_CRYPTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) #define AES_256_XTS_KEY_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) /* QCOM ICE registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) #define QCOM_ICE_REG_VERSION 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) #define QCOM_ICE_REG_FUSE_SETTING 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) #define QCOM_ICE_FUSE_SETTING_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) #define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) #define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) #define QCOM_ICE_REG_BIST_STATUS 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #define QCOM_ICE_BIST_STATUS_MASK 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #define QCOM_ICE_REG_ADVANCED_CONTROL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) #define sdhci_msm_ice_writel(host, val, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) writel((val), (host)->ice_mem + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) #define sdhci_msm_ice_readl(host, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) readl((host)->ice_mem + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) static bool sdhci_msm_ice_supported(struct sdhci_msm_host *msm_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) struct device *dev = mmc_dev(msm_host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) u32 regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) int major = regval >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) int minor = (regval >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) int step = regval & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) /* For now this driver only supports ICE version 3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) if (major != 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) dev_warn(dev, "Unsupported ICE version: v%d.%d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) major, minor, step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) major, minor, step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) /* If fuses are blown, ICE might not work in the standard way. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_FUSE_SETTING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) if (regval & (QCOM_ICE_FUSE_SETTING_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) dev_warn(dev, "Fuses are blown; ICE is unusable!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) return devm_clk_get(dev, "ice");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct cqhci_host *cq_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) struct mmc_host *mmc = msm_host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) struct device *dev = mmc_dev(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) res = platform_get_resource_byname(msm_host->pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) "ice");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) dev_warn(dev, "ICE registers not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) goto disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (!qcom_scm_ice_available()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) dev_warn(dev, "ICE SCM interface not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) goto disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) msm_host->ice_mem = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) if (IS_ERR(msm_host->ice_mem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) err = PTR_ERR(msm_host->ice_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) dev_err(dev, "Failed to map ICE registers; err=%d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) if (!sdhci_msm_ice_supported(msm_host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) goto disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) mmc->caps2 |= MMC_CAP2_CRYPTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) dev_warn(dev, "Disabling inline encryption support\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) static void sdhci_msm_ice_low_power_mode_enable(struct sdhci_msm_host *msm_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) * Enable low power mode sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) * [0]-0, [1]-0, [2]-0, [3]-E, [4]-0, [5]-0, [6]-0, [7]-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) regval |= 0x7000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static void sdhci_msm_ice_optimization_enable(struct sdhci_msm_host *msm_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) /* ICE Optimizations Enable Sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) regval |= 0xD807100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) /* ICE HPG requires delay before writing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) * Wait until the ICE BIST (built-in self-test) has completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) * This may be necessary before ICE can be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) * Note that we don't really care whether the BIST passed or failed; we really
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) * just want to make sure that it isn't still running. This is because (a) the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) * BIST is a FIPS compliance thing that never fails in practice, (b) ICE is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) * documented to reject crypto requests if the BIST fails, so we needn't do it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) * in software too, and (c) properly testing storage encryption requires testing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) * the full storage stack anyway, and not relying on hardware-level self-tests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) static int sdhci_msm_ice_wait_bist_status(struct sdhci_msm_host *msm_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) err = readl_poll_timeout(msm_host->ice_mem + QCOM_ICE_REG_BIST_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) regval, !(regval & QCOM_ICE_BIST_STATUS_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) 50, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) dev_err(mmc_dev(msm_host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) "Timed out waiting for ICE self-test to complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) sdhci_msm_ice_low_power_mode_enable(msm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) sdhci_msm_ice_optimization_enable(msm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) sdhci_msm_ice_wait_bist_status(msm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) static int __maybe_unused sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) return sdhci_msm_ice_wait_bist_status(msm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) * Program a key into a QC ICE keyslot, or evict a keyslot. QC ICE requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) * vendor-specific SCM calls for this; it doesn't support the standard way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) static int sdhci_msm_program_key(struct cqhci_host *cq_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) const union cqhci_crypto_cfg_entry *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) struct device *dev = mmc_dev(cq_host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) union cqhci_crypto_cap_entry cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) u8 bytes[AES_256_XTS_KEY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) } key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) if (!(cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) return qcom_scm_ice_invalidate_key(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) /* Only AES-256-XTS has been tested so far. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) dev_err_ratelimited(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) cap.algorithm_id, cap.key_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) memcpy(key.bytes, cfg->crypto_key, AES_256_XTS_KEY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) * The SCM call byte-swaps the 32-bit words of the key. So we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) * do the same, in order for the final key be correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) for (i = 0; i < ARRAY_SIZE(key.words); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) __cpu_to_be32s(&key.words[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) QCOM_SCM_ICE_CIPHER_AES_256_XTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) cfg->data_unit_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) memzero_explicit(&key, sizeof(key));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) #else /* CONFIG_MMC_CRYPTO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) static inline struct clk *sdhci_msm_ice_get_clk(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) struct cqhci_host *cq_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) static inline int __maybe_unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) #endif /* !CONFIG_MMC_CRYPTO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) /*****************************************************************************\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) * MSM Command Queue Engine (CQE) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) * *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) \*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) int cmd_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) int data_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) return intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) cqhci_irq(host->mmc, intmask, cmd_error, data_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) static void sdhci_msm_cqe_enable(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) sdhci_cqe_enable(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) sdhci_msm_ice_enable(msm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) * When CQE is halted, the legacy SDHCI path operates only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) * on 16-byte descriptors in 64bit mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) if (host->flags & SDHCI_USE_64_BIT_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) host->desc_sz = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) * During CQE command transfers, command complete bit gets latched.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) * So s/w should clear command complete interrupt status when CQE is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) * either halted or disabled. Otherwise unexpected SDCHI legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) * interrupt gets triggered when CQE is halted/disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) ctrl |= SDHCI_INT_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) sdhci_writel(host, ctrl, SDHCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) sdhci_cqe_disable(mmc, recovery);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) static void sdhci_msm_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) u32 count, start = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) __sdhci_set_timeout(host, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) count = sdhci_readb(host, SDHCI_TIMEOUT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) * Update software timeout value if its value is less than hardware data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) * timeout value. Qcom SoC hardware data timeout value was calculated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) if (cmd && cmd->data && host->clock > 400000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) host->clock <= 50000000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) ((1 << (count + start)) > (10 * host->clock)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) host->data_timeout = 22LL * NSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .enable = sdhci_msm_cqe_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .disable = sdhci_msm_cqe_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) #ifdef CONFIG_MMC_CRYPTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .program_key = sdhci_msm_program_key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) struct cqhci_host *cq_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) bool dma64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) u32 cqcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) * When CQE is halted, SDHC operates only on 16byte ADMA descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) * So ensure ADMA table is allocated for 16byte descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) if (host->caps & SDHCI_CAN_64BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) host->alloc_desc_sz = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) ret = sdhci_setup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) cq_host = cqhci_pltfm_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) if (IS_ERR(cq_host)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) ret = PTR_ERR(cq_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) cq_host->ops = &sdhci_msm_cqhci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) ret = sdhci_msm_ice_init(msm_host, cq_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) ret = cqhci_init(cq_host, host->mmc, dma64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) mmc_hostname(host->mmc), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) /* Disable cqe reset due to cqe enable signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) cqcfg = cqhci_readl(cq_host, CQHCI_VENDOR_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) cqcfg |= CQHCI_VENDOR_DIS_RST_ON_CQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) cqhci_writel(cq_host, cqcfg, CQHCI_VENDOR_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) * SDHC expects 12byte ADMA descriptors till CQE is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) * So limit desc_sz to 12 so that the data commands that are sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) * during card initialization (before CQE gets enabled) would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) * get executed without any issues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) if (host->flags & SDHCI_USE_64_BIT_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) host->desc_sz = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) ret = __sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) dev_info(&pdev->dev, "%s: CQE init: success\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) sdhci_cleanup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) * Platform specific register write functions. This is so that, if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) * register write needs to be followed up by platform specific actions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) * they can be added here. These functions can go to sleep when writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) * to certain registers are done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) * These functions are relying on sdhci_set_ios not using spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) u32 req_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) case SDHCI_HOST_CONTROL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) REQ_IO_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) case SDHCI_SOFTWARE_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) if (host->pwr && (val & SDHCI_RESET_ALL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) req_type = REQ_BUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) case SDHCI_POWER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) case SDHCI_TRANSFER_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) msm_host->transfer_mode = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) case SDHCI_COMMAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) if (!msm_host->use_cdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) sdhci_msm_set_cdr(host, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) sdhci_msm_set_cdr(host, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) if (req_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) msm_host->pwr_irq_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) * Since this register write may trigger a power irq, ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) * all previous register writes are complete by this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) return req_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) /* This function may sleep*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) u32 req_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) req_type = __sdhci_msm_check_write(host, val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) writew_relaxed(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (req_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) sdhci_msm_check_power_status(host, req_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) /* This function may sleep*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) u32 req_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) req_type = __sdhci_msm_check_write(host, val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) writeb_relaxed(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) if (req_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) sdhci_msm_check_power_status(host, req_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) struct mmc_host *mmc = msm_host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) struct regulator *supply = mmc->supply.vqmmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) u32 caps = 0, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) const struct sdhci_msm_offset *msm_offset = msm_host->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) if (!IS_ERR(mmc->supply.vqmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) if (regulator_is_supported_voltage(supply, 1700000, 1950000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) caps |= CORE_1_8V_SUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) if (regulator_is_supported_voltage(supply, 2700000, 3600000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) caps |= CORE_3_0V_SUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) if (!caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) pr_warn("%s: 1.8/3V not supported for vqmmc\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) mmc_hostname(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) if (caps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) * bit can be used as required later on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) u32 io_level = msm_host->curr_io_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) config = readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) config |= CORE_IO_PAD_PWR_SWITCH_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) config &= ~CORE_IO_PAD_PWR_SWITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) config |= CORE_IO_PAD_PWR_SWITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) writel_relaxed(config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) host->ioaddr + msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) msm_host->caps_0 |= caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) static void sdhci_msm_reset(struct sdhci_host *host, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) cqhci_deactivate(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) sdhci_reset(host, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) ret = mmc_regulator_get_supply(msm_host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) sdhci_msm_set_regulator_caps(msm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) static int sdhci_msm_start_signal_voltage_switch(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) u16 ctrl, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) * Signal Voltage Switching is only applicable for Host Controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) * v3.00 and above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) if (host->version < SDHCI_SPEC_300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) switch (ios->signal_voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) case MMC_SIGNAL_VOLTAGE_330:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) if (!(host->flags & SDHCI_SIGNALING_330))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) ctrl &= ~SDHCI_CTRL_VDD_180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) case MMC_SIGNAL_VOLTAGE_180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) if (!(host->flags & SDHCI_SIGNALING_180))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) /* Enable 1.8V Signal Enable in the Host Control2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) ctrl |= SDHCI_CTRL_VDD_180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) /* Wait for 5ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) usleep_range(5000, 5500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) /* regulator output should be stable within 5 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) status = ctrl & SDHCI_CTRL_VDD_180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) if ((ctrl & SDHCI_CTRL_VDD_180) == status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) dev_warn(mmc_dev(mmc), "%s: Regulator output did not became stable\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) mmc_hostname(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) #define DRIVER_NAME "sdhci_msm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) #define SDHCI_MSM_DUMP(f, x...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) static void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) const struct sdhci_msm_offset *msm_offset = msm_host->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) SDHCI_MSM_DUMP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) "DLL sts: 0x%08x | DLL cfg: 0x%08x | DLL cfg2: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) readl_relaxed(host->ioaddr + msm_offset->core_dll_status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) readl_relaxed(host->ioaddr + msm_offset->core_dll_config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) SDHCI_MSM_DUMP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) "DLL cfg3: 0x%08x | DLL usr ctl: 0x%08x | DDR cfg: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) readl_relaxed(host->ioaddr + msm_offset->core_ddr_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) SDHCI_MSM_DUMP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) "Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) readl_relaxed(host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) msm_offset->core_vendor_spec_func2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) static const struct sdhci_msm_variant_ops mci_var_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) static const struct sdhci_msm_variant_ops v5_var_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) .var_ops = &mci_var_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .offset = &sdhci_msm_mci_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .mci_removed = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .var_ops = &v5_var_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .offset = &sdhci_msm_v5_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) static const struct sdhci_msm_variant_info sdm845_sdhci_var = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .mci_removed = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .restore_dll_config = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .var_ops = &v5_var_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .offset = &sdhci_msm_v5_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) static const struct sdhci_msm_variant_info sm8250_sdhci_var = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .mci_removed = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .uses_tassadar_dll = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .var_ops = &v5_var_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .offset = &sdhci_msm_v5_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) static const struct of_device_id sdhci_msm_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) {.compatible = "qcom,sm8250-sdhci", .data = &sm8250_sdhci_var},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) static const struct sdhci_ops sdhci_msm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .reset = sdhci_msm_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .set_clock = sdhci_msm_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .get_min_clock = sdhci_msm_get_min_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .get_max_clock = sdhci_msm_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .write_w = sdhci_msm_writew,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .write_b = sdhci_msm_writeb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .irq = sdhci_msm_cqe_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .dump_vendor_regs = sdhci_msm_dump_vendor_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .set_power = sdhci_set_power_noreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .set_timeout = sdhci_msm_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) static const struct sdhci_pltfm_data sdhci_msm_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) SDHCI_QUIRK_SINGLE_POWER_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .ops = &sdhci_msm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) static inline void sdhci_msm_get_of_property(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) if (of_property_read_u32(node, "qcom,ddr-config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) &msm_host->ddr_config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) msm_host->ddr_config = DDR_CONFIG_POR_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) static int sdhci_msm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) struct sdhci_msm_host *msm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) u16 host_version, core_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) u32 core_version, config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) u8 core_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) const struct sdhci_msm_offset *msm_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) const struct sdhci_msm_variant_info *var_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) host->sdma_boundary = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) msm_host->mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) msm_host->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) ret = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) goto pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) * Based on the compatible string, load the required msm host info from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) * the data associated with the version info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) var_info = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) msm_host->mci_removed = var_info->mci_removed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) msm_host->restore_dll_config = var_info->restore_dll_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) msm_host->var_ops = var_info->var_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) msm_host->offset = var_info->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) msm_host->uses_tassadar_dll = var_info->uses_tassadar_dll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) msm_offset = msm_host->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) sdhci_get_of_property(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) sdhci_msm_get_of_property(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) /* Setup SDCC bus voter clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) if (!IS_ERR(msm_host->bus_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) /* Vote for max. clk rate for max. performance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) goto pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) ret = clk_prepare_enable(msm_host->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) goto pltfm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) /* Setup main peripheral bus clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) clk = devm_clk_get(&pdev->dev, "iface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) goto bus_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) msm_host->bulk_clks[1].clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) /* Setup SDC MMC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) clk = devm_clk_get(&pdev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) goto bus_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) msm_host->bulk_clks[0].clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) /* Check for optional interconnect paths */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) goto bus_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) if (IS_ERR(msm_host->opp_table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) ret = PTR_ERR(msm_host->opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) goto bus_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) /* OPP table is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) ret = dev_pm_opp_of_add_table(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) if (ret && ret != -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) dev_err(&pdev->dev, "Invalid OPP table in Device tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) goto opp_put_clkname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) /* Vote for maximum clock rate for maximum performance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) dev_warn(&pdev->dev, "core clock boost failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) clk = devm_clk_get(&pdev->dev, "cal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) msm_host->bulk_clks[2].clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) clk = devm_clk_get(&pdev->dev, "sleep");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) msm_host->bulk_clks[3].clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) clk = sdhci_msm_ice_get_clk(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) msm_host->bulk_clks[4].clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) msm_host->bulk_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) goto opp_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) * xo clock is needed for FLL feature of cm_dll.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) * In case if xo clock is not mentioned in DT, warn and proceed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) if (IS_ERR(msm_host->xo_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) ret = PTR_ERR(msm_host->xo_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) if (!msm_host->mci_removed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) if (IS_ERR(msm_host->core_mem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) ret = PTR_ERR(msm_host->core_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) /* Reset the vendor spec register to power on reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) host->ioaddr + msm_offset->core_vendor_spec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) if (!msm_host->mci_removed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) /* Set HC_MODE_EN bit in HC_MODE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) msm_host_writel(msm_host, HC_MODE_EN, host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) msm_offset->core_hc_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) config = msm_host_readl(msm_host, host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) msm_offset->core_hc_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) config |= FF_CLK_SW_RST_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) msm_host_writel(msm_host, config, host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) msm_offset->core_hc_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) SDHCI_VENDOR_VER_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) core_version = msm_host_readl(msm_host, host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) msm_offset->core_mci_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) CORE_VERSION_MAJOR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) core_minor = core_version & CORE_VERSION_MINOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) core_version, core_major, core_minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) if (core_major == 1 && core_minor >= 0x42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) msm_host->use_14lpp_dll_reset = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) * SDCC 5 controller with major version 1, minor version 0x34 and later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) if (core_major == 1 && core_minor < 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) msm_host->use_cdclp533 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) * Support for some capabilities is not advertised by newer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) * controller versions and must be explicitly enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) writel_relaxed(config, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) msm_offset->core_vendor_spec_capabilities0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) if (core_major == 1 && core_minor >= 0x49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) msm_host->updated_ddr_cfg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) ret = sdhci_msm_register_vreg(msm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) * Power on reset state may trigger power irq if previous status of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) * interrupt in GIC, any pending power irq interrupt should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) * acknowledged. Otherwise power irq interrupt handler would be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) * fired prematurely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) sdhci_msm_handle_pwr_irq(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) * Ensure that above writes are propogated before interrupt enablement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) * in GIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) /* Setup IRQ for handling power/voltage tasks with PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) if (msm_host->pwr_irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) ret = msm_host->pwr_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) sdhci_msm_init_pwr_irq_wait(msm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) /* Enable pwr irq interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) msm_host_writel(msm_host, INT_MASK, host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) msm_offset->core_pwrctl_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) sdhci_msm_pwr_irq, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) dev_name(&pdev->dev), host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) pm_runtime_set_autosuspend_delay(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) MSM_MMC_AUTOSUSPEND_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) host->mmc_host_ops.start_signal_voltage_switch =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) sdhci_msm_start_signal_voltage_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) if (of_property_read_bool(node, "supports-cqe"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) ret = sdhci_msm_cqe_add_host(host, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) ret = sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) goto pm_runtime_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) pm_runtime_mark_last_busy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) pm_runtime_put_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) pm_runtime_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) msm_host->bulk_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) opp_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) dev_pm_opp_of_remove_table(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) opp_put_clkname:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) dev_pm_opp_put_clkname(msm_host->opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) bus_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) if (!IS_ERR(msm_host->bus_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) clk_disable_unprepare(msm_host->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) pltfm_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) static int sdhci_msm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) struct sdhci_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) sdhci_remove_host(host, dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) dev_pm_opp_of_remove_table(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) dev_pm_opp_put_clkname(msm_host->opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) msm_host->bulk_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) if (!IS_ERR(msm_host->bus_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) clk_disable_unprepare(msm_host->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) /* Drop the performance vote */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) dev_pm_opp_set_rate(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) msm_host->bulk_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) msm_host->bulk_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) * Whenever core-clock is gated dynamically, it's needed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) * restore the SDR DLL settings when the clock is ungated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) if (msm_host->restore_dll_config && msm_host->clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) ret = sdhci_msm_restore_sdr_dll_config(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) dev_pm_opp_set_rate(dev, msm_host->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) return sdhci_msm_ice_resume(msm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) static const struct dev_pm_ops sdhci_msm_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) sdhci_msm_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) static struct platform_driver sdhci_msm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) .probe = sdhci_msm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) .remove = sdhci_msm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .name = "sdhci_msm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .of_match_table = sdhci_msm_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) .pm = &sdhci_msm_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) module_platform_driver(sdhci_msm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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