^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Vincent Yang <vincent.yang@tw.fujitsu.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Linaro Ltd Andy Green <andy.green@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2019 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Takao Orito <orito.takao@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "sdhci_f_sdh30.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* milbeaut bridge controller register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MLB_SOFT_RESET 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MLB_SOFT_RESET_RSTX BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MLB_WP_CD_LED_SET 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MLB_WP_CD_LED_SET_LED_INV BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MLB_CR_SET 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MLB_CR_SET_CR_TOCLKUNIT BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MLB_CR_SET_CR_TOCLKFREQ_SFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MLB_CR_SET_CR_TOCLKFREQ_MASK (0x3F << MLB_CR_SET_CR_TOCLKFREQ_SFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MLB_CR_SET_CR_BCLKFREQ_SFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MLB_CR_SET_CR_BCLKFREQ_MASK (0xFF << MLB_CR_SET_CR_BCLKFREQ_SFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MLB_CR_SET_CR_RTUNTIMER_SFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MLB_CR_SET_CR_RTUNTIMER_MASK (0xF << MLB_CR_SET_CR_RTUNTIMER_SFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MLB_SD_TOCLK_I_DIV 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MLB_TOCLKFREQ_UNIT_THRES 16000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MLB_CAL_TOCLKFREQ_MHZ(rate) (rate / MLB_SD_TOCLK_I_DIV / 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MLB_CAL_TOCLKFREQ_KHZ(rate) (rate / MLB_SD_TOCLK_I_DIV / 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MLB_TOCLKFREQ_MAX 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MLB_TOCLKFREQ_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MLB_SD_BCLK_I_DIV 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MLB_CAL_BCLKFREQ(rate) (rate / MLB_SD_BCLK_I_DIV / 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MLB_BCLKFREQ_MAX 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MLB_BCLKFREQ_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MLB_CDR_SET 0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MLB_CDR_SET_CLK2POW16 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct f_sdhost_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk *clk_iface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) bool enable_cmd_dat_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void sdhci_milbeaut_soft_voltage_switch(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) usleep_range(2500, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ctrl |= F_SDH30_CRES_O_DN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ctrl |= F_SDH30_MSEL_O_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ctrl &= ~F_SDH30_CRES_O_DN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) usleep_range(2500, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ctrl |= F_SDH30_CMD_CHK_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static unsigned int sdhci_milbeaut_get_min_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return F_SDH30_MIN_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void sdhci_milbeaut_reset(struct sdhci_host *host, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct f_sdhost_priv *priv = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u16 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ktime_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) clk = (clk & ~SDHCI_CLOCK_CARD_EN) | SDHCI_CLOCK_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) sdhci_reset(host, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) clk |= SDHCI_CLOCK_CARD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) timeout = ktime_add_ms(ktime_get(), 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) bool timedout = ktime_after(ktime_get(), timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (clk & SDHCI_CLOCK_INT_STABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (timedout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_err("%s: Internal clock never stabilised.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mmc_hostname(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) sdhci_dumpregs(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (priv->enable_cmd_dat_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ctl |= F_SDH30_CMD_DAT_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct sdhci_ops sdhci_milbeaut_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .voltage_switch = sdhci_milbeaut_soft_voltage_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .get_min_clock = sdhci_milbeaut_get_min_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .reset = sdhci_milbeaut_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .set_power = sdhci_set_power_and_bus_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void sdhci_milbeaut_bridge_reset(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int reset_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (reset_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) sdhci_writel(host, 0, MLB_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) sdhci_writel(host, MLB_SOFT_RESET_RSTX, MLB_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void sdhci_milbeaut_bridge_init(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 val, clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* IO_SDIO_CR_SET should be set while reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) val = sdhci_readl(host, MLB_CR_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) val &= ~(MLB_CR_SET_CR_TOCLKFREQ_MASK | MLB_CR_SET_CR_TOCLKUNIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MLB_CR_SET_CR_BCLKFREQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (rate >= MLB_TOCLKFREQ_UNIT_THRES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) clk = MLB_CAL_TOCLKFREQ_MHZ(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) clk = min_t(u32, MLB_TOCLKFREQ_MAX, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) val |= MLB_CR_SET_CR_TOCLKUNIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) (clk << MLB_CR_SET_CR_TOCLKFREQ_SFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) clk = MLB_CAL_TOCLKFREQ_KHZ(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) clk = min_t(u32, MLB_TOCLKFREQ_MAX, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clk = max_t(u32, MLB_TOCLKFREQ_MIN, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) val |= clk << MLB_CR_SET_CR_TOCLKFREQ_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clk = MLB_CAL_BCLKFREQ(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) clk = min_t(u32, MLB_BCLKFREQ_MAX, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clk = max_t(u32, MLB_BCLKFREQ_MIN, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val |= clk << MLB_CR_SET_CR_BCLKFREQ_SFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val &= ~MLB_CR_SET_CR_RTUNTIMER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) sdhci_writel(host, val, MLB_CR_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) sdhci_writel(host, MLB_CDR_SET_CLK2POW16, MLB_CDR_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) sdhci_writel(host, MLB_WP_CD_LED_SET_LED_INV, MLB_WP_CD_LED_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void sdhci_milbeaut_vendor_init(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct f_sdhost_priv *priv = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ctl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ctl |= F_SDH30_CRES_O_DN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ctl &= ~F_SDH30_MSEL_O_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ctl &= ~F_SDH30_CRES_O_DN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) sdhci_writel(host, ctl, F_SDH30_IO_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ctl = sdhci_readw(host, F_SDH30_AHB_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ctl |= F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) F_SDH30_AHB_INCR_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ctl &= ~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) sdhci_writew(host, ctl, F_SDH30_AHB_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (priv->enable_cmd_dat_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ctl |= F_SDH30_CMD_DAT_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct of_device_id mlb_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .compatible = "socionext,milbeaut-m10v-sdhci-3.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_DEVICE_TABLE(of, mlb_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void sdhci_milbeaut_init(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct f_sdhost_priv *priv = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int rate = clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u16 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) sdhci_milbeaut_bridge_reset(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ctl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ctl &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) sdhci_writew(host, ctl, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) sdhci_milbeaut_bridge_reset(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) sdhci_milbeaut_bridge_init(host, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) sdhci_milbeaut_bridge_reset(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) sdhci_milbeaut_vendor_init(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int sdhci_milbeaut_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int irq, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct f_sdhost_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) host = sdhci_alloc_host(dev, sizeof(struct f_sdhost_priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) priv = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) host->quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SDHCI_QUIRK_CLOCK_BEFORE_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) SDHCI_QUIRK_DELAY_AFTER_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) host->quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) SDHCI_QUIRK2_TUNING_WORK_AROUND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) priv->enable_cmd_dat_delay = device_property_read_bool(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "fujitsu,cmd-dat-delay-select");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) platform_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) host->hw_name = "f_sdh30";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) host->ops = &sdhci_milbeaut_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) host->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (IS_ERR(host->ioaddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = PTR_ERR(host->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (dev_of_node(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) sdhci_get_of_property(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) priv->clk_iface = devm_clk_get(&pdev->dev, "iface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (IS_ERR(priv->clk_iface)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ret = PTR_ERR(priv->clk_iface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = clk_prepare_enable(priv->clk_iface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) priv->clk = devm_clk_get(&pdev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) sdhci_milbeaut_init(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) goto err_add_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) err_add_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) clk_disable_unprepare(priv->clk_iface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) sdhci_free_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int sdhci_milbeaut_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct sdhci_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct f_sdhost_priv *priv = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) sdhci_remove_host(host, readl(host->ioaddr + SDHCI_INT_STATUS) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) clk_disable_unprepare(priv->clk_iface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) sdhci_free_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) platform_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static struct platform_driver sdhci_milbeaut_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .name = "sdhci-milbeaut",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .of_match_table = of_match_ptr(mlb_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .probe = sdhci_milbeaut_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .remove = sdhci_milbeaut_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) module_platform_driver(sdhci_milbeaut_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MODULE_DESCRIPTION("MILBEAUT SD Card Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MODULE_AUTHOR("Takao Orito <orito.takao@socionext.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MODULE_ALIAS("platform:sdhci-milbeaut");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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