Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (C) 2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * iProc SDHCI platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) struct sdhci_iproc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	const struct sdhci_pltfm_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u32 caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32 caps1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u32 mmc_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) struct sdhci_iproc_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	const struct sdhci_iproc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32 shadow_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u32 shadow_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	bool is_cmd_shadowed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	bool is_blk_shadowed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u32 val = readl(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	pr_debug("%s: readl [0x%02x] 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		 mmc_hostname(host->mmc), reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u16 word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		/* Get the saved transfer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		val = iproc_host->shadow_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	} else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		   iproc_host->is_blk_shadowed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		/* Get the saved block info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		val = iproc_host->shadow_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		val = sdhci_iproc_readl(host, (reg & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	return word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u32 val = sdhci_iproc_readl(host, (reg & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	return byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	pr_debug("%s: writel [0x%02x] 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		 mmc_hostname(host->mmc), reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	writel(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (host->clock <= 400000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		/* Round up to micro-second four SD clock delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		if (host->clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			udelay((4 * 1000000 + host->clock - 1) / host->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * The Arasan has a bugette whereby it may lose the content of successive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * writes to the same register that are within two SD-card clock cycles of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * each other (a clock domain crossing problem). The data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * register does not have this problem, which is just as well - otherwise we'd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * have to nobble the DMA engine too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * This wouldn't be a problem with the code except that we can only write the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * controller with 32-bit writes.  So two different 16-bit registers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * written back to back creates the problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * the work around can be further optimized. We can keep shadow values of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * by the TRANSFER+COMMAND in another 32-bit write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u32 word_shift = REG_OFFSET_IN_BITS(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u32 mask = 0xffff << word_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u32 oldval, newval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (reg == SDHCI_COMMAND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		/* Write the block now as we are issuing a command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		if (iproc_host->is_blk_shadowed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			sdhci_iproc_writel(host, iproc_host->shadow_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				SDHCI_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			iproc_host->is_blk_shadowed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		oldval = iproc_host->shadow_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		iproc_host->is_cmd_shadowed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	} else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		   iproc_host->is_blk_shadowed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		/* Block size and count are stored in shadow reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		oldval = iproc_host->shadow_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		/* Read reg, all other registers are not shadowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		oldval = sdhci_iproc_readl(host, (reg & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	newval = (oldval & ~mask) | (val << word_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (reg == SDHCI_TRANSFER_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		/* Save the transfer mode until the command is issued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		iproc_host->shadow_cmd = newval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		iproc_host->is_cmd_shadowed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		/* Save the block info until the command is issued */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		iproc_host->shadow_blk = newval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		iproc_host->is_blk_shadowed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		/* Command or other regular 32-bit write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		sdhci_iproc_writel(host, newval, reg & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	u32 byte_shift = REG_OFFSET_IN_BITS(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u32 mask = 0xff << byte_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	u32 newval = (oldval & ~mask) | (val << byte_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	sdhci_iproc_writel(host, newval, reg & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static unsigned int sdhci_iproc_get_max_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (pltfm_host->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return sdhci_pltfm_clk_get_max_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return pltfm_host->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  * There is a known bug on BCM2711's SDHCI core integration where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * controller will hang when the difference between the core clock and the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  * clock is too great. Specifically this can be reproduced under the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  * conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  *  - No SD card plugged in, polling thread is running, probing cards at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  *    100 kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  *  - BCM2711's core clock configured at 500MHz or more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  * So we set 200kHz as the minimum clock frequency available for that SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static unsigned int sdhci_iproc_bcm2711_get_min_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return 200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const struct sdhci_ops sdhci_iproc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.get_max_clock = sdhci_iproc_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct sdhci_ops sdhci_iproc_32only_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.read_l = sdhci_iproc_readl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.read_w = sdhci_iproc_readw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.read_b = sdhci_iproc_readb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.write_l = sdhci_iproc_writel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.write_w = sdhci_iproc_writew,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.write_b = sdhci_iproc_writeb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.get_max_clock = sdhci_iproc_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		  SDHCI_QUIRK_NO_HISPD_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | SDHCI_QUIRK2_HOST_OFF_CARD_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.ops = &sdhci_iproc_32only_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct sdhci_iproc_data iproc_cygnus_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.pdata = &sdhci_iproc_cygnus_pltfm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			& SDHCI_MAX_BLOCK_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		SDHCI_CAN_VDD_330 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		SDHCI_CAN_VDD_180 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		SDHCI_CAN_DO_SUSPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		SDHCI_CAN_DO_HISPD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		SDHCI_CAN_DO_ADMA2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		SDHCI_CAN_DO_SDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.caps1 = SDHCI_DRIVER_TYPE_C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		 SDHCI_DRIVER_TYPE_D |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		 SDHCI_SUPPORT_DDR50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.mmc_caps = MMC_CAP_1_8V_DDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		  SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		  SDHCI_QUIRK_NO_HISPD_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.ops = &sdhci_iproc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const struct sdhci_iproc_data iproc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.pdata = &sdhci_iproc_pltfm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			& SDHCI_MAX_BLOCK_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		SDHCI_CAN_VDD_330 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		SDHCI_CAN_VDD_180 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		SDHCI_CAN_DO_SUSPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		SDHCI_CAN_DO_HISPD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		SDHCI_CAN_DO_ADMA2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		SDHCI_CAN_DO_SDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.caps1 = SDHCI_DRIVER_TYPE_C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		 SDHCI_DRIVER_TYPE_D |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		 SDHCI_SUPPORT_DDR50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		  SDHCI_QUIRK_MISSING_CAPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		  SDHCI_QUIRK_NO_HISPD_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.ops = &sdhci_iproc_32only_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct sdhci_iproc_data bcm2835_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.pdata = &sdhci_bcm2835_pltfm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			& SDHCI_MAX_BLOCK_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		SDHCI_CAN_VDD_330 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		SDHCI_CAN_DO_HISPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.caps1 = SDHCI_DRIVER_TYPE_A |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		 SDHCI_DRIVER_TYPE_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.mmc_caps = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const struct sdhci_ops sdhci_iproc_bcm2711_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.read_l = sdhci_iproc_readl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.read_w = sdhci_iproc_readw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.read_b = sdhci_iproc_readb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	.write_l = sdhci_iproc_writel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.write_w = sdhci_iproc_writew,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.write_b = sdhci_iproc_writeb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.set_power = sdhci_set_power_and_bus_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.get_max_clock = sdhci_iproc_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.get_min_clock = sdhci_iproc_bcm2711_get_min_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct sdhci_pltfm_data sdhci_bcm2711_pltfm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.ops = &sdhci_iproc_bcm2711_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct sdhci_iproc_data bcm2711_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.pdata = &sdhci_bcm2711_pltfm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.mmc_caps = MMC_CAP_3_3V_DDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct of_device_id sdhci_iproc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	{ .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	{ .compatible = "brcm,bcm2711-emmc2", .data = &bcm2711_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	{ .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	{ .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  * This is a duplicate of bcm2835_(pltfrm_)data without caps quirks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  * which are provided by the ACPI table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct sdhci_pltfm_data sdhci_bcm_arasan_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		  SDHCI_QUIRK_NO_HISPD_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.ops = &sdhci_iproc_32only_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct sdhci_iproc_data bcm_arasan_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.pdata = &sdhci_bcm_arasan_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const struct acpi_device_id sdhci_iproc_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	{ .id = "BRCM5871", .driver_data = (kernel_ulong_t)&iproc_cygnus_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	{ .id = "BRCM5872", .driver_data = (kernel_ulong_t)&iproc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	{ .id = "BCM2847",  .driver_data = (kernel_ulong_t)&bcm_arasan_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{ .id = "BRCME88C", .driver_data = (kernel_ulong_t)&bcm2711_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MODULE_DEVICE_TABLE(acpi, sdhci_iproc_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int sdhci_iproc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	const struct sdhci_iproc_data *iproc_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	struct sdhci_iproc_host *iproc_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	iproc_data = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	if (!iproc_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	iproc_host = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	iproc_host->data = iproc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	ret = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	sdhci_get_property(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	host->mmc->caps |= iproc_host->data->mmc_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		pltfm_host->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		if (IS_ERR(pltfm_host->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			ret = PTR_ERR(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		ret = clk_prepare_enable(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			dev_err(dev, "failed to enable host clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		host->caps = iproc_host->data->caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		host->caps1 = iproc_host->data->caps1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	ret = sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	if (dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		clk_disable_unprepare(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct platform_driver sdhci_iproc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		.name = "sdhci-iproc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		.of_match_table = sdhci_iproc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		.acpi_match_table = ACPI_PTR(sdhci_iproc_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		.pm = &sdhci_pltfm_pmops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	.probe = sdhci_iproc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.remove = sdhci_pltfm_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) module_platform_driver(sdhci_iproc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MODULE_AUTHOR("Broadcom");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MODULE_DESCRIPTION("IPROC SDHCI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MODULE_LICENSE("GPL v2");