^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale eSDHC controller driver generics for OF and pltfm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2007 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2009 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2010 Pengutronix e.K.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 2020 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Wolfram Sang <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _DRIVERS_MMC_SDHCI_ESDHC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Ops and quirks for the Freescale eSDHC controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) SDHCI_QUIRK_32BIT_DMA_ADDR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) SDHCI_QUIRK_NO_BUSY_IRQ | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) SDHCI_QUIRK_PIO_NEEDS_DELAY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) SDHCI_QUIRK_NO_HISPD_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* pltfm-specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ESDHC_HOST_CONTROL_LE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * eSDHC register definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Present State Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ESDHC_PRSSTAT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ESDHC_CLOCK_GATE_OFF 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ESDHC_CLOCK_STABLE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Protocol Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ESDHC_PROCTL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ESDHC_VOLT_SEL 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ESDHC_CTRL_4BITBUS (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ESDHC_CTRL_8BITBUS (0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ESDHC_HOST_CONTROL_RES 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* System Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ESDHC_SYSTEM_CONTROL 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ESDHC_CLOCK_MASK 0x0000fff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ESDHC_PREDIV_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ESDHC_DIVIDER_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ESDHC_CLOCK_SDCLKEN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ESDHC_CLOCK_PEREN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ESDHC_CLOCK_HCKEN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ESDHC_CLOCK_IPGEN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* System Control 2 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ESDHC_SYSTEM_CONTROL_2 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ESDHC_SMPCLKSEL 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ESDHC_EXTN 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Host Controller Capabilities Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ESDHC_CAPABILITIES_1 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Tuning Block Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ESDHC_TBCTL 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ESDHC_HS400_WNDW_ADJUST 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ESDHC_HS400_MODE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ESDHC_TB_EN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ESDHC_TB_MODE_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ESDHC_TB_MODE_SW 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ESDHC_TB_MODE_3 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ESDHC_TBSTAT 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ESDHC_TBPTR 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ESDHC_WNDW_STRT_PTR_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ESDHC_WNDW_STRT_PTR_MASK (0x7f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ESDHC_WNDW_END_PTR_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* SD Clock Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ESDHC_SDCLKCTL 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ESDHC_LPBK_CLK_SEL 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ESDHC_CMD_CLK_CTL 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* SD Timing Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ESDHC_SDTIMNGCTL 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ESDHC_FLW_CTL_BG 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* DLL Config 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ESDHC_DLLCFG0 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ESDHC_DLL_ENABLE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ESDHC_DLL_RESET 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ESDHC_DLL_FREQ_SEL 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* DLL Config 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ESDHC_DLLCFG1 0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* DLL Status 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ESDHC_DLLSTAT0 0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ESDHC_DLL_STS_SLV_LOCK 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Control Register for DMA transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ESDHC_DMA_SYSCTL 0x40c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ESDHC_PERIPHERAL_CLK_SEL 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ESDHC_FLUSH_ASYNC_FIFO 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ESDHC_DMA_SNOOP 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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