Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Freescale eSDHC ColdFire family controller driver, platform bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2020 Timesys Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *   Author: Angelo Dureghello <angelo.dureghello@timesys.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_data/mmc-esdhc-mcf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "sdhci-esdhc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define	ESDHC_PROCTL_D3CD		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define ESDHC_SYS_CTRL_DTOCV_MASK	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define ESDHC_DEFAULT_HOST_CONTROL	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * Freescale eSDHC has DMA ERR flag at bit 28, not as std spec says, bit 25.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define ESDHC_INT_VENDOR_SPEC_DMA_ERR	BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct pltfm_mcf_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct clk *clk_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct clk *clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	int aside;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	int current_bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static inline void esdhc_mcf_buffer_swap32(u32 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	len = (len + 3) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	for (i = 0; i < len;  i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		temp = swab32(*buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		*buf++ = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static inline void esdhc_clrset_be(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 				   u32 mask, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	void __iomem *base = host->ioaddr + (reg & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u8 shift = (reg & 3) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	mask <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	val <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	if (reg == SDHCI_HOST_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		val |= ESDHC_PROCTL_D3CD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	writel((readl(base) & ~mask) | val, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * Note: mcf is big-endian, single bytes need to be accessed at big endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static void esdhc_mcf_writeb_be(struct sdhci_host *host, u8 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	void __iomem *base = host->ioaddr + (reg & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u8 shift = (reg & 3) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u32 mask = ~(0xff << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (reg == SDHCI_HOST_CONTROL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		u32 host_ctrl = ESDHC_DEFAULT_HOST_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		u8 dma_bits = (val & SDHCI_CTRL_DMA_MASK) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		u8 tmp = readb(host->ioaddr + SDHCI_HOST_CONTROL + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		tmp &= ~0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		tmp |= dma_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		 * Recomposition needed, restore always endianness and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		 * keep D3CD and AI, just setting bus width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		host_ctrl |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		host_ctrl |= (dma_bits << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		writel(host_ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	writel((readl(base) & mask) | (val << shift), base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static void esdhc_mcf_writew_be(struct sdhci_host *host, u16 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	void __iomem *base = host->ioaddr + (reg & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u8 shift = (reg & 3) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u32 mask = ~(0xffff << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	case SDHCI_TRANSFER_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		mcf_data->aside = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	case SDHCI_COMMAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			val |= SDHCI_CMD_ABORTCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		 * As for the fsl driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		 * we have to set the mode in a single write here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		writel(val << 16 | mcf_data->aside,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		       host->ioaddr + SDHCI_TRANSFER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	writel((readl(base) & mask) | (val << shift), base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void esdhc_mcf_writel_be(struct sdhci_host *host, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	writel(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static u8 esdhc_mcf_readb_be(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (reg == SDHCI_HOST_CONTROL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		u8 __iomem *base = host->ioaddr + (reg & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		u16 val = readw(base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		u8 dma_bits = (val >> 5) & SDHCI_CTRL_DMA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		u8 host_ctrl = val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		host_ctrl &= ~SDHCI_CTRL_DMA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		host_ctrl |= dma_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return host_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return readb(host->ioaddr + (reg ^ 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static u16 esdhc_mcf_readw_be(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 * For SDHCI_HOST_VERSION, sdhci specs defines 0xFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 * a wrong offset for us, we are at 0xFC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (reg == SDHCI_HOST_VERSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		reg -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	return readw(host->ioaddr + (reg ^ 0x2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static u32 esdhc_mcf_readl_be(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	val = readl(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	 * RM (25.3.9) sd pin clock must never exceed 25Mhz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 * So forcing legacy mode at 25Mhz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (unlikely(reg == SDHCI_CAPABILITIES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		val &= ~SDHCI_CAN_DO_HISPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (unlikely(reg == SDHCI_INT_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			val |= SDHCI_INT_ADMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static unsigned int esdhc_mcf_get_max_timeout_count(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	return 1 << 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void esdhc_mcf_set_timeout(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 				  struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* Use maximum timeout counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	esdhc_clrset_be(host, ESDHC_SYS_CTRL_DTOCV_MASK, 0xE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			SDHCI_TIMEOUT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void esdhc_mcf_reset(struct sdhci_host *host, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	sdhci_reset(host, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	esdhc_clrset_be(host, ESDHC_CTRL_BUSWIDTH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			mcf_data->current_bus_width, SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static unsigned int esdhc_mcf_pltfm_get_max_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return pltfm_host->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static unsigned int esdhc_mcf_pltfm_get_min_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return pltfm_host->clock / 256 / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void esdhc_mcf_pltfm_set_clock(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				      unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	unsigned long *pll_dr = (unsigned long *)MCF_PLL_DR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	u32 fvco, fsys, fesdhc, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	const int sdclkfs[] = {2, 4, 8, 16, 32, 64, 128, 256};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	int delta, old_delta = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	int i, q, ri, rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (clock == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		host->mmc->actual_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * ColdFire eSDHC clock.s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * pll -+-> / outdiv1 --> fsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 *      +-> / outdiv3 --> eSDHC clock ---> / SDCCLKFS / DVS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 * mcf5441x datasheet says:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 * (8.1.2) eSDHC should be 40 MHz max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 * (25.3.9) eSDHC input is, as example, 96 Mhz ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 * (25.3.9) sd pin clock must never exceed 25Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * fvco = fsys * outdvi1 + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 * fshdc = fvco / outdiv3 + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	temp = readl(pll_dr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	fsys = pltfm_host->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	fvco = fsys * ((temp & 0x1f) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	fesdhc = fvco / (((temp >> 10) & 0x1f) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	for (i = 0; i < 8; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		int result = fesdhc / sdclkfs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		for (q = 1; q < 17; ++q) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			int finale = result / q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			delta = abs(clock - finale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			if (delta < old_delta) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				old_delta = delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				ri = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				rq = q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	 * Apply divisors and re-enable all the clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	temp = ((sdclkfs[ri] >> 1) << 8) | ((rq - 1) << 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	esdhc_clrset_be(host, 0x0000fff7, temp, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	host->mmc->actual_clock = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void esdhc_mcf_pltfm_set_bus_width(struct sdhci_host *host, int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	case MMC_BUS_WIDTH_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		mcf_data->current_bus_width = ESDHC_CTRL_4BITBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		mcf_data->current_bus_width = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	esdhc_clrset_be(host, ESDHC_CTRL_BUSWIDTH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			mcf_data->current_bus_width, SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void esdhc_mcf_request_done(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 				   struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	u32 *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (!mrq->data || !mrq->data->bytes_xfered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		goto exit_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (mmc_get_dma_dir(mrq->data) != DMA_FROM_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		goto exit_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	 * On mcf5441x there is no hw sdma option/flag to select the dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	 * transfer endiannes. A swap after the transfer is needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	for_each_sg(mrq->data->sg, sg, mrq->data->sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		buffer = (u32 *)sg_virt(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		esdhc_mcf_buffer_swap32(buffer, sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) exit_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void esdhc_mcf_copy_to_bounce_buffer(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 					    struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 					    unsigned int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	sg_copy_to_buffer(data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			  host->bounce_buffer, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	esdhc_mcf_buffer_swap32((u32 *)host->bounce_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 				data->blksz * data->blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct sdhci_ops sdhci_esdhc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.reset = esdhc_mcf_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.set_clock = esdhc_mcf_pltfm_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.get_max_clock = esdhc_mcf_pltfm_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.get_min_clock = esdhc_mcf_pltfm_get_min_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.set_bus_width = esdhc_mcf_pltfm_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.get_max_timeout_count = esdhc_mcf_get_max_timeout_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.set_timeout = esdhc_mcf_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.write_b = esdhc_mcf_writeb_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.write_w = esdhc_mcf_writew_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.write_l = esdhc_mcf_writel_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.read_b = esdhc_mcf_readb_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.read_w = esdhc_mcf_readw_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	.read_l = esdhc_mcf_readl_be,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	.copy_to_bounce_buffer = esdhc_mcf_copy_to_bounce_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	.request_done = esdhc_mcf_request_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct sdhci_pltfm_data sdhci_esdhc_mcf_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	.ops = &sdhci_esdhc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_FORCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		 /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		  * Mandatory quirk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		  * controller does not support cmd23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		  * without, on > 8G cards cmd23 is used, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		  * driver times out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		  SDHCI_QUIRK2_HOST_NO_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int esdhc_mcf_plat_init(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			       struct pltfm_mcf_data *mcf_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	struct mcf_esdhc_platform_data *plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (!host->mmc->parent->platform_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		dev_err(mmc_dev(host->mmc), "no platform data!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	plat_data = (struct mcf_esdhc_platform_data *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			host->mmc->parent->platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	/* Card_detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	switch (plat_data->cd_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	case ESDHC_CD_CONTROLLER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		/* We have a working card_detect back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	case ESDHC_CD_PERMANENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		host->mmc->caps |= MMC_CAP_NONREMOVABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	case ESDHC_CD_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	switch (plat_data->max_bus_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		host->mmc->caps |= MMC_CAP_4_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int sdhci_esdhc_mcf_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	struct pltfm_mcf_data *mcf_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_mcf_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 				sizeof(*mcf_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	mcf_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	host->sdma_boundary = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	host->flags |= SDHCI_AUTO_CMD12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	mcf_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	if (IS_ERR(mcf_data->clk_ipg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		err = PTR_ERR(mcf_data->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	mcf_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	if (IS_ERR(mcf_data->clk_ahb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		err = PTR_ERR(mcf_data->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	mcf_data->clk_per = devm_clk_get(&pdev->dev, "per");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	if (IS_ERR(mcf_data->clk_per)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		err = PTR_ERR(mcf_data->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	pltfm_host->clk = mcf_data->clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	pltfm_host->clock = clk_get_rate(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	err = clk_prepare_enable(mcf_data->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	err = clk_prepare_enable(mcf_data->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		goto unprep_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	err = clk_prepare_enable(mcf_data->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		goto unprep_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	err = esdhc_mcf_plat_init(host, mcf_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		goto unprep_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	err = sdhci_setup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		goto unprep_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	if (!host->bounce_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		dev_err(&pdev->dev, "bounce buffer not allocated");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	err = __sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	sdhci_cleanup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unprep_ahb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	clk_disable_unprepare(mcf_data->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unprep_ipg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	clk_disable_unprepare(mcf_data->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unprep_per:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	clk_disable_unprepare(mcf_data->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) err_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int sdhci_esdhc_mcf_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	struct sdhci_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	struct pltfm_mcf_data *mcf_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	sdhci_remove_host(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	clk_disable_unprepare(mcf_data->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	clk_disable_unprepare(mcf_data->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	clk_disable_unprepare(mcf_data->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static struct platform_driver sdhci_esdhc_mcf_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		.name = "sdhci-esdhc-mcf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	.probe = sdhci_esdhc_mcf_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	.remove = sdhci_esdhc_mcf_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) module_platform_driver(sdhci_esdhc_mcf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) MODULE_DESCRIPTION("SDHCI driver for Freescale ColdFire eSDHC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MODULE_AUTHOR("Angelo Dureghello <angelo.dureghello@timesys.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MODULE_LICENSE("GPL v2");