^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale eSDHC i.MX controller driver for the platform bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * derived from the OF-version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2010 Pengutronix e.K.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Wolfram Sang <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_qos.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mmc/sdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_data/mmc-esdhc-imx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "sdhci-esdhc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "cqhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ESDHC_CTRL_D3CD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ESDHC_BURST_LEN_EN_INCR (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* VENDOR SPEC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ESDHC_VENDOR_SPEC 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ESDHC_DEBUG_SEL_REG 0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ESDHC_DEBUG_SEL_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ESDHC_DEBUG_SEL_CMD_STATE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ESDHC_DEBUG_SEL_DATA_STATE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ESDHC_DEBUG_SEL_TRANS_STATE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ESDHC_DEBUG_SEL_DMA_STATE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ESDHC_DEBUG_SEL_ADMA_STATE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ESDHC_DEBUG_SEL_FIFO_STATE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ESDHC_WTMK_LVL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ESDHC_WTMK_DEFAULT_VAL 0x10401040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ESDHC_WTMK_LVL_WML_VAL_DEF 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ESDHC_WTMK_LVL_WML_VAL_MAX 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ESDHC_MIX_CTRL 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ESDHC_MIX_CTRL_DDREN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Bits 3 and 6 are not SDHCI standard definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Tuning bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* dll control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ESDHC_DLL_CTRL 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* tune control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ESDHC_TUNE_CTRL_STATUS 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ESDHC_TUNE_CTRL_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ESDHC_TUNE_CTRL_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* strobe dll register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ESDHC_STROBE_DLL_CTRL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ESDHC_STROBE_DLL_STATUS 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ESDHC_VEND_SPEC2 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ESDHC_TUNING_CTRL 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ESDHC_STD_TUNING_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ESDHC_TUNING_START_TAP_DEFAULT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ESDHC_TUNING_START_TAP_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ESDHC_TUNING_STEP_MASK 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ESDHC_TUNING_STEP_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* pinctrl state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Our interpretation of the SDHCI_HOST_CONTROL register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ESDHC_CTRL_4BITBUS (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ESDHC_CTRL_8BITBUS (0x2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Define this macro DMA error INT for fsl eSDHC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* the address offset of CQHCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ESDHC_CQHCI_ADDR_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * The CMDTYPE of the CMD register (offset 0xE) should be set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * "11" when the STOP CMD12 is issued on imx53 to abort one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * open ended multi-blk IO. Otherwise the TC INT wouldn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * be generated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * In exact block transfer, the controller doesn't complete the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * operations automatically as required at the end of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * transfer and remains on hold if the abort command is not sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * As a result, the TC flag is not asserted and SW received timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * exception. Bit1 of Vendor Spec register is used to fix it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * The flag tells that the ESDHC controller is an USDHC block that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * integrated on the i.MX6 series.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ESDHC_FLAG_USDHC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* The IP supports manual tuning process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ESDHC_FLAG_MAN_TUNING BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* The IP supports standard tuning process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ESDHC_FLAG_STD_TUNING BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* The IP has SDHCI_CAPABILITIES_1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * The IP has erratum ERR004536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * when reading data from the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * This flag is also set for i.MX25 and i.MX35 in order to get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ESDHC_FLAG_ERR004536 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* The IP supports HS200 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ESDHC_FLAG_HS200 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* The IP supports HS400 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ESDHC_FLAG_HS400 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * The IP has errata ERR010450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ESDHC_FLAG_ERR010450 BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* The IP supports HS400ES mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ESDHC_FLAG_HS400_ES BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* The IP has Host Controller Interface for Command Queuing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ESDHC_FLAG_CQHCI BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* need request pmqos during low power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ESDHC_FLAG_PMQOS BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* The IP state got lost in low power mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* The IP lost clock rate in PM_RUNTIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * The IP do not support the ACMD23 feature completely when use ADMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * In ADMA mode, it only use the 16 bit block count of the register 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * ignore the upper 16 bit of the CMD23's argument. This will block the reliable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * write operation in RPMB, because RPMB reliable write need to set the bit31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * of the CMD23's argument.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * do not has this limitation. so when these SoC use ADMA mode, it need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * disable the ACMD23 feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct esdhc_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct esdhc_soc_data esdhc_imx25_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .flags = ESDHC_FLAG_ERR004536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct esdhc_soc_data esdhc_imx35_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .flags = ESDHC_FLAG_ERR004536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct esdhc_soc_data esdhc_imx51_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct esdhc_soc_data esdhc_imx53_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct esdhc_soc_data usdhc_imx6q_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) | ESDHC_FLAG_BROKEN_AUTO_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct esdhc_soc_data usdhc_imx6sl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) | ESDHC_FLAG_HS200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) | ESDHC_FLAG_BROKEN_AUTO_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct esdhc_soc_data usdhc_imx6sll_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) | ESDHC_FLAG_HS400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const struct esdhc_soc_data usdhc_imx6sx_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) | ESDHC_FLAG_STATE_LOST_IN_LPMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) | ESDHC_FLAG_BROKEN_AUTO_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const struct esdhc_soc_data usdhc_imx6ull_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) | ESDHC_FLAG_ERR010450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct esdhc_soc_data usdhc_imx7d_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) | ESDHC_FLAG_HS400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) | ESDHC_FLAG_STATE_LOST_IN_LPMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) | ESDHC_FLAG_BROKEN_AUTO_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static struct esdhc_soc_data usdhc_imx7ulp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct esdhc_soc_data usdhc_imx8qxp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) | ESDHC_FLAG_STATE_LOST_IN_LPMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct esdhc_soc_data usdhc_imx8mm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct pltfm_imx_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 scratchpad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct pinctrl_state *pins_100mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct pinctrl_state *pins_200mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) const struct esdhc_soc_data *socdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct esdhc_platform_data boarddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct clk *clk_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct clk *clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned int actual_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) NO_CMD_PENDING, /* no multiblock command pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) } multiblock_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 is_ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct pm_qos_request pm_qos_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct platform_device_id imx_esdhc_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .name = "sdhci-esdhc-imx25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .name = "sdhci-esdhc-imx35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .name = "sdhci-esdhc-imx51",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct of_device_id imx_esdhc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return data->socdata == &esdhc_imx25_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return data->socdata == &esdhc_imx53_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return data->socdata == &usdhc_imx6q_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) void __iomem *base = host->ioaddr + (reg & ~0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 shift = (reg & 0x3) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DRIVER_NAME "sdhci-esdhc-imx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define ESDHC_IMX_DUMP(f, x...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void esdhc_dump_debug_regs(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) char *debug_status[7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "cmd debug status",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "data debug status",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "trans debug status",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "dma debug status",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "adma debug status",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "fifo debug status",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "async fifo debug status"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) for (i = 0; i < 7; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u32 present_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 val = readl(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (unlikely(reg == SDHCI_PRESENT_STATE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 fsl_prss = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* save the least 20 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) val = fsl_prss & 0x000FFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* move dat[0-3] bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) val |= (fsl_prss & 0x0F000000) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* move cmd line bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) val |= (fsl_prss & 0x00800000) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (unlikely(reg == SDHCI_CAPABILITIES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) val &= 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* In FSL esdhc IC module, only bit20 is used to indicate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * ADMA2 capability of esdhc, but this bit is messed up on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * some SOCs (e.g. on MX25, MX35 this bit is set, but they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * don't actually support ADMA2). So set the BROKEN_ADMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * quirk on MX25/35 platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (val & SDHCI_CAN_DO_ADMA1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) val &= ~SDHCI_CAN_DO_ADMA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) val |= SDHCI_CAN_DO_ADMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (esdhc_is_usdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* imx6q/dl does not have cap_1 register, fake one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) | SDHCI_SUPPORT_SDR50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) | SDHCI_USE_SDR50_TUNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) | FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) SDHCI_TUNING_MODE_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) val |= SDHCI_SUPPORT_HS400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * Do not advertise faster UHS modes if there are no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * pinctrl states for 100MHz/200MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) IS_ERR_OR_NULL(imx_data->pins_200mhz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (unlikely(reg == SDHCI_INT_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) val |= SDHCI_INT_ADMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * mask off the interrupt we get in response to the manually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * sent CMD12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) val &= ~SDHCI_INT_RESPONSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) writel(SDHCI_INT_RESPONSE, host->ioaddr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) SDHCI_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) imx_data->multiblock_status = NO_CMD_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) reg == SDHCI_INT_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * Clear and then set D3CD bit to avoid missing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * card interrupt. This is an eSDHC controller problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * so we need to apply the following workaround: clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * and set D3CD bit will make eSDHC re-sample the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * interrupt. In case a card interrupt was lost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * re-sample it by the following steps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) data &= ~ESDHC_CTRL_D3CD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) data |= ESDHC_CTRL_D3CD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (val & SDHCI_INT_ADMA_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) val &= ~SDHCI_INT_ADMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) && (reg == SDHCI_INT_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) && (val & SDHCI_INT_DATA_END))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* send a manual CMD12 with RESPTYP=none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) data = MMC_STOP_TRANSMISSION << 24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) SDHCI_CMD_ABORTCMD << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) imx_data->multiblock_status = WAIT_FOR_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) writel(val, host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u16 ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (unlikely(reg == SDHCI_HOST_VERSION)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) reg ^= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (esdhc_is_usdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * The usdhc register returns a wrong host version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * Correct it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return SDHCI_SPEC_300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (val & ESDHC_VENDOR_SPEC_VSELECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret |= SDHCI_CTRL_VDD_180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (esdhc_is_usdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) val = readl(host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* the std tuning bits is in ACMD12_ERR for imx6sl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (val & ESDHC_MIX_CTRL_EXE_TUNE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret |= SDHCI_CTRL_EXEC_TUNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ret |= SDHCI_CTRL_TUNED_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (esdhc_is_usdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Swap AC23 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (m & ESDHC_MIX_CTRL_AC23EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ret &= ~ESDHC_MIX_CTRL_AC23EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret |= SDHCI_TRNS_AUTO_CMD23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return readw(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u32 new_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) case SDHCI_CLOCK_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (val & SDHCI_CLOCK_CARD_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) esdhc_wait_for_card_clock_gate_off(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) case SDHCI_HOST_CONTROL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (val & SDHCI_CTRL_VDD_180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) new_val |= ESDHC_VENDOR_SPEC_VSELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (val & SDHCI_CTRL_TUNED_CLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (val & SDHCI_CTRL_TUNED_CLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (val & SDHCI_CTRL_EXEC_TUNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) v |= ESDHC_MIX_CTRL_EXE_TUNE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) m |= ESDHC_MIX_CTRL_FBCLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) writel(m, host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) case SDHCI_TRANSFER_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) && (host->cmd->opcode == SD_IO_RW_EXTENDED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) && (host->cmd->data->blocks > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) && (host->cmd->data->flags & MMC_DATA_READ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (esdhc_is_usdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 wml;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* Swap AC23 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (val & SDHCI_TRNS_AUTO_CMD23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) val &= ~SDHCI_TRNS_AUTO_CMD23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) val |= ESDHC_MIX_CTRL_AC23EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) writel(m, host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Set watermark levels for PIO access to maximum value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * (128 words) to accommodate full 512 bytes buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * For DMA access restore the levels to default value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) m = readl(host->ioaddr + ESDHC_WTMK_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (val & SDHCI_TRNS_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u8 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * Since already disable DMA mode, so also need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * to clear the DMASEL. Otherwise, for standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * tuning, when send tuning command, usdhc will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * still prefetch the ADMA script from wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * DMA address, then we will see IOMMU report
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * some error which show lack of TLB mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ctrl &= ~SDHCI_CTRL_DMA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ESDHC_WTMK_LVL_WR_WML_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) writel(m, host->ioaddr + ESDHC_WTMK_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * Postpone this write, we must do it together with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * command write that is down below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) imx_data->scratchpad = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) case SDHCI_COMMAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) val |= SDHCI_CMD_ABORTCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (esdhc_is_usdhc(imx_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) writel(val << 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) host->ioaddr + SDHCI_TRANSFER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) writel(val << 16 | imx_data->scratchpad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) host->ioaddr + SDHCI_TRANSFER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) case SDHCI_BLOCK_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) esdhc_clrset_le(host, 0xffff, val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u8 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) case SDHCI_HOST_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) val = readl(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ret = val & SDHCI_CTRL_LED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ret |= (val & ESDHC_CTRL_4BITBUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return readb(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u32 new_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) case SDHCI_POWER_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * FSL put some DMA bits here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * If your board has a regulator, code should be here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) case SDHCI_HOST_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* FSL messed up here, so we need to manually compose it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) new_val = val & SDHCI_CTRL_LED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* ensure the endianness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) new_val |= ESDHC_HOST_CONTROL_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* bits 8&9 are reserved on mx25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (!is_imx25_esdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* DMA mode bits are shifted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * Do not touch buswidth bits here. This is done in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * esdhc_pltfm_bus_width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * Do not touch the D3CD bit either which is used for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * SDIO interrupt erratum workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) esdhc_clrset_le(host, mask, new_val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) case SDHCI_SOFTWARE_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (val & SDHCI_RESET_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) esdhc_clrset_le(host, 0xff, val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (reg == SDHCI_SOFTWARE_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (val & SDHCI_RESET_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * The esdhc has a design violation to SDHC spec which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * tells that software reset should not affect card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * detection circuit. But esdhc clears its SYSCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * register bits [0..2] during the software reset. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * will stop those clocks that card detection circuit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * relies on. To work around it, we turn the clocks on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * back to keep card detection circuit functional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * The reset on usdhc fails to clear MIX_CTRL register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * Do it manually here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (esdhc_is_usdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * the tuning bits should be kept during reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) imx_data->is_ddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) } else if (val & SDHCI_RESET_DATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * The eSDHC DAT line software reset clears at least the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * data transfer width on i.MX25, so make sure that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * Host Control register is unaffected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) esdhc_clrset_le(host, 0xff, new_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return pltfm_host->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return pltfm_host->clock / 256 / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) unsigned int host_clock = pltfm_host->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) int pre_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) int div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u32 temp, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (esdhc_is_usdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) host->ioaddr + ESDHC_VENDOR_SPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) esdhc_wait_for_card_clock_gate_off(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (clock == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) host->mmc->actual_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (is_imx53_esdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * According to the i.MX53 reference manual, if DLLCTRL[10] can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * be set, then the controller is eSDHCv3, else it is eSDHCv2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) val = readl(host->ioaddr + ESDHC_DLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) writel(val, host->ioaddr + ESDHC_DLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (temp & BIT(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) pre_div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) | ESDHC_CLOCK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) unsigned int max_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) max_clock = imx_data->is_ddr ? 45000000 : 150000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) clock = min(clock, max_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) pre_div < 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) pre_div *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) clock, host->mmc->actual_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) pre_div >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) div--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) | (div << ESDHC_DIVIDER_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) | (pre_div << ESDHC_PREDIV_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) (temp & ESDHC_CLOCK_STABLE), 2, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (esdhc_is_usdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) host->ioaddr + ESDHC_VENDOR_SPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct esdhc_platform_data *boarddata = &imx_data->boarddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) switch (boarddata->wp_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) case ESDHC_WP_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return mmc_gpio_get_ro(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) case ESDHC_WP_CONTROLLER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) SDHCI_WRITE_PROTECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) case ESDHC_WP_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) case MMC_BUS_WIDTH_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ctrl = ESDHC_CTRL_8BITBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) case MMC_BUS_WIDTH_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ctrl = ESDHC_CTRL_4BITBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * i.MX uSDHC internally already uses a fixed optimized timing for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * DDR50, normally does not require tuning for DDR50 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (host->timing == MMC_TIMING_UHS_DDR50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return sdhci_execute_tuning(mmc, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) u8 sw_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* FIXME: delay a bit for card to be ready for next tuning due to errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* IC suggest to reset USDHC before every tuning command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) !(sw_rst & SDHCI_RESET_ALL), 10, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dev_warn(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) "warning! RESET_ALL never complete before sending tuning command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ESDHC_MIX_CTRL_FBCLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dev_dbg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static void esdhc_post_tuning(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) int min, max, avg, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* find the mininum delay first which can pass tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) min = ESDHC_TUNE_CTRL_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) while (min < ESDHC_TUNE_CTRL_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) esdhc_prepare_tuning(host, min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (!mmc_send_tuning(host->mmc, opcode, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) min += ESDHC_TUNE_CTRL_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* find the maxinum delay which can not pass tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) max = min + ESDHC_TUNE_CTRL_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) while (max < ESDHC_TUNE_CTRL_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) esdhc_prepare_tuning(host, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (mmc_send_tuning(host->mmc, opcode, NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) max -= ESDHC_TUNE_CTRL_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) max += ESDHC_TUNE_CTRL_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /* use average delay to get the best timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) avg = (min + max) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) esdhc_prepare_tuning(host, avg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ret = mmc_send_tuning(host->mmc, opcode, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) esdhc_post_tuning(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ret ? "failed" : "passed", avg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) u32 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) m = readl(host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (ios->enhanced_strobe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) m |= ESDHC_MIX_CTRL_HS400_ES_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) writel(m, host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static int esdhc_change_pinstate(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) unsigned int uhs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct pinctrl_state *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (IS_ERR(imx_data->pinctrl) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) IS_ERR(imx_data->pins_100mhz) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) IS_ERR(imx_data->pins_200mhz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) switch (uhs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) case MMC_TIMING_UHS_SDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) case MMC_TIMING_UHS_DDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) pinctrl = imx_data->pins_100mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) case MMC_TIMING_UHS_SDR104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) case MMC_TIMING_MMC_HS200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) case MMC_TIMING_MMC_HS400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) pinctrl = imx_data->pins_200mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* back to default state for other legacy timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return pinctrl_select_default_state(mmc_dev(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return pinctrl_select_state(imx_data->pinctrl, pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * For HS400 eMMC, there is a data_strobe line. This signal is generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * by the device and used for data output and CRC status response output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * in HS400 mode. The frequency of this signal follows the frequency of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * CLK generated by host. The host receives the data which is aligned to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * edge of data_strobe line. Due to the time delay between CLK line and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * data_strobe line, if the delay time is larger than one clock cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * then CLK and data_strobe line will be misaligned, read error shows up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static void esdhc_set_strobe_dll(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) u32 strobe_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* disable clock before enabling strobe dll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) host->ioaddr + ESDHC_VENDOR_SPEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) esdhc_wait_for_card_clock_gate_off(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* force a reset on strobe dll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) writel(ESDHC_STROBE_DLL_CTRL_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) host->ioaddr + ESDHC_STROBE_DLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* clear the reset bit on strobe dll before any setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * enable strobe dll ctrl and adjust the delay target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * for the uSDHC loopback read clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (imx_data->boarddata.strobe_dll_delay_target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) v = ESDHC_STROBE_DLL_CTRL_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* wait max 50us to get the REF/SLV lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) dev_warn(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static void esdhc_reset_tuning(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* Reset the tuning circuit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (esdhc_is_usdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (ret == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) dev_warn(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) "Warning! clear execute tuning bit failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * usdhc IP internal logic flag execute_tuning_with_clr_buf, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * will finally make sure the normal data transfer logic correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ctrl |= SDHCI_INT_DATA_AVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) u32 m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct esdhc_platform_data *boarddata = &imx_data->boarddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /* disable ddr mode and disable HS400 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) m = readl(host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) imx_data->is_ddr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) switch (timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) case MMC_TIMING_UHS_SDR12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) case MMC_TIMING_UHS_SDR25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) case MMC_TIMING_UHS_SDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) case MMC_TIMING_UHS_SDR104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) case MMC_TIMING_MMC_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) case MMC_TIMING_MMC_HS200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) writel(m, host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) case MMC_TIMING_UHS_DDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) case MMC_TIMING_MMC_DDR52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) m |= ESDHC_MIX_CTRL_DDREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) writel(m, host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) imx_data->is_ddr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (boarddata->delay_line) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) v = boarddata->delay_line <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) ESDHC_DLL_OVERRIDE_VAL_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (is_imx53_esdhc(imx_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) v <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) writel(v, host->ioaddr + ESDHC_DLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) case MMC_TIMING_MMC_HS400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) writel(m, host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) imx_data->is_ddr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* update clock after enable DDR for strobe DLL lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) host->ops->set_clock(host, host->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) esdhc_set_strobe_dll(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) case MMC_TIMING_LEGACY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) esdhc_reset_tuning(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) esdhc_change_pinstate(host, timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static void esdhc_reset(struct sdhci_host *host, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) sdhci_reset(host, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* use maximum timeout counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) SDHCI_TIMEOUT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) int cmd_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) int data_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) cqhci_irq(host->mmc, intmask, cmd_error, data_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static struct sdhci_ops sdhci_esdhc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .read_l = esdhc_readl_le,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .read_w = esdhc_readw_le,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .read_b = esdhc_readb_le,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .write_l = esdhc_writel_le,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .write_w = esdhc_writew_le,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .write_b = esdhc_writeb_le,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .set_clock = esdhc_pltfm_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .get_max_clock = esdhc_pltfm_get_max_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .get_min_clock = esdhc_pltfm_get_min_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .get_max_timeout_count = esdhc_get_max_timeout_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .get_ro = esdhc_pltfm_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .set_timeout = esdhc_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .set_bus_width = esdhc_pltfm_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .set_uhs_signaling = esdhc_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .reset = esdhc_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .irq = esdhc_cqhci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .dump_vendor_regs = esdhc_dump_debug_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .ops = &sdhci_esdhc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct cqhci_host *cq_host = host->mmc->cqe_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (esdhc_is_usdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * The imx6q ROM code will change the default watermark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * level setting to something insane. Change it back here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * ROM code will change the bit burst_length_enable setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * to zero if this usdhc is chosen to boot system. Change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * it back here, otherwise it will impact the performance a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * lot. This bit is used to enable/disable the burst length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * for the external AHB2AXI bridge. It's useful especially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * for INCR transfer because without burst length indicator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * the AHB2AXI bridge does not know the burst length in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * advance. And without burst length indicator, AHB INCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * transfer can only be converted to singles on the AXI side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) | ESDHC_BURST_LEN_EN_INCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) host->ioaddr + SDHCI_HOST_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * TO1.1, it's harmless for MX6SL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) host->ioaddr + 0x6c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /* disable DLL_CTRL delay line settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * For the case of command with busy, if set the bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * transfer complete interrupt when busy is deasserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) * When CQHCI use DCMD to send a CMD need R1b respons,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) * otherwise DCMD will always meet timeout waiting for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * hardware interrupt issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) tmp |= ESDHC_STD_TUNING_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) ESDHC_TUNING_START_TAP_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (imx_data->boarddata.tuning_start_tap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) tmp &= ~ESDHC_TUNING_START_TAP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) tmp |= imx_data->boarddata.tuning_start_tap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (imx_data->boarddata.tuning_step) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) tmp &= ~ESDHC_TUNING_STEP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) tmp |= imx_data->boarddata.tuning_step
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) << ESDHC_TUNING_STEP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) /* Disable the CMD CRC check for tuning, if not, need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * add some delay after every tuning command, because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * hardware standard tuning logic will directly go to next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * step once it detect the CMD CRC error, will not wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) * the card side to finally send out the tuning data, trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * the buffer read ready interrupt immediately. If usdhc send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * the next tuning command some eMMC card will stuck, can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * response, block the tuning procedure or the first command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * after the whole tuning procedure always can't get any response.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * ESDHC_STD_TUNING_EN may be configed in bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * or ROM code, so clear this bit here to make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * the manual tuning can work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) tmp &= ~ESDHC_STD_TUNING_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * the 1st linux configure power/clock for the 2nd Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * After we clear the pending interrupt and halt CQCTL, issue gone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (cq_host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) tmp = cqhci_readl(cq_host, CQHCI_IS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) cqhci_writel(cq_host, tmp, CQHCI_IS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) static void esdhc_cqe_enable(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) struct cqhci_host *cq_host = mmc->cqe_private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) int count = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) * the case after tuning, so ensure the buffer is drained.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) while (reg & SDHCI_DATA_AVAILABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) sdhci_readl(host, SDHCI_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (count-- == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) dev_warn(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) "CQE may get stuck because the Buffer Read Enable bit is set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * Runtime resume will reset the entire host controller, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * Here set DMAEN and BCEN when enable CMDQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (host->flags & SDHCI_REQ_USE_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) mode |= SDHCI_TRNS_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) mode |= SDHCI_TRNS_BLK_CNT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * Though Runtime resume reset the entire host controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) * but do not impact the CQHCI side, need to clear the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * HALT bit, avoid CQHCI stuck in the first request when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) * system resume back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) cqhci_writel(cq_host, 0, CQHCI_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) "failed to exit halt state when enable CQE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) sdhci_cqe_enable(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) sdhci_dumpregs(mmc_priv(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static const struct cqhci_host_ops esdhc_cqhci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .enable = esdhc_cqe_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .disable = sdhci_cqe_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .dumpregs = esdhc_sdhci_dumpregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct pltfm_imx_data *imx_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) struct esdhc_platform_data *boarddata = &imx_data->boarddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (of_get_property(np, "fsl,wp-controller", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) boarddata->wp_type = ESDHC_WP_CONTROLLER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) * If we have this property, then activate WP check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) * Retrieveing and requesting the actual WP GPIO will happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * in the call to mmc_of_parse().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (of_property_read_bool(np, "wp-gpios"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) boarddata->wp_type = ESDHC_WP_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) of_property_read_u32(np, "fsl,tuning-start-tap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) &boarddata->tuning_start_tap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) of_property_read_u32(np, "fsl,strobe-dll-delay-target",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) &boarddata->strobe_dll_delay_target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (of_find_property(np, "no-1-8-v", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) boarddata->delay_line = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) mmc_of_parse_voltage(np, &host->ocr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) ESDHC_PINCTRL_STATE_100MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) ESDHC_PINCTRL_STATE_200MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* call to generic mmc_of_parse to support additional capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ret = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (mmc_gpio_get_cd(host->mmc) >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) struct pltfm_imx_data *imx_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) struct pltfm_imx_data *imx_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) struct esdhc_platform_data *boarddata = &imx_data->boarddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (!host->mmc->parent->platform_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) dev_err(mmc_dev(host->mmc), "no board data!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) imx_data->boarddata = *((struct esdhc_platform_data *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) host->mmc->parent->platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* write_protect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (boarddata->wp_type == ESDHC_WP_GPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) err = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) "failed to request write-protect gpio!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /* card_detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) switch (boarddata->cd_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) case ESDHC_CD_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) err = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) "failed to request card-detect gpio!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) case ESDHC_CD_CONTROLLER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* we have a working card_detect back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) case ESDHC_CD_PERMANENT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) host->mmc->caps |= MMC_CAP_NONREMOVABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) case ESDHC_CD_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) switch (boarddata->max_bus_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) host->mmc->caps |= MMC_CAP_4_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) const struct of_device_id *of_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) of_match_device(imx_esdhc_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct cqhci_host *cq_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) struct pltfm_imx_data *imx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) sizeof(*imx_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) pdev->id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) if (IS_ERR(imx_data->clk_ipg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) err = PTR_ERR(imx_data->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) goto free_sdhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if (IS_ERR(imx_data->clk_ahb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) err = PTR_ERR(imx_data->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) goto free_sdhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (IS_ERR(imx_data->clk_per)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) err = PTR_ERR(imx_data->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) goto free_sdhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) pltfm_host->clk = imx_data->clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) pltfm_host->clock = clk_get_rate(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) err = clk_prepare_enable(imx_data->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) goto free_sdhci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) err = clk_prepare_enable(imx_data->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) goto disable_per_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) err = clk_prepare_enable(imx_data->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) goto disable_ipg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (IS_ERR(imx_data->pinctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) if (esdhc_is_usdhc(imx_data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) /* GPIO CD can be set as a wakeup source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) host->mmc->caps |= MMC_CAP_CD_WAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) /* clear tuning bits in case ROM has set it already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) * Link usdhc specific mmc_host_ops execute_tuning function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) * to replace the standard one in sdhci_ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) sdhci_esdhc_ops.platform_execute_tuning =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) esdhc_executing_tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) host->mmc->caps2 |= MMC_CAP2_HS400_ES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) host->mmc_host_ops.hs400_enhanced_strobe =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) esdhc_hs400_enhanced_strobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (!cq_host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) goto disable_ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) cq_host->ops = &esdhc_cqhci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) err = cqhci_init(cq_host, host->mmc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) goto disable_ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) goto disable_ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) sdhci_esdhc_imx_hwinit(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) err = sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) goto disable_ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) pm_suspend_ignore_children(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) disable_ahb_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) clk_disable_unprepare(imx_data->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) disable_ipg_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) clk_disable_unprepare(imx_data->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) disable_per_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) clk_disable_unprepare(imx_data->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) free_sdhci:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) struct sdhci_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) int dead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) sdhci_remove_host(host, dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) clk_disable_unprepare(imx_data->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) clk_disable_unprepare(imx_data->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) clk_disable_unprepare(imx_data->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) static int sdhci_esdhc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (host->mmc->caps2 & MMC_CAP2_CQE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ret = cqhci_suspend(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) mmc_retune_timer_stop(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) mmc_retune_needed(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if (host->tuning_mode != SDHCI_TUNING_MODE_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) mmc_retune_needed(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ret = sdhci_suspend_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) ret = pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) ret = mmc_gpio_set_cd_wake(host->mmc, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) static int sdhci_esdhc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ret = pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) /* re-initialize hw state in case it's lost in low power mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) sdhci_esdhc_imx_hwinit(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) ret = sdhci_resume_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (host->mmc->caps2 & MMC_CAP2_CQE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) ret = cqhci_resume(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) ret = mmc_gpio_set_cd_wake(host->mmc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) static int sdhci_esdhc_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) if (host->mmc->caps2 & MMC_CAP2_CQE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) ret = cqhci_suspend(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) ret = sdhci_runtime_suspend_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (host->tuning_mode != SDHCI_TUNING_MODE_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) mmc_retune_needed(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) imx_data->actual_clock = host->mmc->actual_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) esdhc_pltfm_set_clock(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) clk_disable_unprepare(imx_data->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) clk_disable_unprepare(imx_data->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) clk_disable_unprepare(imx_data->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) static int sdhci_esdhc_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) clk_set_rate(imx_data->clk_per, pltfm_host->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) err = clk_prepare_enable(imx_data->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) goto remove_pm_qos_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) err = clk_prepare_enable(imx_data->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) goto disable_ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) err = clk_prepare_enable(imx_data->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) goto disable_per_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) esdhc_pltfm_set_clock(host, imx_data->actual_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) err = sdhci_runtime_resume_host(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) goto disable_ipg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (host->mmc->caps2 & MMC_CAP2_CQE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) err = cqhci_resume(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) disable_ipg_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) clk_disable_unprepare(imx_data->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) disable_per_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) clk_disable_unprepare(imx_data->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) disable_ahb_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) clk_disable_unprepare(imx_data->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) remove_pm_qos_request:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static const struct dev_pm_ops sdhci_esdhc_pmops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) sdhci_esdhc_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) static struct platform_driver sdhci_esdhc_imx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .name = "sdhci-esdhc-imx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .of_match_table = imx_esdhc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .pm = &sdhci_esdhc_pmops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .id_table = imx_esdhc_devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .probe = sdhci_esdhc_imx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .remove = sdhci_esdhc_imx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) module_platform_driver(sdhci_esdhc_imx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags