^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sdhci-dove.c Support for SDHCI on Marvell's Dove SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Saeed Bishara <saeed@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Mike Rapoport <mike@compulab.co.il>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on sdhci-cns3xxx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static u16 sdhci_dove_readw(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u16 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) case SDHCI_HOST_VERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) case SDHCI_SLOT_INT_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* those registers don't exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ret = readw(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static u32 sdhci_dove_readl(struct sdhci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ret = readl(host->ioaddr + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) case SDHCI_CAPABILITIES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Mask the support for 3.0V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ret &= ~SDHCI_CAN_VDD_300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const struct sdhci_ops sdhci_dove_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .read_w = sdhci_dove_readw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .read_l = sdhci_dove_readl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const struct sdhci_pltfm_data sdhci_dove_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .ops = &sdhci_dove_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SDHCI_QUIRK_NO_BUSY_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SDHCI_QUIRK_FORCE_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SDHCI_QUIRK_NO_HISPD_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int sdhci_dove_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) host = sdhci_pltfm_init(pdev, &sdhci_dove_pdata, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pltfm_host->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!IS_ERR(pltfm_host->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clk_prepare_enable(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ret = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) goto err_sdhci_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) goto err_sdhci_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) err_sdhci_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clk_disable_unprepare(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct of_device_id sdhci_dove_of_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { .compatible = "marvell,dove-sdhci", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MODULE_DEVICE_TABLE(of, sdhci_dove_of_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct platform_driver sdhci_dove_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .name = "sdhci-dove",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .pm = &sdhci_pltfm_pmops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .of_match_table = sdhci_dove_of_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .probe = sdhci_dove_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .remove = sdhci_pltfm_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) module_platform_driver(sdhci_dove_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MODULE_DESCRIPTION("SDHCI driver for Dove");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "Mike Rapoport <mike@compulab.co.il>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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