^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SDHCI support for CNS3xxx SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008 Cavium Networks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2010 MontaVista Software, LLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Authors: Scott Shu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Anton Vorontsov <avorontsov@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static unsigned int sdhci_cns3xxx_get_max_clk(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) return 150000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static void sdhci_cns3xxx_set_clock(struct sdhci_host *host, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct device *dev = mmc_dev(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) int div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u16 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) host->mmc->actual_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (clock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) while (host->max_clk / div > clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * On CNS3xxx divider grows linearly up to 4, and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * exponentially up to 256.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (div < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) div += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) else if (div < 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) div *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) dev_dbg(dev, "desired SD clock: %d, actual: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) clock, host->max_clk / div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Divide by 3 is special. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (div != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) div >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) clk = div << SDHCI_DIVIDER_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) clk |= SDHCI_CLOCK_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) timeout = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) & SDHCI_CLOCK_INT_STABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dev_warn(dev, "clock is unstable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) clk |= SDHCI_CLOCK_CARD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const struct sdhci_ops sdhci_cns3xxx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .get_max_clock = sdhci_cns3xxx_get_max_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .set_clock = sdhci_cns3xxx_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static const struct sdhci_pltfm_data sdhci_cns3xxx_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .ops = &sdhci_cns3xxx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .quirks = SDHCI_QUIRK_BROKEN_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int sdhci_cns3xxx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return sdhci_pltfm_register(pdev, &sdhci_cns3xxx_pdata, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct platform_driver sdhci_cns3xxx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .name = "sdhci-cns3xxx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .pm = &sdhci_pltfm_pmops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .probe = sdhci_cns3xxx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .remove = sdhci_pltfm_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) module_platform_driver(sdhci_cns3xxx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MODULE_DESCRIPTION("SDHCI driver for CNS3xxx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MODULE_AUTHOR("Scott Shu, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "Anton Vorontsov <avorontsov@mvista.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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