Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2016 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* HRS - Host Register Set (specific to Cadence) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SDHCI_CDNS_HRS04		0x10		/* PHY access port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define   SDHCI_CDNS_HRS04_ACK			BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define   SDHCI_CDNS_HRS04_RD			BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define   SDHCI_CDNS_HRS04_WR			BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define   SDHCI_CDNS_HRS04_RDATA		GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define   SDHCI_CDNS_HRS04_WDATA		GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define   SDHCI_CDNS_HRS04_ADDR			GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SDHCI_CDNS_HRS06		0x18		/* eMMC control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define   SDHCI_CDNS_HRS06_TUNE_UP		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define   SDHCI_CDNS_HRS06_TUNE			GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define   SDHCI_CDNS_HRS06_MODE			GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define   SDHCI_CDNS_HRS06_MODE_SD		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define   SDHCI_CDNS_HRS06_MODE_MMC_SDR		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define   SDHCI_CDNS_HRS06_MODE_MMC_DDR		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define   SDHCI_CDNS_HRS06_MODE_MMC_HS200	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define   SDHCI_CDNS_HRS06_MODE_MMC_HS400	0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define   SDHCI_CDNS_HRS06_MODE_MMC_HS400ES	0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* SRS - Slot Register Set (SDHCI-compatible) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SDHCI_CDNS_SRS_BASE		0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SDHCI_CDNS_PHY_DLY_SD_HS	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SDHCI_CDNS_PHY_DLY_UHS_SDR12	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SDHCI_CDNS_PHY_DLY_UHS_SDR25	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SDHCI_CDNS_PHY_DLY_UHS_SDR50	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SDHCI_CDNS_PHY_DLY_UHS_DDR50	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SDHCI_CDNS_PHY_DLY_EMMC_SDR	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SDHCI_CDNS_PHY_DLY_EMMC_DDR	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SDHCI_CDNS_PHY_DLY_SDCLK	0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SDHCI_CDNS_PHY_DLY_HSMMC	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SDHCI_CDNS_PHY_DLY_STROBE	0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * The tuned val register is 6 bit-wide, but not the whole of the range is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * available.  The range 0-42 seems to be available (then 43 wraps around to 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * but I am not quite sure if it is official.  Use only 0 to 39 for safety.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SDHCI_CDNS_MAX_TUNING_LOOP	40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) struct sdhci_cdns_phy_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct sdhci_cdns_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	void __iomem *hrs_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	bool enhanced_strobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	unsigned int nr_phy_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct sdhci_cdns_phy_param phy_params[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) struct sdhci_cdns_phy_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	const char *property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{ "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{ "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	{ "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	{ "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	{ "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{ "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{ "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				    u8 addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				 0, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	      FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	writel(tmp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	tmp |= SDHCI_CDNS_HRS04_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	writel(tmp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	tmp &= ~SDHCI_CDNS_HRS04_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	writel(tmp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				 0, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static unsigned int sdhci_cdns_phy_param_count(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	unsigned int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		if (of_property_read_bool(np, sdhci_cdns_phy_cfgs[i].property))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void sdhci_cdns_phy_param_parse(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 				       struct sdhci_cdns_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct sdhci_cdns_phy_param *p = priv->phy_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		ret = of_property_read_u32(np, sdhci_cdns_phy_cfgs[i].property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 					   &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		p->addr = sdhci_cdns_phy_cfgs[i].addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		p->data = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		p++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	for (i = 0; i < priv->nr_phy_params; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		ret = sdhci_cdns_write_phy_reg(priv, priv->phy_params[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 					       priv->phy_params[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void *sdhci_cdns_priv(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	return sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * Cadence's spec says the Timeout Clock Frequency is the same as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 * Base Clock Frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return host->max_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* The speed mode for eMMC is selected by HRS06 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	tmp &= ~SDHCI_CDNS_HRS06_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	tmp = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	tmp &= ~SDHCI_CDNS_HRS06_TUNE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * Workaround for IP errata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 * The IP6116 SD/eMMC PHY design has a timing issue on receive data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 * path. Send tune request twice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		writel(tmp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		ret = readl_poll_timeout(reg, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 					 !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 					 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * In SD mode, software must not use the hardware tuning and instead perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  * an almost identical procedure to eMMC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int sdhci_cdns_execute_tuning(struct sdhci_host *host, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	int cur_streak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	int max_streak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	int end_of_streak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	 * Do not execute tuning for UHS_SDR50 or UHS_DDR50.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	 * The delay is set by probe, based on the DT properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (host->timing != MMC_TIMING_MMC_HS200 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	    host->timing != MMC_TIMING_UHS_SDR104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		if (sdhci_cdns_set_tune_val(host, i) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		    mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			cur_streak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		} else { /* good */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			cur_streak++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			if (cur_streak > max_streak) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				max_streak = cur_streak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				end_of_streak = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (!max_streak) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		dev_err(mmc_dev(host->mmc), "no tuning point found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 					 unsigned int timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	switch (timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	case MMC_TIMING_MMC_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	case MMC_TIMING_MMC_DDR52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	case MMC_TIMING_MMC_HS200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	case MMC_TIMING_MMC_HS400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		if (priv->enhanced_strobe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		mode = SDHCI_CDNS_HRS06_MODE_SD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	sdhci_cdns_set_emmc_mode(priv, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	/* For SD, fall back to the default handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (mode == SDHCI_CDNS_HRS06_MODE_SD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		sdhci_set_uhs_signaling(host, timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct sdhci_ops sdhci_cdns_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.get_timeout_clock = sdhci_cdns_get_timeout_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.platform_execute_tuning = sdhci_cdns_execute_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.ops = &sdhci_cdns_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.ops = &sdhci_cdns_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 					     struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	priv->enhanced_strobe = ios->enhanced_strobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	mode = sdhci_cdns_get_emmc_mode(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400 && ios->enhanced_strobe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		sdhci_cdns_set_emmc_mode(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 					 SDHCI_CDNS_HRS06_MODE_MMC_HS400ES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400ES && !ios->enhanced_strobe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		sdhci_cdns_set_emmc_mode(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 					 SDHCI_CDNS_HRS06_MODE_MMC_HS400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int sdhci_cdns_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	const struct sdhci_pltfm_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	struct sdhci_cdns_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	unsigned int nr_phy_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	static const u16 version = SDHCI_SPEC_400 << SDHCI_SPEC_VER_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		data = &sdhci_cdns_pltfm_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	host = sdhci_pltfm_init(pdev, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 				struct_size(priv, phy_params, nr_phy_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	if (IS_ERR(host)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		ret = PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	pltfm_host->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	priv->nr_phy_params = nr_phy_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	priv->hrs_addr = host->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	priv->enhanced_strobe = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	host->ioaddr += SDHCI_CDNS_SRS_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	host->mmc_host_ops.hs400_enhanced_strobe =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 				sdhci_cdns_hs400_enhanced_strobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	sdhci_enable_v4_mode(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	__sdhci_read_caps(host, &version, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	sdhci_get_of_property(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	ret = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	sdhci_cdns_phy_param_parse(dev->of_node, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	ret = sdhci_cdns_phy_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	ret = sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int sdhci_cdns_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	struct sdhci_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	struct sdhci_cdns_priv *priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	ret = clk_prepare_enable(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	ret = sdhci_cdns_phy_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	ret = sdhci_resume_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	clk_disable_unprepare(pltfm_host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const struct dev_pm_ops sdhci_cdns_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_cdns_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static const struct of_device_id sdhci_cdns_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		.compatible = "socionext,uniphier-sd4hc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		.data = &sdhci_cdns_uniphier_pltfm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	{ .compatible = "cdns,sd4hc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static struct platform_driver sdhci_cdns_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		.name = "sdhci-cdns",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		.pm = &sdhci_cdns_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		.of_match_table = sdhci_cdns_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	.probe = sdhci_cdns_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	.remove = sdhci_pltfm_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) module_platform_driver(sdhci_cdns_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MODULE_LICENSE("GPL");