Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "sdhci-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "cqhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SDHCI_VENDOR 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define  SDHCI_VENDOR_ENHANCED_STRB 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define BRCMSTB_PRIV_FLAGS_NO_64BIT		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SDHCI_ARASAN_CQE_BASE_ADDR		0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) struct sdhci_brcmstb_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	void __iomem *cfg_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	bool has_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct brcmstb_match_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct sdhci_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		__func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	reg = readl(host->ioaddr + SDHCI_VENDOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	if (ios->enhanced_strobe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		reg |= SDHCI_VENDOR_ENHANCED_STRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		reg &= ~SDHCI_VENDOR_ENHANCED_STRB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	writel(reg, host->ioaddr + SDHCI_VENDOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u16 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	host->mmc->actual_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (clock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	sdhci_enable_clk(host, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 					    unsigned int timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u16 ctrl_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		__func__, timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/* Select Bus Speed Mode for host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if ((timing == MMC_TIMING_MMC_HS200) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	    (timing == MMC_TIMING_UHS_SDR104))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	else if (timing == MMC_TIMING_UHS_SDR12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	else if (timing == MMC_TIMING_SD_HS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		 timing == MMC_TIMING_MMC_HS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		 timing == MMC_TIMING_UHS_SDR25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	else if (timing == MMC_TIMING_UHS_SDR50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	else if ((timing == MMC_TIMING_UHS_DDR50) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		 (timing == MMC_TIMING_MMC_DDR52))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	else if (timing == MMC_TIMING_MMC_HS400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	sdhci_dumpregs(mmc_priv(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	while (reg & SDHCI_DATA_AVAILABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		sdhci_readl(host, SDHCI_BUFFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	sdhci_cqe_enable(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.enable         = sdhci_brcmstb_cqe_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.disable        = sdhci_cqe_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.dumpregs       = sdhci_brcmstb_dumpregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct sdhci_ops sdhci_brcmstb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct sdhci_ops sdhci_brcmstb_ops_7216 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.set_clock = sdhci_brcmstb_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct brcmstb_match_priv match_priv_7425 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.flags = BRCMSTB_PRIV_FLAGS_NO_64BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.ops = &sdhci_brcmstb_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct brcmstb_match_priv match_priv_7445 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.flags = BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.ops = &sdhci_brcmstb_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct brcmstb_match_priv match_priv_7216 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.hs400es = sdhci_brcmstb_hs400es,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.ops = &sdhci_brcmstb_ops_7216,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct of_device_id sdhci_brcm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{ .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	{ .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	{ .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int cmd_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	int data_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		return intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int sdhci_brcmstb_add_host(struct sdhci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				  struct sdhci_brcmstb_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct cqhci_host *cq_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	bool dma64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (!priv->has_cqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	ret = sdhci_setup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	cq_host = devm_kzalloc(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			       sizeof(*cq_host), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (!cq_host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	cq_host->ops = &sdhci_brcmstb_cqhci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (dma64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	ret = cqhci_init(cq_host, host->mmc, dma64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	ret = __sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		goto cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	sdhci_cleanup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int sdhci_brcmstb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	const struct brcmstb_match_priv *match_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct sdhci_pltfm_data brcmstb_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct sdhci_pltfm_host *pltfm_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct sdhci_brcmstb_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct resource *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	bool has_cqe = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	match_priv = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	dev_dbg(&pdev->dev, "Probe found match for %s\n",  match->compatible);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	clk = devm_clk_get_optional(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return dev_err_probe(&pdev->dev, PTR_ERR(clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 				     "Failed to get clock from Device Tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	res = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		has_cqe = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	brcmstb_pdata.ops = match_priv->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	host = sdhci_pltfm_init(pdev, &brcmstb_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 				sizeof(struct sdhci_brcmstb_priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (IS_ERR(host)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		res = PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	pltfm_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	priv = sdhci_pltfm_priv(pltfm_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	priv->has_cqe = has_cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* Map in the non-standard CFG registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	priv->cfg_regs = devm_ioremap_resource(&pdev->dev, iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (IS_ERR(priv->cfg_regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		res = PTR_ERR(priv->cfg_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	sdhci_get_of_property(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	res = mmc_of_parse(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	 * If the chip has enhanced strobe and it's enabled, add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 * callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (match_priv->hs400es &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	    (host->mmc->caps2 & MMC_CAP2_HS400_ES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	 * Supply the existing CAPS, but clear the UHS modes. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	 * will allow these modes to be specified by device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	 * properties through mmc_of_parse().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (match_priv->flags & BRCMSTB_PRIV_FLAGS_NO_64BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		host->caps &= ~SDHCI_CAN_64BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			 SDHCI_SUPPORT_DDR50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	if (match_priv->flags & BRCMSTB_PRIV_FLAGS_BROKEN_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	res = sdhci_brcmstb_add_host(host, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	pltfm_host->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	sdhci_pltfm_free(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static void sdhci_brcmstb_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	sdhci_pltfm_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static struct platform_driver sdhci_brcmstb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		.name	= "sdhci-brcmstb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.pm	= &sdhci_pltfm_pmops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		.of_match_table = of_match_ptr(sdhci_brcm_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.probe		= sdhci_brcmstb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.remove		= sdhci_pltfm_unregister,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.shutdown	= sdhci_brcmstb_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) module_platform_driver(sdhci_brcmstb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MODULE_AUTHOR("Broadcom");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MODULE_LICENSE("GPL v2");