^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Secure Digital Host Controller Interface ACPI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2012, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mmc/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/cpu_device_id.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/intel-family.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/iosf_mbi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "sdhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SDHCI_ACPI_SD_CD = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SDHCI_ACPI_RUNTIME_PM = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct sdhci_acpi_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const struct sdhci_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int quirks2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int caps2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mmc_pm_flag_t pm_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct sdhci_acpi_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const struct sdhci_acpi_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int quirks2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int caps2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mmc_pm_flag_t pm_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) size_t priv_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int (*probe_slot)(struct platform_device *, struct acpi_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int (*remove_slot)(struct platform_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int (*free_slot)(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int (*setup_host)(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct sdhci_acpi_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const struct sdhci_acpi_slot *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) bool use_runtime_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bool is_intel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bool reset_signal_volt_on_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long private[] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DMI_QUIRK_SD_NO_WRITE_PROTECT = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return (void *)c->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return c->slot && (c->slot->flags & flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define INTEL_DSM_HS_CAPS_SDR25 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define INTEL_DSM_HS_CAPS_DDR50 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define INTEL_DSM_HS_CAPS_SDR50 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define INTEL_DSM_HS_CAPS_SDR104 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) INTEL_DSM_FNS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) INTEL_DSM_V18_SWITCH = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) INTEL_DSM_V33_SWITCH = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) INTEL_DSM_HS_CAPS = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct intel_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 dsm_fns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 hs_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const guid_t intel_dsm_guid =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int fn, u32 *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) union acpi_object *obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!obj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (obj->type == ACPI_TYPE_INTEGER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *result = obj->integer.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) size_t len = min_t(size_t, obj->buffer.length, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) memcpy(result, obj->buffer.pointer, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __func__, fn, obj->type, obj->buffer.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ACPI_FREE(obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int intel_dsm(struct intel_host *intel_host, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int fn, u32 *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return __intel_dsm(intel_host, dev, fn, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) intel_host->hs_caps = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pr_debug("%s: DSM not supported, error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mmc_hostname(mmc), err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pr_debug("%s: DSM function mask %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) mmc_hostname(mmc), intel_host->dsm_fns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct device *dev = mmc_dev(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct sdhci_acpi_host *c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct intel_host *intel_host = sdhci_acpi_priv(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) err = sdhci_start_signal_voltage_switch(mmc, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) switch (ios->signal_voltage) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case MMC_SIGNAL_VOLTAGE_330:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) fn = INTEL_DSM_V33_SWITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case MMC_SIGNAL_VOLTAGE_180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) fn = INTEL_DSM_V18_SWITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) err = intel_dsm(intel_host, dev, fn, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pr_debug("%s: %s DSM fn %u error %d result %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mmc_hostname(mmc), __func__, fn, err, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void sdhci_acpi_int_hw_reset(struct sdhci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) reg |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* For eMMC, minimum is 1us but give it 9us for good measure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) udelay(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) reg &= ~0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* For eMMC, minimum is 200us but give it 300us for good measure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) usleep_range(300, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct sdhci_ops sdhci_acpi_ops_dflt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct sdhci_ops sdhci_acpi_ops_int = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .reset = sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .hw_reset = sdhci_acpi_int_hw_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct sdhci_acpi_chip sdhci_acpi_chip_int = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .ops = &sdhci_acpi_ops_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #ifdef CONFIG_X86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static bool sdhci_acpi_byt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const struct x86_cpu_id byt[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return x86_match_cpu(byt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static bool sdhci_acpi_cht(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const struct x86_cpu_id cht[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return x86_match_cpu(cht);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define BYT_IOSF_SCCEP 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define BYT_IOSF_OCP_NETCTRL0 0x1078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void sdhci_acpi_byt_setting(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (!sdhci_acpi_byt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_err(dev, "%s read error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_err(dev, "%s write error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_dbg(dev, "%s completed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static bool sdhci_acpi_byt_defer(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!sdhci_acpi_byt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!iosf_mbi_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) sdhci_acpi_byt_setting(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static bool sdhci_acpi_cht_pci_wifi(unsigned int vendor, unsigned int device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned int slot, unsigned int parent_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct pci_dev *dev, *parent, *from = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev = pci_get_device(vendor, device, from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pci_dev_put(from);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) parent = pci_upstream_bridge(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (ACPI_COMPANION(&dev->dev) && PCI_SLOT(dev->devfn) == slot &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) parent && PCI_SLOT(parent->devfn) == parent_slot &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) !pci_upstream_bridge(parent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pci_dev_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) from = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * GPDwin uses PCI wifi which conflicts with SDIO's use of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * acpi_device_fix_up_power() on child device nodes. Identifying GPDwin is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * problematic, but since SDIO is only used for wifi, the presence of the PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * wifi card in the expected slot with an ACPI companion node, is used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * indicate that acpi_device_fix_up_power() should be avoided.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static inline bool sdhci_acpi_no_fixup_child_power(struct acpi_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return sdhci_acpi_cht() &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) acpi_dev_hid_uid_match(adev, "80860F14", "2") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) sdhci_acpi_cht_pci_wifi(0x14e4, 0x43ec, 0, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static inline void sdhci_acpi_byt_setting(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static inline bool sdhci_acpi_byt_defer(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static inline bool sdhci_acpi_no_fixup_child_power(struct acpi_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int bxt_get_cd(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int gpio_cd = mmc_gpio_get_cd(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!gpio_cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (host->flags & SDHCI_DEVICE_DEAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int intel_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct intel_host *intel_host = sdhci_acpi_priv(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct sdhci_host *host = c->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (acpi_dev_hid_uid_match(adev, "80860F14", "1") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (acpi_dev_hid_uid_match(adev, "80865ACA", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) host->mmc_host_ops.get_cd = bxt_get_cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) intel_dsm_init(intel_host, &pdev->dev, host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) host->mmc_host_ops.start_signal_voltage_switch =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) intel_start_signal_voltage_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) c->is_intel = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int intel_setup_host(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct intel_host *intel_host = sdhci_acpi_priv(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .chip = &sdhci_acpi_chip_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .flags = SDHCI_ACPI_RUNTIME_PM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) SDHCI_QUIRK_NO_LED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) SDHCI_QUIRK2_STOP_WITH_TC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .probe_slot = intel_probe_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .setup_host = intel_setup_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .priv_size = sizeof(struct intel_host),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) SDHCI_QUIRK_NO_LED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MMC_CAP_WAIT_WHILE_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .flags = SDHCI_ACPI_RUNTIME_PM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .pm_caps = MMC_PM_KEEP_POWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .probe_slot = intel_probe_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .setup_host = intel_setup_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .priv_size = sizeof(struct intel_host),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .flags = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) SDHCI_ACPI_RUNTIME_PM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) SDHCI_QUIRK_NO_LED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) SDHCI_QUIRK2_STOP_WITH_TC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .caps = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .probe_slot = intel_probe_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .setup_host = intel_setup_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .priv_size = sizeof(struct intel_host),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define VENDOR_SPECIFIC_PWRCTL_CLEAR_REG 0x1a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define VENDOR_SPECIFIC_PWRCTL_CTL_REG 0x1ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static irqreturn_t sdhci_acpi_qcom_handler(int irq, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct sdhci_host *host = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int qcom_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct sdhci_host *host = c->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int *irq = sdhci_acpi_priv(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) *irq = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) *irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (*irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return request_threaded_irq(*irq, NULL, sdhci_acpi_qcom_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) "sdhci_qcom", host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int qcom_free_slot(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct sdhci_host *host = c->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct acpi_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int *irq = sdhci_acpi_priv(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) adev = ACPI_COMPANION(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (!adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (*irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) free_irq(*irq, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .quirks2 = SDHCI_QUIRK2_NO_1_8_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .caps = MMC_CAP_NONREMOVABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .priv_size = sizeof(int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .probe_slot = qcom_probe_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .free_slot = qcom_free_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .caps = MMC_CAP_NONREMOVABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct amd_sdhci_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) bool tuned_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) bool dll_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* AMD sdhci reset dll register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define SDHCI_AMD_RESET_DLL_REGISTER 0x908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int amd_select_drive_strength(struct mmc_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned int max_dtr, int host_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int card_drv, int *drv_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) *drv_type = MMC_SET_DRIVER_TYPE_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return MMC_SET_DRIVER_TYPE_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* AMD Platform requires dll setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) amd_host->dll_enabled = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * The initialization sequence for HS400 is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * HS->HS200->Perform Tuning->HS->HS400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * The re-tuning sequence is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * mode. If we switch to a different mode, we need to disable the tuned clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * If we have previously performed tuning and switch back to HS200 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * HS400, we can re-enable the tuned clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) unsigned int old_timing = host->timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) sdhci_set_ios(mmc, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (old_timing != host->timing && amd_host->tuned_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (host->timing == MMC_TIMING_MMC_HS400 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) host->timing == MMC_TIMING_MMC_HS200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) val |= SDHCI_CTRL_TUNED_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) val &= ~SDHCI_CTRL_TUNED_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* DLL is only required for HS400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (host->timing == MMC_TIMING_MMC_HS400 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) !amd_host->dll_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) sdhci_acpi_amd_hs400_dll(host, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int amd_sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct sdhci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) amd_host->tuned_clock = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) err = sdhci_execute_tuning(mmc, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (!err && !host->tuning_err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) amd_host->tuned_clock = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (mask & SDHCI_RESET_ALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) amd_host->tuned_clock = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) sdhci_acpi_amd_hs400_dll(host, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) sdhci_reset(host, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const struct sdhci_ops sdhci_acpi_ops_amd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .set_clock = sdhci_set_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .set_bus_width = sdhci_set_bus_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .reset = amd_sdhci_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .set_uhs_signaling = sdhci_set_uhs_signaling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .ops = &sdhci_acpi_ops_amd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct acpi_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct sdhci_host *host = c->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) sdhci_read_caps(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (host->caps1 & SDHCI_SUPPORT_DDR50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) host->mmc->caps = MMC_CAP_1_8V_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if ((host->caps1 & SDHCI_SUPPORT_SDR104) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) (host->mmc->caps & MMC_CAP_1_8V_DDR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) host->mmc->caps2 = MMC_CAP2_HS400_1_8V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * There are two types of presets out in the wild:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * 1) Default/broken presets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * These presets have two sets of problems:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * a) The clock divisor for SDR12, SDR25, and SDR50 is too small.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * This results in clock frequencies that are 2x higher than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * acceptable. i.e., SDR12 = 25 MHz, SDR25 = 50 MHz, SDR50 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * 100 MHz.x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * b) The HS200 and HS400 driver strengths don't match.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * By default, the SDR104 preset register has a driver strength of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * A, but the (internal) HS400 preset register has a driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * strength of B. As part of initializing HS400, HS200 tuning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * needs to be performed. Having different driver strengths
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * between tuning and operation is wrong. It results in different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * rise/fall times that lead to incorrect sampling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * 2) Firmware with properly initialized presets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * These presets have proper clock divisors. i.e., SDR12 => 12MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * SDR25 => 25 MHz, SDR50 => 50 MHz. Additionally the HS200 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * HS400 preset driver strengths match.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * Enabling presets for HS400 doesn't work for the following reasons:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * 1) sdhci_set_ios has a hard coded list of timings that are used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * to determine if presets should be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * 2) sdhci_get_preset_value is using a non-standard register to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * read out HS400 presets. The AMD controller doesn't support this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * non-standard register. In fact, it doesn't expose the HS400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * preset register anywhere in the SDHCI memory map. This results
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * in reading a garbage value and using the wrong presets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * Since HS400 and HS200 presets must be identical, we could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * instead use the the SDR104 preset register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * If the above issues are resolved we could remove this quirk for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * firmware that that has valid presets (i.e., SDR12 <= 12 MHz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) host->mmc_host_ops.set_ios = amd_set_ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) host->mmc_host_ops.execute_tuning = amd_sdhci_execute_tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .chip = &sdhci_acpi_chip_amd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) SDHCI_QUIRK_32BIT_DMA_SIZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) SDHCI_QUIRK_32BIT_ADMA_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .quirks2 = SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .probe_slot = sdhci_acpi_emmc_amd_probe_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .priv_size = sizeof(struct amd_sdhci_host),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct sdhci_acpi_uid_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) const char *hid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) const char *uid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) const struct sdhci_acpi_slot *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) { "80865ACA", NULL, &sdhci_acpi_slot_int_sd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) { "80860F14" , "3" , &sdhci_acpi_slot_int_sd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) { "80860F16" , NULL, &sdhci_acpi_slot_int_sd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) { "INT33BB" , "2" , &sdhci_acpi_slot_int_sdio },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) { "INT33BB" , "3" , &sdhci_acpi_slot_int_sd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) { "INT33C6" , NULL, &sdhci_acpi_slot_int_sdio },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) { "INT3436" , NULL, &sdhci_acpi_slot_int_sdio },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) { "INT344D" , NULL, &sdhci_acpi_slot_int_sdio },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) { "PNP0FFF" , "3" , &sdhci_acpi_slot_int_sd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) { "PNP0D40" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const struct acpi_device_id sdhci_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) { "80865ACA" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) { "80865ACC" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) { "80865AD0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) { "80860F14" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) { "80860F16" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) { "INT33BB" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) { "INT33C6" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) { "INT3436" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) { "INT344D" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) { "PNP0D40" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) { "QCOM8051" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) { "QCOM8052" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) { "AMDI0040" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static const struct dmi_system_id sdhci_acpi_quirks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * The Lenovo Miix 320-10ICR has a bug in the _PS0 method of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * the SHC1 ACPI device, this bug causes it to reprogram the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * wrong LDO (DLDO3) to 1.8V if 1.8V modes are used and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * card is (runtime) suspended + resumed. DLDO3 is used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * the LCD and setting it to 1.8V causes the LCD to go black.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .driver_data = (void *)DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * The Acer Aspire Switch 10 (SW5-012) microSD slot always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * reports the card being write-protected even though microSD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * cards do not have a write-protect switch at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * The Toshiba WT8-B's microSD slot always reports the card being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * write-protected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) DMI_MATCH(DMI_PRODUCT_NAME, "TOSHIBA ENCORE 2 WT8-B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {} /* Terminating entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(struct acpi_device *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) const struct sdhci_acpi_uid_slot *u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) for (u = sdhci_acpi_uids; u->hid; u++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (acpi_dev_hid_uid_match(adev, u->hid, u->uid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return u->slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static int sdhci_acpi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) const struct sdhci_acpi_slot *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct acpi_device *device, *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) const struct dmi_system_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct sdhci_acpi_host *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct sdhci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct resource *iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) resource_size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) size_t priv_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) int quirks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) device = ACPI_COMPANION(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (!device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) id = dmi_first_match(sdhci_acpi_quirks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) quirks = (long)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) slot = sdhci_acpi_get_slot(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* Power on the SDHCI controller and its children */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) acpi_device_fix_up_power(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (!sdhci_acpi_no_fixup_child_power(device)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) list_for_each_entry(child, &device->children, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (child->status.present && child->status.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) acpi_device_fix_up_power(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (sdhci_acpi_byt_defer(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (!iomem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) len = resource_size(iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (len < 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dev_err(dev, "Invalid iomem size!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) priv_size = slot ? slot->priv_size : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (IS_ERR(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return PTR_ERR(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) c = sdhci_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) c->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) c->slot = slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) c->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) platform_set_drvdata(pdev, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) host->hw_name = "ACPI";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) host->ops = &sdhci_acpi_ops_dflt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) host->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (host->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) host->ioaddr = devm_ioremap(dev, iomem->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) resource_size(iomem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (host->ioaddr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (c->slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (c->slot->probe_slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) err = c->slot->probe_slot(pdev, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (c->slot->chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) host->ops = c->slot->chip->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) host->quirks |= c->slot->chip->quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) host->quirks2 |= c->slot->chip->quirks2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) host->mmc->caps |= c->slot->chip->caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) host->mmc->caps2 |= c->slot->chip->caps2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) host->mmc->pm_caps |= c->slot->chip->pm_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) host->quirks |= c->slot->quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) host->quirks2 |= c->slot->quirks2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) host->mmc->caps |= c->slot->caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) host->mmc->caps2 |= c->slot->caps2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) host->mmc->pm_caps |= c->slot->pm_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (err == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dev_warn(dev, "failed to setup card detect gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) c->use_runtime_pm = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (quirks & DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) c->reset_signal_volt_on_suspend = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (quirks & DMI_QUIRK_SD_NO_WRITE_PROTECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) host->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) err = sdhci_setup_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (c->slot && c->slot->setup_host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) err = c->slot->setup_host(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) goto err_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) err = __sdhci_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) goto err_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (c->use_runtime_pm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) pm_suspend_ignore_children(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) pm_runtime_set_autosuspend_delay(dev, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) pm_runtime_use_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) device_enable_async_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) err_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) sdhci_cleanup_host(c->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (c->slot && c->slot->free_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) c->slot->free_slot(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) sdhci_free_host(c->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static int sdhci_acpi_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) int dead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (c->use_runtime_pm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (c->slot && c->slot->remove_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) c->slot->remove_slot(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) sdhci_remove_host(c->host, dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (c->slot && c->slot->free_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) c->slot->free_slot(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) sdhci_free_host(c->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static void __maybe_unused sdhci_acpi_reset_signal_voltage_if_needed(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct sdhci_acpi_host *c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct sdhci_host *host = c->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (c->is_intel && c->reset_signal_volt_on_suspend &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) host->mmc->ios.signal_voltage != MMC_SIGNAL_VOLTAGE_330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct intel_host *intel_host = sdhci_acpi_priv(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) unsigned int fn = INTEL_DSM_V33_SWITCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) u32 result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) intel_dsm(intel_host, dev, fn, &result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static int sdhci_acpi_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct sdhci_acpi_host *c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct sdhci_host *host = c->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (host->tuning_mode != SDHCI_TUNING_MODE_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) mmc_retune_needed(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ret = sdhci_suspend_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) sdhci_acpi_reset_signal_voltage_if_needed(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static int sdhci_acpi_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct sdhci_acpi_host *c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) sdhci_acpi_byt_setting(&c->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return sdhci_resume_host(c->host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static int sdhci_acpi_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct sdhci_acpi_host *c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct sdhci_host *host = c->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (host->tuning_mode != SDHCI_TUNING_MODE_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) mmc_retune_needed(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ret = sdhci_runtime_suspend_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) sdhci_acpi_reset_signal_voltage_if_needed(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static int sdhci_acpi_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct sdhci_acpi_host *c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) sdhci_acpi_byt_setting(&c->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return sdhci_runtime_resume_host(c->host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static const struct dev_pm_ops sdhci_acpi_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) sdhci_acpi_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static struct platform_driver sdhci_acpi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .name = "sdhci-acpi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .acpi_match_table = sdhci_acpi_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .pm = &sdhci_acpi_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .probe = sdhci_acpi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .remove = sdhci_acpi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) module_platform_driver(sdhci_acpi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) MODULE_AUTHOR("Adrian Hunter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags