^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Synopsys DesignWare Multimedia Card Interface driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * (Based on NXP driver for lpc 31xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 NXP Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2014 Fuzhou Rockchip Electronics Co.Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * the Free Software Foundation; either version 2 of the License, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef _DW_MMC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define _DW_MMC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "rk_sdmmc_dbg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DW_MMC_240A 0x240a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DW_MMC_270A 0x270a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SDMMC_CTRL 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SDMMC_PWREN 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SDMMC_CLKDIV 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SDMMC_CLKSRC 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SDMMC_CLKENA 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SDMMC_TMOUT 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SDMMC_CTYPE 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SDMMC_BLKSIZ 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SDMMC_BYTCNT 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SDMMC_INTMASK 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SDMMC_CMDARG 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SDMMC_CMD 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SDMMC_RESP0 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SDMMC_RESP1 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SDMMC_RESP2 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SDMMC_RESP3 0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SDMMC_MINTSTS 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SDMMC_RINTSTS 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SDMMC_STATUS 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SDMMC_FIFOTH 0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SDMMC_CDETECT 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SDMMC_WRTPRT 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SDMMC_GPIO 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SDMMC_TCBCNT 0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SDMMC_TBBCNT 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SDMMC_DEBNCE 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SDMMC_USRID 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SDMMC_VERID 0x06c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SDMMC_HCON 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SDMMC_UHS_REG 0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SDMMC_RST_N 0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SDMMC_BMOD 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SDMMC_PLDMND 0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SDMMC_DBADDR 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SDMMC_IDSTS 0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SDMMC_IDINTEN 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SDMMC_DSCADDR 0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SDMMC_BUFADDR 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SDMMC_CDTHRCTL 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SDMMC_DATA(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const u8 tuning_blk_pattern_4bit[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const u8 tuning_blk_pattern_8bit[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Data offset is difference according to Version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Lower than 2.40a : data register offest is 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DATA_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DATA_240A_OFFSET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* shift bit field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define _SBF(f, v) ((v) << (f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct sdmmc_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct sdmmc_reg dw_mci_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { 0x0000, "CTRL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { 0x0004, "PWREN" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { 0x0008, "CLKDIV" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { 0x000C, "CLKSRC" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { 0x0010, "CLKENA" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { 0x0014, "TMOUT" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { 0x0018, "CTYPE" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { 0x001C, "BLKSIZ" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { 0x0020, "BYTCNT" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { 0x0024, "INTMASK" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 0x0028, "CMDARG" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 0x002C, "CMD" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 0x0030, "RESP0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 0x0034, "RESP1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 0x0038, "RESP2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { 0x003C, "RESP3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { 0x0040, "MINSTS" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { 0x0044, "RINTSTS" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 0x0048, "STATUS" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { 0x004C, "FIFOTH" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { 0x0050, "CDETECT" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { 0x0054, "WRTPRT" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 0x0058, "GPIO" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 0x005C, "TCBCNT" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 0x0060, "TBBCNT" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { 0x0064, "DEBNCE" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { 0x0068, "USRID" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { 0x006C, "VERID" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { 0x0070, "HCON" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { 0x0074, "UHS_REG" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { 0x0078, "RST_n" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { 0x0080, "BMOD" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { 0x0084, "PLDMND" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { 0x0088, "DBADDR" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { 0x008C, "IDSTS" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { 0x0090, "IDINTEN" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { 0x0094, "DSCADDR" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { 0x0098, "BUFADDR" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { 0x0100, "CARDTHRCTL" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { 0x0104, "BackEndPwr" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Control register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SDMMC_CTRL_USE_IDMAC BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SDMMC_CTRL_SEND_CCSD BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SDMMC_CTRL_READ_WAIT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SDMMC_CTRL_DMA_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SDMMC_CTRL_INT_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SDMMC_CTRL_DMA_RESET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SDMMC_CTRL_FIFO_RESET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SDMMC_CTRL_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Clock Enable register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SDMMC_CLKEN_LOW_PWR BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SDMMC_CLKEN_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* time-out register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SDMMC_TMOUT_RESP_MSK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* card-type register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SDMMC_CTYPE_8BIT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SDMMC_CTYPE_4BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SDMMC_CTYPE_1BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Interrupt status & mask register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SDMMC_INT_SDIO(n) BIT(16 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SDMMC_INT_EBE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SDMMC_INT_ACD BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SDMMC_INT_SBE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SDMMC_INT_HLE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SDMMC_INT_FRUN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SDMMC_INT_HTO BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SDMMC_INT_VSI SDMMC_INT_HTO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SDMMC_INT_DRTO BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SDMMC_INT_RTO BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SDMMC_INT_DCRC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SDMMC_INT_RCRC BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SDMMC_INT_RXDR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SDMMC_INT_TXDR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SDMMC_INT_DATA_OVER BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SDMMC_INT_CMD_DONE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SDMMC_INT_RESP_ERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SDMMC_INT_CD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SDMMC_INT_ERROR 0xbfc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Command register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SDMMC_CMD_START BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SDMMC_CMD_USE_HOLD_REG BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SDMMC_CMD_VOLT_SWITCH BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SDMMC_CMD_BOOT_MODE BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SDMMC_CMD_DISABLE_BOOT BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SDMMC_CMD_EXPECT_BOOT_ACK BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SDMMC_CMD_ENABLE_BOOT BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SDMMC_CMD_CCS_EXP BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SDMMC_CMD_CEATA_RD BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SDMMC_CMD_UPD_CLK BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SDMMC_CMD_INIT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SDMMC_CMD_STOP BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SDMMC_CMD_SEND_STOP BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SDMMC_CMD_STRM_MODE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SDMMC_CMD_DAT_WR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SDMMC_CMD_DAT_EXP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SDMMC_CMD_RESP_CRC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SDMMC_CMD_RESP_LONG BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define SDMMC_CMD_RESP_EXP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SDMMC_CMD_INDX(n) ((n) & 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Status register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SDMMC_STAUTS_MC_BUSY BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SDMMC_STAUTS_DATA_BUSY BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SDMMC_CMD_FSM_MASK (0x0F << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SDMMC_CMD_FSM_IDLE (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SDMMC_STAUTS_FIFO_FULL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SDMMC_STAUTS_FIFO_EMPTY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Control SDMMC_UHS_REG defines (base+ 0x74)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SDMMC_UHS_DDR_MODE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SDMMC_UHS_VOLT_REG_18 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* FIFOTH register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ((r) & 0xFFF) << 16 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ((t) & 0xFFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Internal DMAC interrupt defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SDMMC_IDMAC_INT_AI BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SDMMC_IDMAC_INT_NI BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SDMMC_IDMAC_INT_CES BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SDMMC_IDMAC_INT_DU BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define SDMMC_IDMAC_INT_FBE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define SDMMC_IDMAC_INT_RI BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SDMMC_IDMAC_INT_TI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Internal DMAC bus mode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SDMMC_IDMAC_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SDMMC_IDMAC_FB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SDMMC_IDMAC_SWRESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Version ID register define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Card read threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SDMMC_SET_RD_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Register access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define mci_readl(dev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) __raw_readl((dev)->regs + SDMMC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define mci_writel(dev, reg, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) __raw_writel((value), (dev)->regs + SDMMC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define mci_readreg(dev, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) __raw_readl((dev)->regs + addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define mci_writereg(dev, addr, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) __raw_writel((value), (dev)->regs + addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* 16-bit FIFO access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define mci_readw(dev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) __raw_readw((dev)->regs + SDMMC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define mci_writew(dev, reg, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) __raw_writew((value), (dev)->regs + SDMMC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* 64-bit FIFO access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #ifdef readq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define mci_readq(dev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) __raw_readq((dev)->regs + SDMMC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define mci_writeq(dev, reg, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) __raw_writeq((value), (dev)->regs + SDMMC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * Dummy readq implementation for architectures that don't define it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * We would assume that none of these architectures would configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * the IP block with a 64bit FIFO width, so this code will never be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * executed on those machines. Defining these macros here keeps the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * rest of the code free from ifdefs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define mci_readq(dev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) (*(u64 __force *)((dev)->regs + SDMMC_##reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define mci_writeq(dev, reg, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) (*(u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) extern int dw_mci_suspend(struct dw_mci *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) extern int dw_mci_resume(struct dw_mci *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct dw_mci_rst_ops dw_mci_pdrst_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * struct dw_mci_slot - MMC slot state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * @mmc: The mmc_host representing this slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * @host: The MMC controller this slot is using.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * @wp_gpio: If gpio_is_valid() we'll use this to read write protect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * @ctype: Card type for this slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * @mrq: mmc_request currently being processed or waiting to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * processed, or NULL when the slot is idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * @queue_node: List node for placing this node in the @queue list of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * &struct dw_mci.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * @clock: Clock rate configured by set_ios(). Protected by host->lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @__clk_old: The last updated clock with reflecting clock divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * Keeping track of this helps us to avoid spamming the console
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * with CONFIG_MMC_CLKGATE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * @flags: Random state bits associated with the slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * @id: Number of this slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * @last_detect_state: Most recently observed card detect state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct dw_mci_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct dw_mci *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int wp_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int cd_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int pwr_en_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 ctype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 pre_ctype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct list_head queue_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned int __clk_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DW_MMC_CARD_PRESENT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DW_MMC_CARD_NEED_INIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int last_detect_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct dw_mci_tuning_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) const u8 *blk_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * dw_mci driver data - dw-mshc implementation specific driver data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * @caps: mmc subsystem specified capabilities of the controller(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * @hold_reg_flag: Fixed the value of HOLG_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * @init: early implementation specific initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * @setup_clock: implementation specific clock configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @prepare_command: handle CMD register extensions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * @set_ios: handle bus specific extensions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @parse_dt: parse implementation specific device tree properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * Provide controller implementation specific extensions. The usage of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * data structure is fully optional and usage of each member in this structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * is optional as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct dw_mci_drv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned long *caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned int *hold_reg_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int (*init)(struct dw_mci *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int (*setup_clock)(struct dw_mci *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) void (*prepare_command)(struct dw_mci *host, u32 *cmdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int (*parse_dt)(struct dw_mci *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int (*execute_tuning)(struct dw_mci_slot *slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 opcode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct dw_mci_tuning_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *tuning_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Variations in Rockchip specific dw-mshc controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) enum dw_mci_rockchip_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) DW_MCI_TYPE_RK3188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) DW_MCI_TYPE_RK3288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) DW_MCI_TYPE_RK3036,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) DW_MCI_TYPE_RK312X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) DW_MCI_TYPE_RK3368,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) DW_MCI_TYPE_RK3228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #endif /* _DW_MMC_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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