Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Renesas Mobile SDHI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2017 Horms Solutions Ltd., Simon Horman
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2017-19 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef RENESAS_SDHI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RENESAS_SDHI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "tmio_mmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct renesas_sdhi_scc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	unsigned long clk_rate;	/* clock rate for SDR104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	u32 tap;		/* sampling clock position for SDR104/HS400 (8 TAP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	u32 tap_hs400_4tap;	/* sampling clock position for HS400 (4 TAP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct renesas_sdhi_of_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	unsigned long tmio_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	u32	      tmio_ocr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	unsigned long capabilities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	unsigned long capabilities2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	enum dma_slave_buswidth dma_buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	dma_addr_t dma_rx_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	unsigned int bus_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	int scc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	struct renesas_sdhi_scc *taps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	int taps_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	unsigned int max_blk_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	unsigned short max_segs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SDHI_CALIB_TABLE_MAX 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct renesas_sdhi_quirks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	bool hs400_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	bool hs400_4taps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	u32 hs400_bad_taps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct tmio_mmc_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	enum dma_slave_buswidth dma_buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	bool (*filter)(struct dma_chan *chan, void *arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	void (*enable)(struct tmio_mmc_host *host, bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	struct completion	dma_dataend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	struct tasklet_struct	dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct renesas_sdhi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	struct clk *clk_cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	struct tmio_mmc_data mmc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	struct tmio_mmc_dma dma_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	const struct renesas_sdhi_quirks *quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	struct pinctrl_state *pins_default, *pins_uhs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	void __iomem *scc_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	u32 scc_tappos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	u32 scc_tappos_hs400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	const u8 *adjust_hs400_calib_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	bool needs_adjust_hs400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	/* Tuning values: 1 for success, 0 for failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	DECLARE_BITMAP(taps, BITS_PER_LONG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	/* Sampling data comparison: 1 for match, 0 for mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	DECLARE_BITMAP(smpcmp, BITS_PER_LONG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	unsigned int tap_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	unsigned int tap_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define host_to_priv(host) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	container_of((host)->pdata, struct renesas_sdhi, mmc_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int renesas_sdhi_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 		       const struct tmio_mmc_dma_ops *dma_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int renesas_sdhi_remove(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif