^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #define MMC_STRPCL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define STOP_CLOCK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define START_CLOCK (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define MMC_STAT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define STAT_END_CMD_RES (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define STAT_PRG_DONE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define STAT_DATA_TRAN_DONE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define STAT_CLK_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define STAT_RECV_FIFO_FULL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define STAT_XMIT_FIFO_EMPTY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define STAT_RES_CRC_ERR (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define STAT_SPI_READ_ERROR_TOKEN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define STAT_CRC_READ_ERROR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define STAT_CRC_WRITE_ERROR (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define STAT_TIME_OUT_RESPONSE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define STAT_READ_TIME_OUT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MMC_CLKRT 0x0008 /* 3 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MMC_SPI 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPI_CS_ADDRESS (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPI_CS_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CRC_ON (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPI_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MMC_CMDAT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CMDAT_SDIO_INT_EN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CMDAT_SD_4DAT (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CMDAT_DMAEN (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CMDAT_INIT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CMDAT_BUSY (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CMDAT_STREAM (1 << 4) /* 1 = stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CMDAT_WRITE (1 << 3) /* 1 = write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CMDAT_DATAEN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CMDAT_RESP_NONE (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CMDAT_RESP_SHORT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CMDAT_RESP_R2 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CMDAT_RESP_R3 (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MMC_RESTO 0x0014 /* 7 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MMC_RDTO 0x0018 /* 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MMC_BLKLEN 0x001c /* 10 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MMC_NOB 0x0020 /* 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MMC_PRTBUF 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BUF_PART_FULL (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MMC_I_MASK 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*PXA27x MMC interrupts*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SDIO_SUSPEND_ACK (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SDIO_INT (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RD_STALLED (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RES_ERR (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DAT_ERR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TINT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*PXA2xx MMC interrupts*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TXFIFO_WR_REQ (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RXFIFO_RD_REQ (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_IS_OFF (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define STOP_CMD (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define END_CMD_RES (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PRG_DONE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DATA_TRAN_DONE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MMC_I_MASK_ALL 0x00001fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MMC_I_MASK_ALL 0x0000007f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MMC_I_REG 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* same as MMC_I_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MMC_CMD 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MMC_ARGH 0x0034 /* 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MMC_ARGL 0x0038 /* 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MMC_RES 0x003c /* 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MMC_RXFIFO 0x0040 /* 8 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MMC_TXFIFO 0x0044 /* 8 bit */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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