^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/mmc/host/pxa.c - PXA MMCI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003 Russell King, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This hardware is really sick:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * - No way to clear interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * - Have to turn off the clock whenever we touch the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * - Doesn't tell you how many data blocks were transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Yuck!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 1 and 3 byte data transfers not supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * max block length up to 1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/platform_data/mmc-pxamci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "pxamci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRIVER_NAME "pxa2xx-mci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NR_SG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLKRT_OFF (~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define mmc_has_26MHz() (cpu_is_pxa300() || cpu_is_pxa310() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) || cpu_is_pxa935())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct pxamci_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int clkrt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int cmdat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int imask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long detect_delay_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) bool use_ro_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct gpio_desc *power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct pxamci_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct mmc_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct dma_chan *dma_chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct dma_chan *dma_chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dma_cookie_t dma_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int dma_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int pxamci_init_ocr(struct pxamci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = mmc_regulator_get_supply(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (IS_ERR(mmc->supply.vmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* fall-back to platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mmc->ocr_avail = host->pdata ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) host->pdata->ocr_mask :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MMC_VDD_32_33 | MMC_VDD_33_34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline int pxamci_set_power(struct pxamci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned char power_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int vdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct regulator *supply = mmc->supply.vmmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!IS_ERR(supply))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return mmc_regulator_set_ocr(mmc, supply, vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (host->power) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bool on = !!((1 << vdd) & host->pdata->ocr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) gpiod_set_value(host->power, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (host->pdata && host->pdata->setpower)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return host->pdata->setpower(mmc_dev(host->mmc), vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void pxamci_stop_clock(struct pxamci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long timeout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel(STOP_CLOCK, host->base + MMC_STRPCL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) v = readl(host->base + MMC_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (!(v & STAT_CLK_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) } while (timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (v & STAT_CLK_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) host->imask &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writel(host->imask, host->base + MMC_I_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) host->imask |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writel(host->imask, host->base + MMC_I_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void pxamci_dma_irq(void *param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) enum dma_transfer_direction direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct dma_slave_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int nob = data->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long long clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) host->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) writel(nob, host->base + MMC_NOB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel(data->blksz, host->base + MMC_BLKLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) clks = (unsigned long long)data->timeout_ns * host->clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) do_div(clks, 1000000000UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) writel((timeout + 255) / 256, host->base + MMC_RDTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) memset(&config, 0, sizeof(config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) config.src_addr = host->res->start + MMC_RXFIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) config.dst_addr = host->res->start + MMC_TXFIFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) config.src_maxburst = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) config.dst_maxburst = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (data->flags & MMC_DATA_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) host->dma_dir = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) chan = host->dma_chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) host->dma_dir = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) chan = host->dma_chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) config.direction = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = dmaengine_slave_config(chan, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_err(mmc_dev(host->mmc), "dma slave config failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) host->dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) host->dma_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) tx = dmaengine_prep_slave_sg(chan, data->sg, host->dma_len, direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) DMA_PREP_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!(data->flags & MMC_DATA_READ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) tx->callback = pxamci_dma_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tx->callback_param = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) host->dma_cookie = dmaengine_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * workaround for erratum #91:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * only start DMA now if we are doing a read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * otherwise we wait until CMD/RESP has finished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * before starting DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dma_async_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) WARN_ON(host->cmd != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) host->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (cmd->flags & MMC_RSP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) cmdat |= CMDAT_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) switch (RSP_TYPE(mmc_resp_type(cmd))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cmdat |= CMDAT_RESP_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case RSP_TYPE(MMC_RSP_R3):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) cmdat |= CMDAT_RESP_R3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case RSP_TYPE(MMC_RSP_R2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) cmdat |= CMDAT_RESP_R2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) writel(cmd->opcode, host->base + MMC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) writel(cmd->arg >> 16, host->base + MMC_ARGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) writel(cmdat, host->base + MMC_CMDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) writel(host->clkrt, host->base + MMC_CLKRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) writel(START_CLOCK, host->base + MMC_STRPCL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pxamci_enable_irq(host, END_CMD_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct mmc_command *cmd = host->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * Did I mention this is Sick. We always need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * discard the upper 8 bits of the first 16-bit word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) v = readl(host->base + MMC_RES) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 w1 = readl(host->base + MMC_RES) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 w2 = readl(host->base + MMC_RES) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) v = w2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (stat & STAT_TIME_OUT_RESPONSE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * workaround for erratum #42:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Intel PXA27x Family Processor Specification Update Rev 001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * A bogus CRC error can appear if the msb of a 136 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * response is a one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (cpu_is_pxa27x() &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pxamci_disable_irq(host, END_CMD_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (host->data && !cmd->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) pxamci_enable_irq(host, DATA_TRAN_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * workaround for erratum #91, if doing write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * enable DMA late
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dma_async_issue_pending(host->dma_chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pxamci_finish_request(host, host->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct mmc_data *data = host->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) chan = host->dma_chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) chan = host->dma_chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dma_unmap_sg(chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) data->sg, data->sg_len, host->dma_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (stat & STAT_READ_TIME_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) data->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * There appears to be a hardware design bug here. There seems to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * be no way to find out how much data was transferred to the card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * This means that if there was an error on any block, we mark all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * data blocks as being in error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (!data->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) data->bytes_xfered = data->blocks * data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) data->bytes_xfered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pxamci_disable_irq(host, DATA_TRAN_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (host->mrq->stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pxamci_stop_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pxamci_start_cmd(host, host->mrq->stop, host->cmdat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pxamci_finish_request(host, host->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static irqreturn_t pxamci_irq(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct pxamci_host *host = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned int ireg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ireg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned stat = readl(host->base + MMC_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ireg & END_CMD_RES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) handled |= pxamci_cmd_done(host, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ireg & DATA_TRAN_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) handled |= pxamci_data_done(host, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ireg & SDIO_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mmc_signal_sdio_irq(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct pxamci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned int cmdat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) WARN_ON(host->mrq != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) host->mrq = mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pxamci_stop_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) cmdat = host->cmdat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) host->cmdat &= ~CMDAT_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (mrq->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pxamci_setup_data(host, mrq->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) cmdat &= ~CMDAT_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (mrq->data->flags & MMC_DATA_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cmdat |= CMDAT_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pxamci_start_cmd(host, mrq->cmd, cmdat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int pxamci_get_ro(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct pxamci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (host->use_ro_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return mmc_gpio_get_ro(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (host->pdata && host->pdata->get_ro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return !!host->pdata->get_ro(mmc_dev(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * Board doesn't support read only detection; let the mmc core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * decide what to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct pxamci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ios->clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned long rate = host->clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned int clk = rate / ios->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (host->clkrt == CLKRT_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) clk_prepare_enable(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (ios->clock == 26000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* to support 26MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) host->clkrt = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* to handle (19.5MHz, 26MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) clk = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * clk might result in a lower divisor than we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * desire. check for that condition and adjust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * as appropriate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (rate / clk > ios->clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) clk <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) host->clkrt = fls(clk) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * we write clkrt on the next command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pxamci_stop_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (host->clkrt != CLKRT_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) host->clkrt = CLKRT_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) clk_disable_unprepare(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (host->power_mode != ios->power_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) host->power_mode = ios->power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = pxamci_set_power(host, ios->power_mode, ios->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_err(mmc_dev(mmc), "unable to set power\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * The .set_ios() function in the mmc_host_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * struct return void, and failing to set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * power should be rare so we print an error and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * return here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ios->power_mode == MMC_POWER_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) host->cmdat |= CMDAT_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (ios->bus_width == MMC_BUS_WIDTH_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) host->cmdat |= CMDAT_SD_4DAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) host->cmdat &= ~CMDAT_SD_4DAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_dbg(mmc_dev(mmc), "PXAMCI: clkrt = %x cmdat = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) host->clkrt, host->cmdat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct pxamci_host *pxa_host = mmc_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pxamci_enable_irq(pxa_host, SDIO_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pxamci_disable_irq(pxa_host, SDIO_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct mmc_host_ops pxamci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .request = pxamci_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .get_cd = mmc_gpio_get_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .get_ro = pxamci_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .set_ios = pxamci_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .enable_sdio_irq = pxamci_enable_sdio_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static void pxamci_dma_irq(void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct pxamci_host *host = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct dma_tx_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (!host->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (host->data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) chan = host->dma_chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) chan = host->dma_chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) status = dmaengine_tx_status(chan, host->dma_cookie, &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (likely(status == DMA_COMPLETE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) writel(BUF_PART_FULL, host->base + MMC_PRTBUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pr_err("%s: DMA error on %s channel\n", mmc_hostname(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) host->data->flags & MMC_DATA_READ ? "rx" : "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) host->data->error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pxamci_data_done(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static irqreturn_t pxamci_detect_irq(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct pxamci_host *host = mmc_priv(devid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mmc_detect_change(devid, msecs_to_jiffies(host->detect_delay_ms));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static const struct of_device_id pxa_mmc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { .compatible = "marvell,pxa-mmc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) MODULE_DEVICE_TABLE(of, pxa_mmc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int pxamci_of_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct pxamci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* pxa-mmc specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (of_property_read_u32(np, "pxa-mmc,detect-delay-ms", &tmp) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) host->detect_delay_ms = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ret = mmc_of_parse(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int pxamci_of_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int pxamci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct pxamci_host *host = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mmc = mmc_alloc_host(sizeof(struct pxamci_host), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (!mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) mmc->ops = &pxamci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * We can do SG-DMA, but we don't because we never know how much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * data we successfully wrote to the card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) mmc->max_segs = NR_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * Our hardware DMA can handle a maximum of one page per SG entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) mmc->max_seg_size = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * Block length register is only 10 bits before PXA27x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * Block count register is 16 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mmc->max_blk_count = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ret = pxamci_of_init(pdev, mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) host->mmc = mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) host->pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) host->clkrt = CLKRT_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) host->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (IS_ERR(host->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = PTR_ERR(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) host->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) host->clkrate = clk_get_rate(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * Calculate minimum clock rate, rounding up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) mmc->f_min = (host->clkrate + 63) / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ret = pxamci_init_ocr(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) mmc->caps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) host->cmdat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (!cpu_is_pxa25x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) host->cmdat |= CMDAT_SDIO_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (mmc_has_26MHz())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) mmc->caps |= MMC_CAP_MMC_HIGHSPEED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) MMC_CAP_SD_HIGHSPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) spin_lock_init(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) host->res = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) host->imask = MMC_I_MASK_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) host->base = devm_ioremap_resource(dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (IS_ERR(host->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret = PTR_ERR(host->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * Ensure that the host controller is shut down, and setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * with our defaults.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) pxamci_stop_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) writel(0, host->base + MMC_SPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) writel(64, host->base + MMC_RESTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) writel(host->imask, host->base + MMC_I_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ret = devm_request_irq(dev, irq, pxamci_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) DRIVER_NAME, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) platform_set_drvdata(pdev, mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) host->dma_chan_rx = dma_request_chan(dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (IS_ERR(host->dma_chan_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_err(dev, "unable to request rx dma channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = PTR_ERR(host->dma_chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) host->dma_chan_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) host->dma_chan_tx = dma_request_chan(dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (IS_ERR(host->dma_chan_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev_err(dev, "unable to request tx dma channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = PTR_ERR(host->dma_chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) host->dma_chan_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (host->pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) host->detect_delay_ms = host->pdata->detect_delay_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) host->power = devm_gpiod_get_optional(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (IS_ERR(host->power)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ret = PTR_ERR(host->power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_err(dev, "Failed requesting gpio_power\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* FIXME: should we pass detection delay to debounce? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (ret && ret != -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_err(dev, "Failed requesting gpio_cd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (!host->pdata->gpio_card_ro_invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (ret && ret != -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev_err(dev, "Failed requesting gpio_ro\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) host->use_ro_gpio = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (host->pdata->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) host->pdata->init(dev, pxamci_detect_irq, mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (host->power && host->pdata->setpower)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_warn(dev, "gpio_power and setpower() both defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (host->use_ro_gpio && host->pdata->get_ro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_warn(dev, "gpio_ro and get_ro() both defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (host) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (host->dma_chan_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dma_release_channel(host->dma_chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (host->dma_chan_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dma_release_channel(host->dma_chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int pxamci_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct mmc_host *mmc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct pxamci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mmc_remove_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (host->pdata && host->pdata->exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) host->pdata->exit(&pdev->dev, mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pxamci_stop_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) host->base + MMC_I_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dmaengine_terminate_all(host->dma_chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dmaengine_terminate_all(host->dma_chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) dma_release_channel(host->dma_chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dma_release_channel(host->dma_chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static struct platform_driver pxamci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .probe = pxamci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .remove = pxamci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .of_match_table = of_match_ptr(pxa_mmc_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) module_platform_driver(pxamci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) MODULE_ALIAS("platform:pxa2xx-mci");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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