^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * drivers/mmc/host/omap_hsmmc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Driver for OMAP2430/3430 MMC controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2007 Texas Instruments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Syed Mohammed Khasim <x0khasim@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Madhusudhan <madhu.cr@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Mohit Jalori <mjalori@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This file is licensed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * version 2. This program is licensed "as is" without any warranty of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/mmc/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/pm_wakeirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/platform_data/hsmmc-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* OMAP HSMMC Host Controller Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP_HSMMC_SYSSTATUS 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP_HSMMC_CON 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP_HSMMC_SDMASA 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP_HSMMC_BLK 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP_HSMMC_ARG 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP_HSMMC_CMD 0x010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP_HSMMC_RSP10 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP_HSMMC_RSP32 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP_HSMMC_RSP54 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OMAP_HSMMC_RSP76 0x011C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP_HSMMC_DATA 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP_HSMMC_PSTATE 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP_HSMMC_HCTL 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP_HSMMC_SYSCTL 0x012C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP_HSMMC_STAT 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP_HSMMC_IE 0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP_HSMMC_ISE 0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP_HSMMC_AC12 0x013C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP_HSMMC_CAPA 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VS18 (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VS30 (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HSS (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SDVS18 (0x5 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SDVS30 (0x6 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SDVS33 (0x7 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SDVS_MASK 0x00000E00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SDVSCLR 0xFFFFF1FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SDVSDET 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AUTOIDLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SDBP (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DTO 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ICE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ICS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CEN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLKD_MASK 0x0000FFC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLKD_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DTO_MASK 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DTO_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define INIT_STREAM (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ACEN_ACMD23 (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DP_SELECT (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DDIR (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DMAE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MSBS (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BCE (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define FOUR_BIT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HSPE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IWE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DDR (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLKEXTFREE (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CTPL (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DW8 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OD 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define STAT_CLEAR 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define INIT_STREAM_CMD 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DUAL_VOLT_OCR_BIT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SRC (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SRD (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SOFTRESET (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* PSTATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DLEV_DAT(x) (1 << (20 + (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Interrupt masks for IE and ISE register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CC_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TC_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BWR_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BRR_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CIRQ_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ERR_EN (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CTO_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CCRC_EN (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CEB_EN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CIE_EN (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DTO_EN (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DCRC_EN (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DEB_EN (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ACE_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CERR_EN (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BADA_EN (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) BRR_EN | BWR_EN | TC_EN | CC_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CNI (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ACIE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ACEB (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ACCE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ACTO (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ACNE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MMC_AUTOSUSPEND_DELAY 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MMC_TIMEOUT_MS 20 /* 20 mSec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP_MMC_MIN_CLOCK 400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OMAP_MMC_MAX_CLOCK 52000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DRIVER_NAME "omap_hsmmc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * One controller can have multiple slots, like on some omap boards using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * omap.c controller driver. Luckily this is not currently done on any known
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * omap_hsmmc.c device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define mmc_pdata(host) host->pdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * MMC Host controller read/write API's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OMAP_HSMMC_READ(base, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) __raw_readl((base) + OMAP_HSMMC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OMAP_HSMMC_WRITE(base, reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) __raw_writel((val), (base) + OMAP_HSMMC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct omap_hsmmc_next {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) s32 cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct omap_hsmmc_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct mmc_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct clk *fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct clk *dbclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct regulator *pbias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bool pbias_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int vqmmc_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) resource_size_t mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) spinlock_t irq_lock; /* Prevent races with irq handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned int dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int dma_sg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned char bus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned char power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 hctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 sysctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 capa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int wake_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int use_dma, dma_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct dma_chan *tx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct dma_chan *rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int response_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int context_loss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int reqs_blocked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int req_in_progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct omap_hsmmc_next next_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct omap_hsmmc_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct omap_mmc_of_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 controller_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct omap_hsmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct mmc_ios *ios = &mmc->ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!IS_ERR(mmc->supply.vmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Enable interface voltage rail, if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = regulator_enable(mmc->supply.vqmmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto err_vqmmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) host->vqmmc_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) err_vqmmc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!IS_ERR(mmc->supply.vmmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct omap_hsmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = regulator_disable(mmc->supply.vqmmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) host->vqmmc_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!IS_ERR(mmc->supply.vmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) goto err_set_ocr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) err_set_ocr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!IS_ERR(mmc->supply.vqmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) status = regulator_enable(mmc->supply.vqmmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (IS_ERR(host->pbias))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (power_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (host->pbias_enabled == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = regulator_enable(host->pbias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev_err(host->dev, "pbias reg enable fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) host->pbias_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (host->pbias_enabled == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = regulator_disable(host->pbias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_err(host->dev, "pbias reg disable fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) host->pbias_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * If we don't see a Vcc regulator, assume it's a fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * voltage always-on regulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (IS_ERR(mmc->supply.vmmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = omap_hsmmc_set_pbias(host, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Assume Vcc regulator is used only to power the card ... OMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * VDDS is used to power the pins, optionally with a transceiver to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * support cards using voltages other than VDDS (1.8V nominal). When a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * transceiver is used, DAT3..7 are muxed as transceiver control pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * In some cases this regulator won't support enable/disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * e.g. it's a fixed rail for a WLAN chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * In other cases vcc_aux switches interface power. Example, for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * chips/cards need an interface voltage rail too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (power_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = omap_hsmmc_enable_supply(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = omap_hsmmc_set_pbias(host, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) goto err_set_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = omap_hsmmc_disable_supply(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) err_set_voltage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) omap_hsmmc_disable_supply(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (regulator_is_enabled(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = regulator_enable(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ret = regulator_disable(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * disable regulators enabled during boot and get the usecount
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * right so that regulators can be enabled/disabled by checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * the return value of regulator_is_enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(host->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "fail to disable boot enabled vmmc_aux reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = omap_hsmmc_disable_boot_regulator(host->pbias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_err(host->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) "failed to disable boot enabled pbias reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = mmc_regulator_get_supply(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Allow an aux regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (IS_ERR(mmc->supply.vqmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mmc->supply.vqmmc = devm_regulator_get_optional(host->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "vmmc_aux");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (IS_ERR(mmc->supply.vqmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ret = PTR_ERR(mmc->supply.vqmmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if ((ret != -ENODEV) && host->dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PTR_ERR(mmc->supply.vqmmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) host->pbias = devm_regulator_get_optional(host->dev, "pbias");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (IS_ERR(host->pbias)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = PTR_ERR(host->pbias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if ((ret != -ENODEV) && host->dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_err(host->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PTR_ERR(host->pbias));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* For eMMC do not power off when not in sleep state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (mmc_pdata(host)->no_regulator_off_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = omap_hsmmc_disable_boot_regulators(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * Start clock to the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) OMAP_HSMMC_WRITE(host->base, SYSCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * Stop clock to the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) OMAP_HSMMC_WRITE(host->base, SYSCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u32 irq_mask = INT_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (host->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) irq_mask &= ~(BRR_EN | BWR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Disable timeout for erases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (cmd->opcode == MMC_ERASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) irq_mask &= ~DTO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) spin_lock_irqsave(&host->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* latch pending CIRQ, but don't signal MMC core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) irq_mask |= CIRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) spin_unlock_irqrestore(&host->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 irq_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) spin_lock_irqsave(&host->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* no transfer running but need to keep cirq if enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) irq_mask |= CIRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) spin_unlock_irqrestore(&host->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Calculate divisor for the given clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u16 dsor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ios->clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (dsor > CLKD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dsor = CLKD_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return dsor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct mmc_ios *ios = &host->mmc->ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned long regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned long clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) omap_hsmmc_stop_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) regval = OMAP_HSMMC_READ(host->base, SYSCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) regval = regval & ~(CLKD_MASK | DTO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) clkdiv = calc_divisor(host, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) regval = regval | (clkdiv << 6) | (DTO << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) OMAP_HSMMC_WRITE(host->base, SYSCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* Wait till the ICS bit is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) && time_before(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * Enable High-Speed Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * Pre-Requisites
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * - Controller should support High-Speed-Enable Bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * - Controller should not be using DDR Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * - Controller should advertise that it supports High Speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * in capabilities register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * - MMC/SD clock coming out of controller > 25MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) (ios->timing != MMC_TIMING_MMC_DDR52) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) (ios->timing != MMC_TIMING_UHS_DDR50) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) regval = OMAP_HSMMC_READ(host->base, HCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) regval |= HSPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) regval &= ~HSPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) OMAP_HSMMC_WRITE(host->base, HCTL, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) omap_hsmmc_start_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct mmc_ios *ios = &host->mmc->ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) con = OMAP_HSMMC_READ(host->base, CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (ios->timing == MMC_TIMING_MMC_DDR52 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ios->timing == MMC_TIMING_UHS_DDR50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) con |= DDR; /* configure in DDR mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) con &= ~DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) switch (ios->bus_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) case MMC_BUS_WIDTH_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case MMC_BUS_WIDTH_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) OMAP_HSMMC_WRITE(host->base, HCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case MMC_BUS_WIDTH_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) OMAP_HSMMC_WRITE(host->base, HCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct mmc_ios *ios = &host->mmc->ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u32 con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) con = OMAP_HSMMC_READ(host->base, CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) OMAP_HSMMC_WRITE(host->base, CON, con | OD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * Restore the MMC host context, if it was lost as result of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * power state change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct mmc_ios *ios = &host->mmc->ios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u32 hctl, capa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) host->capa == OMAP_HSMMC_READ(host->base, CAPA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) host->context_loss++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (host->power_mode != MMC_POWER_OFF &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) (1 << ios->vdd) <= MMC_VDD_23_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) hctl = SDVS18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) hctl = SDVS30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) capa = VS30 | VS18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) hctl = SDVS18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) capa = VS18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) hctl |= IWE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) OMAP_HSMMC_WRITE(host->base, HCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) OMAP_HSMMC_READ(host->base, HCTL) | hctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) OMAP_HSMMC_WRITE(host->base, CAPA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) OMAP_HSMMC_READ(host->base, CAPA) | capa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) OMAP_HSMMC_WRITE(host->base, HCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) && time_before(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) OMAP_HSMMC_WRITE(host->base, ISE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) OMAP_HSMMC_WRITE(host->base, IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Do not initialize card-specific things if the power is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (host->power_mode == MMC_POWER_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) omap_hsmmc_set_bus_width(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) omap_hsmmc_set_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) omap_hsmmc_set_bus_mode(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) host->context_loss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * Save the MMC host context (store the number of power state changes so far).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) host->con = OMAP_HSMMC_READ(host->base, CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) host->capa = OMAP_HSMMC_READ(host->base, CAPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * Send init stream sequence to card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * before sending IDLE command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static void send_init_stream(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) disable_irq(host->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) OMAP_HSMMC_WRITE(host->base, CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) while ((reg != CC_EN) && time_before(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) OMAP_HSMMC_WRITE(host->base, CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) OMAP_HSMMC_READ(host->base, STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) enable_irq(host->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct omap_hsmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return sprintf(buf, "%s\n", mmc_pdata(host)->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * Configure the response type and send the cmd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int cmdreg = 0, resptype = 0, cmdtype = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) host->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) omap_hsmmc_enable_irq(host, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) host->response_busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (cmd->flags & MMC_RSP_136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) resptype = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) else if (cmd->flags & MMC_RSP_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) resptype = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) host->response_busy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) resptype = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * Unlike OMAP1 controller, the cmdtype does not seem to be based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * a val of 0x3, rest 0x0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (cmd == host->mrq->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) cmdtype = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) host->mrq->sbc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) cmdreg |= ACEN_ACMD23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) cmdreg |= DP_SELECT | MSBS | BCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) cmdreg |= DDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) cmdreg &= ~(DDIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (host->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) cmdreg |= DMAE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) host->req_in_progress = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int dma_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) spin_lock_irqsave(&host->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) host->req_in_progress = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dma_ch = host->dma_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) spin_unlock_irqrestore(&host->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) omap_hsmmc_disable_irq(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* Do not complete the request if DMA is still in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (mrq->data && host->use_dma && dma_ch != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * Notify the transfer complete to MMC core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct mmc_request *mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* TC before CC from CMD6 - don't know why, but it happens */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (host->cmd && host->cmd->opcode == 6 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) host->response_busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) host->response_busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) omap_hsmmc_request_done(host, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (!data->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) data->bytes_xfered += data->blocks * (data->blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) data->bytes_xfered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (data->stop && (data->error || !host->mrq->sbc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) omap_hsmmc_start_command(host, data->stop, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) omap_hsmmc_request_done(host, data->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * Notify the core about command completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) omap_hsmmc_start_dma_transfer(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) omap_hsmmc_start_command(host, host->mrq->cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) host->mrq->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* response type 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* response types 1, 1b, 3, 4, 5, 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if ((host->data == NULL && !host->response_busy) || cmd->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) omap_hsmmc_request_done(host, host->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * DMA clean up for command errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) int dma_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) host->data->error = errno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) spin_lock_irqsave(&host->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dma_ch = host->dma_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) host->dma_ch = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) spin_unlock_irqrestore(&host->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (host->use_dma && dma_ch != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dmaengine_terminate_all(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dma_unmap_sg(chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) host->data->sg, host->data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) mmc_get_dma_dir(host->data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) host->data->host_cookie = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * Readable error output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #ifdef CONFIG_MMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* --- means reserved bit without definition at documentation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static const char *omap_hsmmc_status_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) char res[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) char *buf = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) int len, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) len = sprintf(buf, "MMC IRQ 0x%x :", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) buf += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (status & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) buf += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #endif /* CONFIG_MMC_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * MMC controller internal state machines reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * Used to reset command or data internal state machines, using respectively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * SRC or SRD bit of SYSCTL register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * Can be called from interrupt context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) unsigned long bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) unsigned long i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) unsigned long limit = MMC_TIMEOUT_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) OMAP_HSMMC_WRITE(host->base, SYSCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * OMAP4 ES2 and greater has an updated reset logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * Monitor a 0->1 transition first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) && (i++ < limit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) (i++ < limit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) "Timeout waiting on controller reset in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) int err, int end_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (end_cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) omap_hsmmc_reset_controller_fsm(host, SRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (host->cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) host->cmd->error = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (host->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) omap_hsmmc_reset_controller_fsm(host, SRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) omap_hsmmc_dma_cleanup(host, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) } else if (host->mrq && host->mrq->cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) host->mrq->cmd->error = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) int end_cmd = 0, end_trans = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) data = host->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (status & ERR_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) omap_hsmmc_dbg_report_irq(host, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (status & (CTO_EN | CCRC_EN | CEB_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) end_cmd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (host->data || host->response_busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) end_trans = !end_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) host->response_busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (status & (CTO_EN | DTO_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) BADA_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (status & ACE_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) u32 ac12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ac12 = OMAP_HSMMC_READ(host->base, AC12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (!(ac12 & ACNE) && host->mrq->sbc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) end_cmd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (ac12 & ACTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) else if (ac12 & (ACCE | ACEB | ACIE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) host->mrq->sbc->error = error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) hsmmc_command_incomplete(host, error, end_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) OMAP_HSMMC_WRITE(host->base, STAT, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (end_cmd || ((status & CC_EN) && host->cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) omap_hsmmc_cmd_done(host, host->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if ((end_trans || (status & TC_EN)) && host->mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) omap_hsmmc_xfer_done(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * MMC controller IRQ handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct omap_hsmmc_host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) status = OMAP_HSMMC_READ(host->base, STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) while (status & (INT_EN_MASK | CIRQ_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (host->req_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) omap_hsmmc_do_irq(host, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (status & CIRQ_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) mmc_signal_sdio_irq(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /* Flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) status = OMAP_HSMMC_READ(host->base, STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static void set_sd_bus_power(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) unsigned long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) OMAP_HSMMC_WRITE(host->base, HCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) for (i = 0; i < loops_per_jiffy; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * Switch MMC interface voltage ... only relevant for MMC1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * The MMC2 transceiver controls are used instead of DAT4..DAT7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * Some chips, like eMMC ones, use internal transceivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) u32 reg_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* Disable the clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) clk_disable_unprepare(host->dbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* Turn the power off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ret = omap_hsmmc_set_power(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* Turn the power ON with given VDD 1.8 or 3.0v */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ret = omap_hsmmc_set_power(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) clk_prepare_enable(host->dbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) OMAP_HSMMC_WRITE(host->base, HCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) reg_val = OMAP_HSMMC_READ(host->base, HCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * If a MMC dual voltage card is detected, the set_ios fn calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * this fn with VDD bit set for 1.8V. Upon card removal from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * Cope with a bit of slop in the range ... per data sheets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * but recommended values are 1.71V to 1.89V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * but recommended values are 2.7V to 3.3V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * Board setup code shouldn't permit anything very out-of-range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if ((1 << vdd) <= MMC_VDD_23_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) reg_val |= SDVS18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) reg_val |= SDVS30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) set_sd_bus_power(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static void omap_hsmmc_dma_callback(void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct omap_hsmmc_host *host = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) int req_in_progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) spin_lock_irq(&host->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (host->dma_ch < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) spin_unlock_irq(&host->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) data = host->mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) chan = omap_hsmmc_get_dma_chan(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (!data->host_cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) dma_unmap_sg(chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) req_in_progress = host->req_in_progress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) host->dma_ch = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) spin_unlock_irq(&host->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* If DMA has finished after TC, complete the request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (!req_in_progress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct mmc_request *mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct omap_hsmmc_next *next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) int dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (!next && data->host_cookie &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) data->host_cookie != host->next_data.cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) " host->next_data.cookie %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) __func__, data->host_cookie, host->next_data.cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) data->host_cookie = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* Check if next job is already prepared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (next || data->host_cookie != host->next_data.cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dma_len = host->next_data.dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) host->next_data.dma_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (dma_len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) next->dma_len = dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) host->dma_len = dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * Routine to configure and start DMA for the MMC card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) int ret = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct mmc_data *data = req->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) struct dma_slave_config cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .src_addr = host->mapbase + OMAP_HSMMC_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .src_maxburst = data->blksz / 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .dst_maxburst = data->blksz / 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /* Sanity check: all the SG entries must be aligned by block size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) for (i = 0; i < data->sg_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) struct scatterlist *sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) sgl = data->sg + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (sgl->length % data->blksz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if ((data->blksz % 4) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* REVISIT: The MMC buffer increments only when MSB is written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * Return error for blksz which is non multiple of four.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) BUG_ON(host->dma_ch != -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) chan = omap_hsmmc_get_dma_chan(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) ret = dmaengine_slave_config(chan, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (!tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /* FIXME: cleanup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) tx->callback = omap_hsmmc_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) tx->callback_param = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /* Does not fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) dmaengine_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) host->dma_ch = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static void set_data_timeout(struct omap_hsmmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) unsigned long long timeout_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) unsigned int timeout_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) unsigned long long timeout = timeout_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) unsigned int cycle_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) uint32_t reg, clkd, dto = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) reg = OMAP_HSMMC_READ(host->base, SYSCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (clkd == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) clkd = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) cycle_ns = 1000000000 / (host->clk_rate / clkd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) do_div(timeout, cycle_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) timeout += timeout_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) while ((timeout & 0x80000000) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) dto += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) timeout <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) dto = 31 - dto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) timeout <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (timeout && dto)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) dto += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (dto >= 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) dto -= 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) dto = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (dto > 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dto = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) reg &= ~DTO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) reg |= dto << DTO_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) struct mmc_request *req = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (!req->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) | (req->data->blocks << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) set_data_timeout(host, req->data->timeout_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) req->data->timeout_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) chan = omap_hsmmc_get_dma_chan(host, req->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) dma_async_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * Configure block length for MMC/SD cards and initiate the transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) unsigned long long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) host->data = req->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (req->data == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) OMAP_HSMMC_WRITE(host->base, BLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (req->cmd->flags & MMC_RSP_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) timeout = req->cmd->busy_timeout * NSEC_PER_MSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * Set an arbitrary 100ms data timeout for commands with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * busy signal and no indication of busy_timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) timeout = 100000000U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) set_data_timeout(host, timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (host->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) ret = omap_hsmmc_setup_dma_transfer(host, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct omap_hsmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct mmc_data *data = mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (host->use_dma && data->host_cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) data->host_cookie = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct omap_hsmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (mrq->data->host_cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) mrq->data->host_cookie = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (host->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) &host->next_data, c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) mrq->data->host_cookie = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * Request function. for read/write operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) struct omap_hsmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) BUG_ON(host->req_in_progress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) BUG_ON(host->dma_ch != -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (host->reqs_blocked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) host->reqs_blocked = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) WARN_ON(host->mrq != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) host->mrq = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) host->clk_rate = clk_get_rate(host->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) err = omap_hsmmc_prepare_data(host, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) req->cmd->error = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (req->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) req->data->error = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) mmc_request_done(mmc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (req->sbc && !(host->flags & AUTO_CMD23)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) omap_hsmmc_start_command(host, req->sbc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) omap_hsmmc_start_dma_transfer(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) omap_hsmmc_start_command(host, req->cmd, req->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /* Routine to configure clock values. Exposed API to core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) struct omap_hsmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) int do_send_init_stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (ios->power_mode != host->power_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) switch (ios->power_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) case MMC_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) omap_hsmmc_set_power(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) case MMC_POWER_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) omap_hsmmc_set_power(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) case MMC_POWER_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) do_send_init_stream = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) host->power_mode = ios->power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* FIXME: set registers based only on changes to ios */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) omap_hsmmc_set_bus_width(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) /* Only MMC1 can interface at 3V without some flavor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) * of external transceiver; but they all handle 1.8V.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) (ios->vdd == DUAL_VOLT_OCR_BIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) * The mmc_select_voltage fn of the core does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * not seem to set the power_mode to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) * MMC_POWER_UP upon recalculating the voltage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) * vdd 1.8v.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) dev_dbg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) "Switch operation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) omap_hsmmc_set_clock(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (do_send_init_stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) send_init_stream(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) omap_hsmmc_set_bus_mode(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct omap_hsmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) if (card->type == MMC_TYPE_SDIO || card->type == MMC_TYPE_SD_COMBO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) struct device_node *np = mmc_dev(mmc)->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) * REVISIT: should be moved to sdio core and made more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) * general e.g. by expanding the DT bindings of child nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * to provide a mechanism to provide this information:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) * Documentation/devicetree/bindings/mmc/mmc-card.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) np = of_get_compatible_child(np, "ti,wl1251");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * We have TI wl1251 attached to MMC3. Pass this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * information to the SDIO core because it can't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * probed by normal methods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) dev_info(host->dev, "found wl1251\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) card->quirks |= MMC_QUIRK_NONSTD_SDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) card->cccr.wide_bus = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) card->cis.vendor = 0x104c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) card->cis.device = 0x9066;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) card->cis.blksize = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) card->cis.max_dtr = 24000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) card->ocr = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) struct omap_hsmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) u32 irq_mask, con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) spin_lock_irqsave(&host->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) con = OMAP_HSMMC_READ(host->base, CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) irq_mask = OMAP_HSMMC_READ(host->base, ISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) host->flags |= HSMMC_SDIO_IRQ_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) irq_mask |= CIRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) con |= CTPL | CLKEXTFREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) irq_mask &= ~CIRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) con &= ~(CTPL | CLKEXTFREE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) OMAP_HSMMC_WRITE(host->base, CON, con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * if enable, piggy back detection on current request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * but always disable immediately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (!host->req_in_progress || !enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /* flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) OMAP_HSMMC_READ(host->base, IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) spin_unlock_irqrestore(&host->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * For omaps with wake-up path, wakeirq will be irq from pinctrl and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * for other omaps, wakeirq will be from GPIO (dat line remuxed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * with functional clock disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (!host->dev->of_node || !host->wake_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) * Some omaps don't have wake-up path from deeper idle states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct pinctrl *p = devm_pinctrl_get(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (IS_ERR(p)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) ret = PTR_ERR(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) dev_info(host->dev, "missing idle pinctrl state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) devm_pinctrl_put(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) devm_pinctrl_put(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) OMAP_HSMMC_WRITE(host->base, HCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) OMAP_HSMMC_READ(host->base, HCTL) | IWE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) dev_pm_clear_wake_irq(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) host->wake_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) u32 hctl, capa, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /* Only MMC1 supports 3.0V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) hctl = SDVS30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) capa = VS30 | VS18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) hctl = SDVS18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) capa = VS18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) value = OMAP_HSMMC_READ(host->base, CAPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /* Set SD bus power bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) set_sd_bus_power(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) unsigned int direction, int blk_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) /* This controller can't do multiblock reads due to hw bugs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (direction == MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return blk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static struct mmc_host_ops omap_hsmmc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .post_req = omap_hsmmc_post_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .pre_req = omap_hsmmc_pre_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .request = omap_hsmmc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .set_ios = omap_hsmmc_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .get_cd = mmc_gpio_get_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .get_ro = mmc_gpio_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .init_card = omap_hsmmc_init_card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static int mmc_regs_show(struct seq_file *s, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) struct mmc_host *mmc = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) struct omap_hsmmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) seq_printf(s, "mmc%d:\n", mmc->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) seq_printf(s, "sdio irq mode\t%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) if (mmc->caps & MMC_CAP_SDIO_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) seq_printf(s, "sdio irq \t%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) pm_runtime_get_sync(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) seq_puts(s, "\nregs:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) seq_printf(s, "CON:\t\t0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) OMAP_HSMMC_READ(host->base, CON));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) seq_printf(s, "PSTATE:\t\t0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) OMAP_HSMMC_READ(host->base, PSTATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) seq_printf(s, "HCTL:\t\t0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) OMAP_HSMMC_READ(host->base, HCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) seq_printf(s, "SYSCTL:\t\t0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) OMAP_HSMMC_READ(host->base, SYSCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) seq_printf(s, "IE:\t\t0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) OMAP_HSMMC_READ(host->base, IE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) seq_printf(s, "ISE:\t\t0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) OMAP_HSMMC_READ(host->base, ISE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) seq_printf(s, "CAPA:\t\t0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) OMAP_HSMMC_READ(host->base, CAPA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) pm_runtime_mark_last_busy(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) pm_runtime_put_autosuspend(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) DEFINE_SHOW_ATTRIBUTE(mmc_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static void omap_hsmmc_debugfs(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (mmc->debugfs_root)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) mmc, &mmc_regs_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) static void omap_hsmmc_debugfs(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) /* See 35xx errata 2.1.1.128 in SPRZ278F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) static const struct omap_mmc_of_data omap4_mmc_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .reg_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static const struct omap_mmc_of_data am33xx_mmc_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .reg_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static const struct of_device_id omap_mmc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .compatible = "ti,omap2-hsmmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .compatible = "ti,omap3-pre-es3-hsmmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .data = &omap3_pre_es3_mmc_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .compatible = "ti,omap3-hsmmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .compatible = "ti,omap4-hsmmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .data = &omap4_mmc_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .compatible = "ti,am33xx-hsmmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .data = &am33xx_mmc_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) struct omap_hsmmc_platform_data *pdata, *legacy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) return ERR_PTR(-ENOMEM); /* out of memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) legacy = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (legacy && legacy->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) pdata->name = legacy->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) if (of_find_property(np, "ti,dual-volt", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) if (of_find_property(np, "ti,non-removable", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) pdata->nonremovable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) pdata->no_regulator_off_init = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (of_find_property(np, "ti,needs-special-reset", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) pdata->features |= HSMMC_HAS_UPDATED_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) static inline struct omap_hsmmc_platform_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) *of_get_hsmmc_pdata(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) static int omap_hsmmc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) struct omap_hsmmc_host *host = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) const struct omap_mmc_of_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) pdata = of_get_hsmmc_pdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (IS_ERR(pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) return PTR_ERR(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (match->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) pdata->reg_offset = data->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) pdata->controller_flags |= data->controller_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) if (pdata == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) dev_err(&pdev->dev, "Platform Data is missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (res == NULL || irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if (!mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) ret = mmc_of_parse(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) host->mmc = mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) host->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) host->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) host->use_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) host->dma_ch = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) host->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) host->mapbase = res->start + pdata->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) host->base = base + pdata->reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) host->power_mode = MMC_POWER_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) host->next_data.cookie = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) host->pbias_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) host->vqmmc_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) platform_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) mmc->ops = &omap_hsmmc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) mmc->f_min = OMAP_MMC_MIN_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (pdata->max_freq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) mmc->f_max = pdata->max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) else if (mmc->f_max == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) mmc->f_max = OMAP_MMC_MAX_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) spin_lock_init(&host->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) host->fclk = devm_clk_get(&pdev->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) if (IS_ERR(host->fclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) ret = PTR_ERR(host->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) host->fclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) device_init_wakeup(&pdev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) pm_runtime_enable(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) pm_runtime_get_sync(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) pm_runtime_use_autosuspend(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) omap_hsmmc_context_save(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * MMC can still work without debounce clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (IS_ERR(host->dbclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) host->dbclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) } else if (clk_prepare_enable(host->dbclk) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) host->dbclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) /* Set this to a value that allows allocating an entire descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) * list within a page (zero order allocation). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) mmc->max_segs = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_CMD23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) mmc->caps |= mmc_pdata(host)->caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) if (mmc->caps & MMC_CAP_8_BIT_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) mmc->caps |= MMC_CAP_4_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (mmc_pdata(host)->nonremovable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) mmc->caps |= MMC_CAP_NONREMOVABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) mmc->pm_caps |= mmc_pdata(host)->pm_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) omap_hsmmc_conf_bus_power(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) host->rx_chan = dma_request_chan(&pdev->dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) if (IS_ERR(host->rx_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) ret = PTR_ERR(host->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) host->tx_chan = dma_request_chan(&pdev->dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (IS_ERR(host->tx_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) ret = PTR_ERR(host->tx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) * Limit the maximum segment size to the lower of the request size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) * and the DMA engine device segment size limits. In reality, with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) * 32-bit transfers, the DMA engine can do longer segments than this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) * but there is no way to represent that in the DMA model - if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) * increase this figure here, we get warnings from the DMA API debug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) mmc->max_seg_size = min3(mmc->max_req_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) dma_get_max_seg_size(host->rx_chan->device->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) dma_get_max_seg_size(host->tx_chan->device->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) /* Request IRQ for MMC operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) mmc_hostname(mmc), host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) ret = omap_hsmmc_reg_get(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) if (!mmc->ocr_avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) omap_hsmmc_disable_irq(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) * For now, only support SDIO interrupt if we have a separate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) * wake-up interrupt configured from device tree. This is because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) * the wake-up interrupt is needed for idle state and some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) * platforms need special quirks. And we don't want to add new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) * legacy mux platform init code callbacks any longer as we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) * are moving to DT based booting anyways.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) ret = omap_hsmmc_configure_wake_irq(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) mmc->caps |= MMC_CAP_SDIO_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) if (mmc_pdata(host)->name != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) goto err_slot_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) omap_hsmmc_debugfs(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) pm_runtime_mark_last_busy(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) pm_runtime_put_autosuspend(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) err_slot_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) mmc_remove_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) device_init_wakeup(&pdev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) if (!IS_ERR_OR_NULL(host->tx_chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) dma_release_channel(host->tx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (!IS_ERR_OR_NULL(host->rx_chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) dma_release_channel(host->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) pm_runtime_dont_use_autosuspend(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) pm_runtime_put_sync(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) pm_runtime_disable(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) clk_disable_unprepare(host->dbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static int omap_hsmmc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) pm_runtime_get_sync(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) mmc_remove_host(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) dma_release_channel(host->tx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) dma_release_channel(host->rx_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) dev_pm_clear_wake_irq(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) pm_runtime_dont_use_autosuspend(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) pm_runtime_put_sync(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) pm_runtime_disable(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) device_init_wakeup(&pdev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) clk_disable_unprepare(host->dbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) mmc_free_host(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) static int omap_hsmmc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) struct omap_hsmmc_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) pm_runtime_get_sync(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) OMAP_HSMMC_WRITE(host->base, ISE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) OMAP_HSMMC_WRITE(host->base, IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) OMAP_HSMMC_WRITE(host->base, HCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) clk_disable_unprepare(host->dbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) pm_runtime_put_sync(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) /* Routine to resume the MMC device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) static int omap_hsmmc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) struct omap_hsmmc_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) pm_runtime_get_sync(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) clk_prepare_enable(host->dbclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) omap_hsmmc_conf_bus_power(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) pm_runtime_mark_last_busy(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) pm_runtime_put_autosuspend(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static int omap_hsmmc_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) struct omap_hsmmc_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) omap_hsmmc_context_save(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) dev_dbg(dev, "disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) spin_lock_irqsave(&host->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) /* disable sdio irq handling to prevent race */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) OMAP_HSMMC_WRITE(host->base, ISE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) OMAP_HSMMC_WRITE(host->base, IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) * dat1 line low, pending sdio irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) * race condition: possible irq handler running on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) * multi-core, abort
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) dev_dbg(dev, "pending sdio irq, abort suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) goto abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) pinctrl_pm_select_idle_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) pinctrl_pm_select_idle_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) abort:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) spin_unlock_irqrestore(&host->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) static int omap_hsmmc_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) struct omap_hsmmc_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) omap_hsmmc_context_restore(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) dev_dbg(dev, "enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) spin_lock_irqsave(&host->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) pinctrl_select_default_state(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) /* irq lost, if pinmux incorrect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) pinctrl_select_default_state(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) spin_unlock_irqrestore(&host->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .runtime_suspend = omap_hsmmc_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .runtime_resume = omap_hsmmc_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) static struct platform_driver omap_hsmmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .probe = omap_hsmmc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .remove = omap_hsmmc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .pm = &omap_hsmmc_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .of_match_table = of_match_ptr(omap_mmc_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) module_platform_driver(omap_hsmmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) MODULE_ALIAS("platform:" DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) MODULE_AUTHOR("Texas Instruments Inc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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