^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/mmc/host/omap.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Other hacks (DMA, SD, etc) by David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mmc/card.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/platform_data/mmc-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP_MMC_REG_CMD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP_MMC_REG_ARGL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP_MMC_REG_ARGH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP_MMC_REG_CON 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP_MMC_REG_STAT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP_MMC_REG_IE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP_MMC_REG_CTO 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP_MMC_REG_DTO 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP_MMC_REG_DATA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP_MMC_REG_BLEN 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP_MMC_REG_NBLK 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP_MMC_REG_BUF 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP_MMC_REG_SDIO 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP_MMC_REG_REV 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP_MMC_REG_RSP0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP_MMC_REG_RSP1 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP_MMC_REG_RSP2 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP_MMC_REG_RSP3 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP_MMC_REG_RSP4 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP_MMC_REG_RSP5 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP_MMC_REG_RSP6 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP_MMC_REG_RSP7 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP_MMC_REG_IOSR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP_MMC_REG_SYSC 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OMAP_MMC_REG_SYSS 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP_MMC_STAT_A_FULL (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP_MMC_STAT_END_BUSY (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define mmc_omap7xx() (host->features & MMC_OMAP7XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define mmc_omap15xx() (host->features & MMC_OMAP15XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define mmc_omap16xx() (host->features & MMC_OMAP16XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define mmc_omap1() (host->features & MMC_OMAP1_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define mmc_omap2() (!mmc_omap1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Command types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP_MMC_CMDTYPE_BC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP_MMC_CMDTYPE_BCR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP_MMC_CMDTYPE_AC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP_MMC_CMDTYPE_ADTC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DRIVER_NAME "mmci-omap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Specifies how often in millisecs to poll for card status changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * when the cover switch is open */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP_MMC_COVER_POLL_DELAY 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct mmc_omap_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct mmc_omap_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 saved_con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u16 bus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int fclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct tasklet_struct cover_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct timer_list cover_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned cover_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct mmc_omap_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct omap_mmc_slot_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct mmc_omap_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct mmc_request * mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct mmc_command * cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct mmc_data * data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct mmc_host * mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct device * dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned char id; /* 16xx chips have 2 MMC blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct clk * iclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct clk * fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct dma_chan *dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 dma_rx_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct dma_chan *dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 dma_tx_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void __iomem *virt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned char bus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct work_struct cmd_abort_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned abort:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct timer_list cmd_abort_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct work_struct slot_release_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct mmc_omap_slot *next_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct work_struct send_stop_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct mmc_data *stop_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int sg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u16 * buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 buffer_bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 total_bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned brs_received:1, dma_done:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned dma_in_use:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) spinlock_t dma_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct mmc_omap_slot *current_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) spinlock_t slot_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) wait_queue_head_t slot_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int nr_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct timer_list clk_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) spinlock_t clk_lock; /* for changing enabled state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int fclk_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct workqueue_struct *mmc_omap_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct omap_mmc_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long tick_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ndelay(8 * tick_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) spin_lock_irqsave(&host->clk_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (host->fclk_enabled != enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) host->fclk_enabled = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) clk_enable(host->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) clk_disable(host->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) spin_unlock_irqrestore(&host->clk_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct mmc_omap_host *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (claimed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto no_claim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) spin_lock_irqsave(&host->slot_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) while (host->mmc != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) spin_unlock_irqrestore(&host->slot_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) wait_event(host->slot_wq, host->mmc == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) spin_lock_irqsave(&host->slot_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) host->mmc = slot->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) spin_unlock_irqrestore(&host->slot_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) no_claim:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) del_timer(&host->clk_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (host->current_slot != slot || !claimed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mmc_omap_fclk_offdelay(host->current_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (host->current_slot != slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (host->pdata->switch_slot != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) host->current_slot = slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (claimed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mmc_omap_fclk_enable(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Doing the dummy read here seems to work around some bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * at least in OMAP24xx silicon where the command would not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * start after writing the CMD register. Sigh. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) OMAP_MMC_READ(host, CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) OMAP_MMC_WRITE(host, CON, slot->saved_con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mmc_omap_fclk_enable(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void mmc_omap_start_request(struct mmc_omap_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct mmc_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static void mmc_omap_slot_release_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) slot_release_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct mmc_omap_slot *next_slot = host->next_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct mmc_request *rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) host->next_slot = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mmc_omap_select_slot(next_slot, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) rq = next_slot->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) next_slot->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) mmc_omap_start_request(host, rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct mmc_omap_host *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) BUG_ON(slot == NULL || host->mmc == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (clk_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Keeps clock running for at least 8 cycles on valid freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mod_timer(&host->clk_timer, jiffies + HZ/10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) del_timer(&host->clk_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mmc_omap_fclk_offdelay(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mmc_omap_fclk_enable(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) spin_lock_irqsave(&host->slot_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Check for any pending requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) for (i = 0; i < host->nr_slots; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct mmc_omap_slot *new_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) BUG_ON(host->next_slot != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) new_slot = host->slots[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* The current slot should not have a request in queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) BUG_ON(new_slot == host->current_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) host->next_slot = new_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) host->mmc = new_slot->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) spin_unlock_irqrestore(&host->slot_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) queue_work(host->mmc_omap_wq, &host->slot_release_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) host->mmc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) wake_up(&host->slot_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) spin_unlock_irqrestore(&host->slot_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (slot->pdata->get_cover_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) slot->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct mmc_omap_slot *slot = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "closed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct mmc_omap_slot *slot = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return sprintf(buf, "%s\n", slot->pdata->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 cmdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 resptype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 cmdtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u16 irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) host->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) resptype = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) cmdtype = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Our hardware needs to know exact type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) switch (mmc_resp_type(cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case MMC_RSP_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case MMC_RSP_R1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case MMC_RSP_R1B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* resp 1, 1b, 6, 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) resptype = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case MMC_RSP_R2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) resptype = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case MMC_RSP_R3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) resptype = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) cmdtype = OMAP_MMC_CMDTYPE_ADTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) cmdtype = OMAP_MMC_CMDTYPE_BC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) cmdtype = OMAP_MMC_CMDTYPE_BCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) cmdtype = OMAP_MMC_CMDTYPE_AC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) cmdreg |= 1 << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (cmd->flags & MMC_RSP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) cmdreg |= 1 << 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (host->data && !(host->data->flags & MMC_DATA_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) cmdreg |= 1 << 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) OMAP_MMC_WRITE(host, CTO, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) OMAP_MMC_STAT_END_OF_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (cmd->opcode == MMC_ERASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) OMAP_MMC_WRITE(host, IE, irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) OMAP_MMC_WRITE(host, CMD, cmdreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int abort)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) enum dma_data_direction dma_data_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct device *dev = mmc_dev(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct dma_chan *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (data->flags & MMC_DATA_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dma_data_dir = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) c = host->dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dma_data_dir = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) c = host->dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (data->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dmaengine_terminate_all(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Claim nothing transferred on error... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) data->bytes_xfered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev = c->device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static void mmc_omap_send_stop_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) send_stop_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct mmc_omap_slot *slot = host->current_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct mmc_data *data = host->stop_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) unsigned long tick_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ndelay(8*tick_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) mmc_omap_start_command(host, data->stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (host->dma_in_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) mmc_omap_release_dma(host, data, data->error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) host->sg_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * dozens of requests until the card finishes writing data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * It'd be cheaper to just wait till an EOFB interrupt arrives...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!data->stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mmc_omap_release_slot(host->current_slot, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) mmc_request_done(mmc, data->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) host->stop_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) queue_work(host->mmc_omap_wq, &host->send_stop_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct mmc_omap_slot *slot = host->current_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) unsigned int restarts, passes, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u16 stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Sending abort takes 80 clocks. Have some extra and round up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) restarts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) while (restarts < maxloops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) OMAP_MMC_WRITE(host, STAT, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) passes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) while (passes < timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) stat = OMAP_MMC_READ(host, STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (stat & OMAP_MMC_STAT_END_OF_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) passes++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) restarts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) OMAP_MMC_WRITE(host, STAT, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (host->dma_in_use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mmc_omap_release_dma(host, data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) host->sg_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) mmc_omap_send_abort(host, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (!host->dma_in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) mmc_omap_xfer_done(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) spin_lock_irqsave(&host->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (host->dma_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) host->brs_received = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) spin_unlock_irqrestore(&host->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) mmc_omap_xfer_done(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) spin_lock_irqsave(&host->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (host->brs_received)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) host->dma_done = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) spin_unlock_irqrestore(&host->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mmc_omap_xfer_done(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) del_timer(&host->cmd_abort_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* response type 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) cmd->resp[3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) OMAP_MMC_READ(host, RSP0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) (OMAP_MMC_READ(host, RSP1) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) cmd->resp[2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) OMAP_MMC_READ(host, RSP2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) (OMAP_MMC_READ(host, RSP3) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) cmd->resp[1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) OMAP_MMC_READ(host, RSP4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) (OMAP_MMC_READ(host, RSP5) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) cmd->resp[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) OMAP_MMC_READ(host, RSP6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) (OMAP_MMC_READ(host, RSP7) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* response types 1, 1b, 3, 4, 5, 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) cmd->resp[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) OMAP_MMC_READ(host, RSP6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) (OMAP_MMC_READ(host, RSP7) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (host->data == NULL || cmd->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (host->data != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) mmc_omap_abort_xfer(host, host->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) mmc_omap_release_slot(host->current_slot, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) mmc_request_done(mmc, cmd->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * Abort stuck command. Can occur when card is removed while it is being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static void mmc_omap_abort_command(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) cmd_abort_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) BUG_ON(!host->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) host->cmd->opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (host->cmd->error == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) host->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (host->data == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct mmc_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) cmd = host->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mmc_omap_send_abort(host, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) mmc_omap_release_slot(host->current_slot, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mmc_request_done(mmc, cmd->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mmc_omap_cmd_done(host, host->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) host->abort = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) enable_irq(host->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) mmc_omap_cmd_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct mmc_omap_host *host = from_timer(host, t, cmd_abort_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) spin_lock_irqsave(&host->slot_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (host->cmd != NULL && !host->abort) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) OMAP_MMC_WRITE(host, IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) disable_irq(host->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) host->abort = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) spin_unlock_irqrestore(&host->slot_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* PIO only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) mmc_omap_sg_to_buf(struct mmc_omap_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) sg = host->data->sg + host->sg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) host->buffer_bytes_left = sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) host->buffer = sg_virt(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (host->buffer_bytes_left > host->total_bytes_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) host->buffer_bytes_left = host->total_bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) mmc_omap_clk_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct mmc_omap_host *host = from_timer(host, t, clk_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) mmc_omap_fclk_enable(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* PIO only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int n, nwords;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (host->buffer_bytes_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) host->sg_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) BUG_ON(host->sg_idx == host->sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) mmc_omap_sg_to_buf(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) n = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (n > host->buffer_bytes_left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) n = host->buffer_bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Round up to handle odd number of bytes to transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) nwords = DIV_ROUND_UP(n, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) host->buffer_bytes_left -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) host->total_bytes_left -= n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) host->data->bytes_xfered += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) host->buffer, nwords);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) host->buffer, nwords);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) host->buffer += nwords;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #ifdef CONFIG_MMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const char *mmc_omap_status_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) char res[64], *buf = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) buf += sprintf(buf, "MMC IRQ 0x%x:", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (status & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int end_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int end_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int transfer_error, cmd_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (host->cmd == NULL && host->data == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) status = OMAP_MMC_READ(host, STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dev_info(mmc_dev(host->slots[0]->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) "Spurious IRQ 0x%04x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) OMAP_MMC_WRITE(host, STAT, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) OMAP_MMC_WRITE(host, IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) end_command = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) end_transfer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) transfer_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) cmd_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) OMAP_MMC_WRITE(host, STAT, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (host->cmd != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) cmd = host->cmd->opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) cmd = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) status, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mmc_omap_report_irq(host, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (host->total_bytes_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if ((status & OMAP_MMC_STAT_A_FULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) (status & OMAP_MMC_STAT_END_OF_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) mmc_omap_xfer_data(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (status & OMAP_MMC_STAT_A_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) mmc_omap_xfer_data(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (status & OMAP_MMC_STAT_END_OF_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) end_transfer = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (status & OMAP_MMC_STAT_DATA_TOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (host->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) host->data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) transfer_error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (status & OMAP_MMC_STAT_DATA_CRC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (host->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) host->data->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_dbg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "data CRC error, bytes left %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) host->total_bytes_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) transfer_error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (status & OMAP_MMC_STAT_CMD_TOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* Timeouts are routine with some commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (host->cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct mmc_omap_slot *slot =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) host->current_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (slot == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) !mmc_omap_cover_is_open(slot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) "command timeout (CMD%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) host->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) end_command = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) cmd_error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (status & OMAP_MMC_STAT_CMD_CRC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (host->cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) "command CRC error (CMD%d, arg 0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) cmd, host->cmd->arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) host->cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) end_command = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) cmd_error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "command CRC error without cmd?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (status & OMAP_MMC_STAT_CARD_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev_dbg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) "ignoring card status error (CMD%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) end_command = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * NOTE: On 1610 the END_OF_CMD may come too early when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * starting a write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) (!(status & OMAP_MMC_STAT_A_EMPTY))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) end_command = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (cmd_error && host->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) del_timer(&host->cmd_abort_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) host->abort = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) OMAP_MMC_WRITE(host, IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) disable_irq_nosync(host->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (end_command && host->cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) mmc_omap_cmd_done(host, host->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (host->data != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (transfer_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) mmc_omap_xfer_done(host, host->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) else if (end_transfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) mmc_omap_end_of_data(host, host->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) int cover_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct mmc_omap_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct mmc_omap_slot *slot = host->slots[num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) BUG_ON(num >= host->nr_slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* Other subsystems can call in here before we're initialised. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (host->nr_slots == 0 || !host->slots[num])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) cover_open = mmc_omap_cover_is_open(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (cover_open != slot->cover_open) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) slot->cover_open = cover_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) tasklet_hi_schedule(&slot->cover_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static void mmc_omap_cover_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct mmc_omap_slot *slot = from_timer(slot, t, cover_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) tasklet_schedule(&slot->cover_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static void mmc_omap_cover_handler(unsigned long param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int cover_open = mmc_omap_cover_is_open(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) mmc_detect_change(slot->mmc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (!cover_open)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * If no card is inserted, we postpone polling until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * the cover has been closed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (slot->mmc->card == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) mod_timer(&slot->cover_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static void mmc_omap_dma_callback(void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct mmc_omap_host *host = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct mmc_data *data = host->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* If we got to the end of DMA, assume everything went well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) data->bytes_xfered += data->blocks * data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) mmc_omap_dma_done(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) reg = OMAP_MMC_READ(host, SDIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) reg &= ~(1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) OMAP_MMC_WRITE(host, SDIO, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* Set maximum timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) OMAP_MMC_WRITE(host, CTO, 0xfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) unsigned int timeout, cycle_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) cycle_ns = 1000000000 / host->current_slot->fclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) timeout = req->data->timeout_ns / cycle_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) timeout += req->data->timeout_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* Check if we need to use timeout multiplier register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) reg = OMAP_MMC_READ(host, SDIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (timeout > 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) reg |= (1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) timeout /= 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) reg &= ~(1 << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) OMAP_MMC_WRITE(host, SDIO, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) OMAP_MMC_WRITE(host, DTO, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct mmc_data *data = req->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) int i, use_dma = 1, block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) unsigned sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) host->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (data == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) OMAP_MMC_WRITE(host, BLEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) OMAP_MMC_WRITE(host, NBLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) OMAP_MMC_WRITE(host, BUF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) host->dma_in_use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) set_cmd_timeout(host, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) block_size = data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) OMAP_MMC_WRITE(host, BLEN, block_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) set_data_timeout(host, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* cope with calling layer confusion; it issues "single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * block" writes using multi-block scatterlists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) sg_len = (data->blocks == 1) ? 1 : data->sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* Only do DMA for entire blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) for_each_sg(data->sg, sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if ((sg->length % block_size) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) use_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) host->sg_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) enum dma_data_direction dma_data_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct dma_chan *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) u32 burst, *bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) u16 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * and 24xx. Use 16 or 32 word frames when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * blocksize is at least that large. Blocksize is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * usually 512 bytes; but not for some SD reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) burst = mmc_omap15xx() ? 32 : 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (burst > data->blksz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) burst = data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) burst >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (data->flags & MMC_DATA_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) c = host->dma_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) bp = &host->dma_tx_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) buf = 0x0f80 | (burst - 1) << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dma_data_dir = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) c = host->dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) bp = &host->dma_rx_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) buf = 0x800f | (burst - 1) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) dma_data_dir = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (!c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) goto use_pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* Only reconfigure if we have a different burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (*bp != burst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct dma_slave_config cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .src_addr = host->phys_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) OMAP_MMC_REG(host, DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .dst_addr = host->phys_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) OMAP_MMC_REG(host, DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .src_maxburst = burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .dst_maxburst = burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (dmaengine_slave_config(c, &cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) goto use_pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) *bp = burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dma_data_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (host->sg_len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) goto use_pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (!tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) goto use_pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) OMAP_MMC_WRITE(host, BUF, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) tx->callback = mmc_omap_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) tx->callback_param = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) dmaengine_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) host->brs_received = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) host->dma_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) host->dma_in_use = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) use_pio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* Revert to PIO? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) OMAP_MMC_WRITE(host, BUF, 0x1f1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) host->total_bytes_left = data->blocks * block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) host->sg_len = sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) mmc_omap_sg_to_buf(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) host->dma_in_use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static void mmc_omap_start_request(struct mmc_omap_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) BUG_ON(host->mrq != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) host->mrq = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* only touch fifo AFTER the controller readies it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) mmc_omap_prepare_data(host, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) mmc_omap_start_command(host, req->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (host->dma_in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) host->dma_tx : host->dma_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) dma_async_issue_pending(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct mmc_omap_slot *slot = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct mmc_omap_host *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) spin_lock_irqsave(&host->slot_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (host->mmc != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) BUG_ON(slot->mrq != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) slot->mrq = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) spin_unlock_irqrestore(&host->slot_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) host->mmc = mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) spin_unlock_irqrestore(&host->slot_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) mmc_omap_select_slot(slot, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) mmc_omap_start_request(host, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) int vdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct mmc_omap_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (slot->pdata->set_power != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (mmc_omap2()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (power_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) w = OMAP_MMC_READ(host, CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) OMAP_MMC_WRITE(host, CON, w | (1 << 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) w = OMAP_MMC_READ(host, CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct mmc_omap_slot *slot = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct mmc_omap_host *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) int func_clk_rate = clk_get_rate(host->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) int dsor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (ios->clock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) dsor = func_clk_rate / ios->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (dsor < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dsor = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (func_clk_rate / dsor > ios->clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) dsor++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (dsor > 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dsor = 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) slot->fclk_freq = func_clk_rate / dsor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (ios->bus_width == MMC_BUS_WIDTH_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dsor |= 1 << 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return dsor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct mmc_omap_slot *slot = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct mmc_omap_host *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) int i, dsor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) int clk_enabled, init_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) mmc_omap_select_slot(slot, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) dsor = mmc_omap_calc_divisor(mmc, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (ios->vdd != slot->vdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) slot->vdd = ios->vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) clk_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) init_stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) switch (ios->power_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) case MMC_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) mmc_omap_set_power(slot, 0, ios->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) case MMC_POWER_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* Cannot touch dsor yet, just power up MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) mmc_omap_set_power(slot, 1, ios->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) slot->power_mode = ios->power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) case MMC_POWER_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) mmc_omap_fclk_enable(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) clk_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) dsor |= 1 << 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (slot->power_mode != MMC_POWER_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) init_stream = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) slot->power_mode = ios->power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (slot->bus_mode != ios->bus_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (slot->pdata->set_bus_mode != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ios->bus_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) slot->bus_mode = ios->bus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /* On insanely high arm_per frequencies something sometimes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * goes somehow out of sync, and the POW bit is not being set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * which results in the while loop below getting stuck.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * Writing to the CON register twice seems to do the trick. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) for (i = 0; i < 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) OMAP_MMC_WRITE(host, CON, dsor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) slot->saved_con = dsor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (init_stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* worst case at 400kHz, 80 cycles makes 200 microsecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) int usecs = 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* Send clock cycles, poll completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) OMAP_MMC_WRITE(host, IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) OMAP_MMC_WRITE(host, STAT, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) OMAP_MMC_WRITE(host, CMD, 1 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) usecs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) OMAP_MMC_WRITE(host, STAT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) mmc_omap_release_slot(slot, clk_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static const struct mmc_host_ops mmc_omap_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .request = mmc_omap_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .set_ios = mmc_omap_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct mmc_omap_slot *slot = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (mmc == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) slot = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) slot->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) slot->mmc = mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) slot->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) slot->power_mode = MMC_POWER_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) slot->pdata = &host->pdata->slots[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) host->slots[id] = slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) mmc->caps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (host->pdata->slots[id].wires >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) mmc->caps |= MMC_CAP_4_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) mmc->ops = &mmc_omap_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) mmc->f_min = 400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (mmc_omap2())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) mmc->f_max = 48000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) mmc->f_max = 24000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (host->pdata->max_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) mmc->ocr_avail = slot->pdata->ocr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /* Use scatterlist DMA to reduce per-transfer costs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * NOTE max_seg_size assumption that small blocks aren't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * normally used (except e.g. for reading SD registers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) mmc->max_segs = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) mmc->max_seg_size = mmc->max_req_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (slot->pdata->get_cover_state != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) timer_setup(&slot->cover_timer, mmc_omap_cover_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) (unsigned long)slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) r = mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) goto err_remove_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (slot->pdata->name != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) r = device_create_file(&mmc->class_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) &dev_attr_slot_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) goto err_remove_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (slot->pdata->get_cover_state != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) r = device_create_file(&mmc->class_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) &dev_attr_cover_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) goto err_remove_slot_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) tasklet_schedule(&slot->cover_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) err_remove_slot_name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (slot->pdata->name != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) err_remove_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) mmc_remove_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct mmc_host *mmc = slot->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (slot->pdata->name != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (slot->pdata->get_cover_state != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) tasklet_kill(&slot->cover_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) del_timer_sync(&slot->cover_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) flush_workqueue(slot->host->mmc_omap_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) mmc_remove_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static int mmc_omap_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) struct mmc_omap_host *host = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (pdata == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dev_err(&pdev->dev, "platform data missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (pdata->nr_slots == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) dev_err(&pdev->dev, "no slots\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (host == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) host->virt_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (IS_ERR(host->virt_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return PTR_ERR(host->virt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) timer_setup(&host->cmd_abort_timer, mmc_omap_cmd_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) spin_lock_init(&host->clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) timer_setup(&host->clk_timer, mmc_omap_clk_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) spin_lock_init(&host->dma_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) spin_lock_init(&host->slot_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) init_waitqueue_head(&host->slot_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) host->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) host->features = host->pdata->slots[0].features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) host->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) platform_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) host->id = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) host->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) host->phys_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) host->iclk = clk_get(&pdev->dev, "ick");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (IS_ERR(host->iclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return PTR_ERR(host->iclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) clk_enable(host->iclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) host->fclk = clk_get(&pdev->dev, "fck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (IS_ERR(host->fclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ret = PTR_ERR(host->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) goto err_free_iclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) host->dma_tx_burst = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) host->dma_rx_burst = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) host->dma_tx = dma_request_chan(&pdev->dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (IS_ERR(host->dma_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ret = PTR_ERR(host->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (ret == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) clk_put(host->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) goto err_free_iclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) host->dma_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) dev_warn(host->dev, "TX DMA channel request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) host->dma_rx = dma_request_chan(&pdev->dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (IS_ERR(host->dma_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) ret = PTR_ERR(host->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (ret == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (host->dma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dma_release_channel(host->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) clk_put(host->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) goto err_free_iclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) host->dma_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) dev_warn(host->dev, "RX DMA channel request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) goto err_free_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (pdata->init != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ret = pdata->init(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) host->nr_slots = pdata->nr_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) host->reg_shift = (mmc_omap7xx() ? 1 : 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (!host->mmc_omap_wq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) goto err_plat_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) for (i = 0; i < pdata->nr_slots; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ret = mmc_omap_new_slot(host, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) mmc_omap_remove_slot(host->slots[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) goto err_destroy_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) err_destroy_wq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) destroy_workqueue(host->mmc_omap_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) err_plat_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (pdata->cleanup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) pdata->cleanup(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) free_irq(host->irq, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) err_free_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (host->dma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) dma_release_channel(host->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (host->dma_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) dma_release_channel(host->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) clk_put(host->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) err_free_iclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) clk_disable(host->iclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) clk_put(host->iclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static int mmc_omap_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) struct mmc_omap_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) BUG_ON(host == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) for (i = 0; i < host->nr_slots; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) mmc_omap_remove_slot(host->slots[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (host->pdata->cleanup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) host->pdata->cleanup(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) mmc_omap_fclk_enable(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) free_irq(host->irq, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) clk_put(host->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) clk_disable(host->iclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) clk_put(host->iclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (host->dma_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) dma_release_channel(host->dma_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (host->dma_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) dma_release_channel(host->dma_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) destroy_workqueue(host->mmc_omap_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) #if IS_BUILTIN(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static const struct of_device_id mmc_omap_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) { .compatible = "ti,omap2420-mmc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) MODULE_DEVICE_TABLE(of, mmc_omap_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static struct platform_driver mmc_omap_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .probe = mmc_omap_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .remove = mmc_omap_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .of_match_table = of_match_ptr(mmc_omap_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) module_platform_driver(mmc_omap_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) MODULE_DESCRIPTION("OMAP Multimedia Card driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) MODULE_ALIAS("platform:" DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) MODULE_AUTHOR("Juha Yrjölä");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags