^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This is a driver for the SDHC controller found in Freescale MX2/MX3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Unlike the hardware found on MX1, this hardware just works and does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * not need all the quirks found in imxmmc.c, hence the separate driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * derived from pxamci.c by Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mmc/card.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/platform_data/mmc-mxcmmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/platform_data/dma-imx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRIVER_NAME "mxc-mmc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MXCMCI_TIMEOUT_MS 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MMC_REG_STR_STP_CLK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MMC_REG_STATUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MMC_REG_CLK_RATE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MMC_REG_CMD_DAT_CONT 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MMC_REG_RES_TO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MMC_REG_READ_TO 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MMC_REG_BLK_LEN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MMC_REG_NOB 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MMC_REG_REV_NO 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MMC_REG_INT_CNTR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MMC_REG_CMD 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MMC_REG_ARG 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MMC_REG_RES_FIFO 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MMC_REG_BUFFER_ACCESS 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STR_STP_CLK_RESET (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define STR_STP_CLK_START_CLK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define STR_STP_CLK_STOP_CLK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define STATUS_CARD_INSERTION (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define STATUS_CARD_REMOVAL (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define STATUS_YBUF_EMPTY (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define STATUS_XBUF_EMPTY (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define STATUS_YBUF_FULL (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define STATUS_XBUF_FULL (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define STATUS_BUF_UND_RUN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define STATUS_BUF_OVFL (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define STATUS_SDIO_INT_ACTIVE (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define STATUS_END_CMD_RESP (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define STATUS_WRITE_OP_DONE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define STATUS_DATA_TRANS_DONE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define STATUS_READ_OP_DONE (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define STATUS_BUF_READ_RDY (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define STATUS_BUF_WRITE_RDY (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define STATUS_RESP_CRC_ERR (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define STATUS_CRC_READ_ERR (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define STATUS_CRC_WRITE_ERR (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define STATUS_TIME_OUT_RESP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define STATUS_TIME_OUT_READ (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define STATUS_ERR_MASK 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CMD_DAT_CONT_START_READWAIT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CMD_DAT_CONT_INIT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CMD_DAT_CONT_WRITE (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define INT_SDIO_INT_WKP_EN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define INT_CARD_INSERTION_WKP_EN (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define INT_CARD_INSERTION_EN (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define INT_CARD_REMOVAL_EN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define INT_SDIO_IRQ_EN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define INT_DAT0_EN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define INT_BUF_READ_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define INT_BUF_WRITE_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define INT_END_CMD_RES_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define INT_WRITE_OP_DONE_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define INT_READ_OP_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) enum mxcmci_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) IMX21_MMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) IMX31_MMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MPC512X_MMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct mxcmci_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dma_addr_t phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int detect_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct dma_chan *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int do_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int default_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int use_sdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct imxmmc_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct mmc_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct mmc_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int datasize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int dma_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u16 rev_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int cmdat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct clk *clk_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct work_struct datawork;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int burstlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int dmareq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct dma_slave_config dma_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct imx_dma_data dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct timer_list watchdog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) enum mxcmci_type devtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct platform_device_id mxcmci_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .name = "imx21-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .driver_data = IMX21_MMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "imx31-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .driver_data = IMX31_MMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .name = "mpc512x-sdhc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .driver_data = MPC512X_MMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MODULE_DEVICE_TABLE(platform, mxcmci_devtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct of_device_id mxcmci_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .compatible = "fsl,imx21-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .data = &mxcmci_devtype[IMX21_MMC],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .compatible = "fsl,imx31-mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .data = &mxcmci_devtype[IMX31_MMC],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .compatible = "fsl,mpc5121-sdhc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .data = &mxcmci_devtype[MPC512X_MMC],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MODULE_DEVICE_TABLE(of, mxcmci_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline int is_imx31_mmc(struct mxcmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return host->devtype == IMX31_MMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline int is_mpc512x_mmc(struct mxcmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return host->devtype == MPC512X_MMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (IS_ENABLED(CONFIG_PPC_MPC512x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return ioread32be(host->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return readl(host->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (IS_ENABLED(CONFIG_PPC_MPC512x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) iowrite32be(val, host->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) writel(val, host->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (IS_ENABLED(CONFIG_PPC_MPC512x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ioread32be(host->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return readw(host->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (IS_ENABLED(CONFIG_PPC_MPC512x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) iowrite32be(val, host->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) writew(val, host->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!IS_ERR(host->mmc->supply.vmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (host->power_mode == MMC_POWER_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mmc_regulator_set_ocr(host->mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) host->mmc->supply.vmmc, vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) else if (host->power_mode == MMC_POWER_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mmc_regulator_set_ocr(host->mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) host->mmc->supply.vmmc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (host->pdata && host->pdata->setpower)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) host->pdata->setpower(mmc_dev(host->mmc), vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static inline int mxcmci_use_dma(struct mxcmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return host->do_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void mxcmci_softreset(struct mxcmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* reset sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MMC_REG_STR_STP_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #if IS_ENABLED(CONFIG_PPC_MPC512x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static inline void buffer_swap32(u32 *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) for (i = 0; i < ((len + 3) / 4); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *buf = swab32(*buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void mxcmci_swap_buffers(struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) for_each_sg(data->sg, sg, data->sg_len, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) buffer_swap32(sg_virt(sg), sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int nob = data->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int blksz = data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int datasize = nob * blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) enum dma_transfer_direction slave_dirn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int i, nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) host->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) data->bytes_xfered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mxcmci_writew(host, nob, MMC_REG_NOB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) host->datasize = datasize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!mxcmci_use_dma(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) for_each_sg(data->sg, sg, data->sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) host->do_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (data->flags & MMC_DATA_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) host->dma_dir = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) slave_dirn = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) host->dma_dir = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) slave_dirn = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mxcmci_swap_buffers(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) nents = dma_map_sg(host->dma->device->dev, data->sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) data->sg_len, host->dma_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (nents != data->sg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) host->desc = dmaengine_prep_slave_sg(host->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) data->sg, data->sg_len, slave_dirn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!host->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) host->dma_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) host->do_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return 0; /* Fall back to PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dmaengine_submit(host->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dma_async_issue_pending(host->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static void mxcmci_dma_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct mxcmci_host *host = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) del_timer(&host->watchdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) stat = mxcmci_readl(host, MMC_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mxcmci_data_done(host, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned int cmdat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 int_cntr = host->default_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) WARN_ON(host->cmd != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) host->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) switch (mmc_resp_type(cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case MMC_RSP_R1: /* short CRC, OPCODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case MMC_RSP_R2: /* long 136 bit + CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case MMC_RSP_R3: /* short */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case MMC_RSP_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) mmc_resp_type(cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) cmd->error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int_cntr = INT_END_CMD_RES_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (mxcmci_use_dma(host)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (host->dma_dir == DMA_FROM_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) host->desc->callback = mxcmci_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) host->desc->callback_param = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int_cntr |= INT_WRITE_OP_DONE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (host->use_sdio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int_cntr |= INT_SDIO_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static void mxcmci_finish_request(struct mxcmci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u32 int_cntr = host->default_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (host->use_sdio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int_cntr |= INT_SDIO_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) host->req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) mmc_request_done(host->mmc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct mmc_data *data = host->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int data_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (mxcmci_use_dma(host)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) host->dma_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) mxcmci_swap_buffers(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (stat & STATUS_ERR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (stat & STATUS_CRC_READ_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) data->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) } else if (stat & STATUS_CRC_WRITE_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 err_code = (stat >> 9) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (err_code == 2) { /* No CRC response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "%s: No CRC -ETIMEDOUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "%s: -EILSEQ\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) data->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) } else if (stat & STATUS_TIME_OUT_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "%s: read -ETIMEDOUT\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) data->error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) data->bytes_xfered = host->datasize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) data_error = data->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return data_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct mmc_command *cmd = host->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 a, b, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (stat & STATUS_TIME_OUT_RESP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) a = mxcmci_readw(host, MMC_REG_RES_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) b = mxcmci_readw(host, MMC_REG_RES_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) cmd->resp[i] = a << 16 | b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) a = mxcmci_readw(host, MMC_REG_RES_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) b = mxcmci_readw(host, MMC_REG_RES_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) c = mxcmci_readw(host, MMC_REG_RES_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) cmd->resp[0] = a << 24 | b << 8 | c >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned long timeout = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) stat = mxcmci_readl(host, MMC_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (stat & STATUS_ERR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mxcmci_softreset(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mxcmci_set_clk_rate(host, host->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return STATUS_TIME_OUT_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (stat & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned int stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 *buf = _buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) while (bytes > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) stat = mxcmci_poll_status(host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) bytes -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u8 *b = (u8 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) stat = mxcmci_poll_status(host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) memcpy(b, &tmp, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned int stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u32 *buf = _buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) while (bytes > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) bytes -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u8 *b = (u8 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) memcpy(&tmp, b, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static int mxcmci_transfer_data(struct mxcmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct mmc_data *data = host->req->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int stat, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) host->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) host->datasize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (data->flags & MMC_DATA_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) for_each_sg(data->sg, sg, data->sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) stat = mxcmci_pull(host, sg_virt(sg), sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) host->datasize += sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) for_each_sg(data->sg, sg, data->sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) stat = mxcmci_push(host, sg_virt(sg), sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) host->datasize += sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static void mxcmci_datawork(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct mxcmci_host *host = container_of(work, struct mxcmci_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) datawork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int datastat = mxcmci_transfer_data(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MMC_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) mxcmci_finish_data(host, datastat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (host->req->stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (mxcmci_start_cmd(host, host->req->stop, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) mxcmci_finish_request(host, host->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) mxcmci_finish_request(host, host->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct mmc_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int data_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!host->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (!host->req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) req = host->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!req->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) host->req = NULL; /* we will handle finish req below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) data_error = mxcmci_finish_data(host, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (data_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mxcmci_read_response(host, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (req->stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (mxcmci_start_cmd(host, req->stop, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) mxcmci_finish_request(host, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mxcmci_finish_request(host, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) mxcmci_read_response(host, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (!host->data && host->req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) mxcmci_finish_request(host, host->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* For the DMA case the DMA engine handles the data transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * automatically. For non DMA we have to do it ourselves.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * Don't do it in interrupt context though.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (!mxcmci_use_dma(host) && host->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) schedule_work(&host->datawork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static irqreturn_t mxcmci_irq(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct mxcmci_host *host = devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) bool sdio_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) stat = mxcmci_readl(host, MMC_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) mxcmci_writel(host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) STATUS_WRITE_OP_DONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) MMC_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (sdio_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) mmc_signal_sdio_irq(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (stat & STATUS_END_CMD_RESP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) mxcmci_cmd_done(host, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) del_timer(&host->watchdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) mxcmci_data_done(host, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (host->default_irq_mask &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) mmc_detect_change(host->mmc, msecs_to_jiffies(200));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct mxcmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) unsigned int cmdat = host->cmdat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) WARN_ON(host->req != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) host->req = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) host->cmdat &= ~CMD_DAT_CONT_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (host->dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) host->do_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (req->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) error = mxcmci_setup_data(host, req->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) req->cmd->error = error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) cmdat |= CMD_DAT_CONT_DATA_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (req->data->flags & MMC_DATA_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) cmdat |= CMD_DAT_CONT_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) error = mxcmci_start_cmd(host, req->cmd, cmdat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mxcmci_finish_request(host, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) unsigned int divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) int prescaler = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) unsigned int clk_in = clk_get_rate(host->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) while (prescaler <= 0x800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) for (divider = 1; divider <= 0xF; divider++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) x = (clk_in / (divider + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (prescaler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) x /= (prescaler * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (x <= clk_ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (divider < 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (prescaler == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) prescaler = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) prescaler <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) prescaler, divider, clk_in, clk_ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static int mxcmci_setup_dma(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct mxcmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct dma_slave_config *config = &host->dma_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) config->dst_addr_width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) config->src_addr_width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) config->dst_maxburst = host->burstlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) config->src_maxburst = host->burstlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) config->device_fc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return dmaengine_slave_config(host->dma, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct mxcmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int burstlen, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (ios->bus_width == MMC_BUS_WIDTH_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) burstlen = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) burstlen = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) host->burstlen = burstlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = mxcmci_setup_dma(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) "failed to config DMA channel. Falling back to PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dma_release_channel(host->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) host->do_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) host->dma = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (ios->bus_width == MMC_BUS_WIDTH_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (host->power_mode != ios->power_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) host->power_mode = ios->power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) mxcmci_set_power(host, ios->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (ios->power_mode == MMC_POWER_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) host->cmdat |= CMD_DAT_CONT_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (ios->clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) mxcmci_set_clk_rate(host, ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) host->clock = ios->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static irqreturn_t mxcmci_detect_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct mmc_host *mmc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_dbg(mmc_dev(mmc), "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) mmc_detect_change(mmc, msecs_to_jiffies(250));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static int mxcmci_get_ro(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct mxcmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (host->pdata && host->pdata->get_ro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return !!host->pdata->get_ro(mmc_dev(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * If board doesn't support read only detection (no mmc_gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * context or gpio is invalid), then let the mmc core decide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * what to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return mmc_gpio_get_ro(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct mxcmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) u32 int_cntr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) host->use_sdio = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) int_cntr |= INT_SDIO_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) int_cntr &= ~INT_SDIO_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct mxcmci_host *mxcmci = mmc_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * MX3 SoCs have a silicon bug which corrupts CRC calculation of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * multi-block transfers when connected SDIO peripheral doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * drive the BUSY line as required by the specs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * One way to prevent this is to only allow 1-bit transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) host->caps &= ~MMC_CAP_4_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) host->caps |= MMC_CAP_4_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static bool filter(struct dma_chan *chan, void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct mxcmci_host *host = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (!imx_dma_is_general_purpose(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) chan->private = &host->dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static void mxcmci_watchdog(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct mxcmci_host *host = from_timer(host, t, watchdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct mmc_request *req = host->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (host->dma_dir == DMA_FROM_DEVICE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) dmaengine_terminate_all(host->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) "%s: read time out (status = 0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) __func__, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) "%s: write time out (status = 0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) __func__, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) mxcmci_softreset(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* Mark transfer as erroneus and inform the upper layers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (host->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) host->data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) host->req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) mmc_request_done(host->mmc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static const struct mmc_host_ops mxcmci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .request = mxcmci_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .set_ios = mxcmci_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .get_ro = mxcmci_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .enable_sdio_irq = mxcmci_enable_sdio_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .init_card = mxcmci_init_card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static int mxcmci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct mxcmci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) int ret = 0, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) bool dat3_card_detect = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) pr_info("i.MX/MPC512x SDHC driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) of_id = of_match_device(mxcmci_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (!mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) host->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (IS_ERR(host->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ret = PTR_ERR(host->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) host->phys_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret = mmc_of_parse(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) mmc->ops = &mxcmci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* For devicetree parsing, the bus width is read from devicetree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) mmc->caps |= MMC_CAP_SDIO_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* MMC core transfer sizes tunable parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) mmc->max_blk_size = 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) mmc->max_blk_count = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) mmc->max_seg_size = mmc->max_req_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (of_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) const struct platform_device_id *id_entry = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) host->devtype = id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) host->devtype = pdev->id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* adjust max_segs after devtype detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (!is_mpc512x_mmc(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) mmc->max_segs = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) host->mmc = mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) host->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) spin_lock_init(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) dat3_card_detect = pdata->dat3_card_detect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) else if (mmc_card_is_removable(mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) dat3_card_detect = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ret = mmc_regulator_get_supply(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (!mmc->ocr_avail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (pdata && pdata->ocr_avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) mmc->ocr_avail = pdata->ocr_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (dat3_card_detect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) host->default_irq_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) host->default_irq_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (IS_ERR(host->clk_ipg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ret = PTR_ERR(host->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) host->clk_per = devm_clk_get(&pdev->dev, "per");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (IS_ERR(host->clk_per)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ret = PTR_ERR(host->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ret = clk_prepare_enable(host->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ret = clk_prepare_enable(host->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) goto out_clk_per_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) mxcmci_softreset(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (host->rev_no != 0x400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) host->rev_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) goto out_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) mmc->f_min = clk_get_rate(host->clk_per) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) mmc->f_max = clk_get_rate(host->clk_per) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* recommended in data sheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (!host->pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) host->dma = dma_request_chan(&pdev->dev, "rx-tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (IS_ERR(host->dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (PTR_ERR(host->dma) == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) goto out_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* Ignore errors to fall back to PIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) host->dma = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) host->dmareq = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) host->dma_data.priority = DMA_PRIO_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) host->dma_data.dma_request = host->dmareq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) host->dma = dma_request_channel(mask, filter, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (host->dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) mmc->max_seg_size = dma_get_max_seg_size(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) host->dma->device->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) INIT_WORK(&host->datawork, mxcmci_datawork);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dev_name(&pdev->dev), host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) goto out_free_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) platform_set_drvdata(pdev, mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (host->pdata && host->pdata->init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) goto out_free_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) timer_setup(&host->watchdog, mxcmci_watchdog, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) out_free_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (host->dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) dma_release_channel(host->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) out_clk_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) clk_disable_unprepare(host->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) out_clk_per_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) clk_disable_unprepare(host->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static int mxcmci_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct mmc_host *mmc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct mxcmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) mmc_remove_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (host->pdata && host->pdata->exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) host->pdata->exit(&pdev->dev, mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (host->dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) dma_release_channel(host->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) clk_disable_unprepare(host->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) clk_disable_unprepare(host->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static int mxcmci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct mmc_host *mmc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct mxcmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) clk_disable_unprepare(host->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) clk_disable_unprepare(host->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static int mxcmci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct mmc_host *mmc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct mxcmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) ret = clk_prepare_enable(host->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ret = clk_prepare_enable(host->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) clk_disable_unprepare(host->clk_per);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) static struct platform_driver mxcmci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .probe = mxcmci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .remove = mxcmci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .id_table = mxcmci_devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .pm = &mxcmci_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .of_match_table = mxcmci_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) module_platform_driver(mxcmci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) MODULE_AUTHOR("Sascha Hauer, Pengutronix");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) MODULE_ALIAS("platform:mxc-mmc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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