Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Copyright (C) 2008 Marvell Semiconductors, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef __MVSDIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define __MVSDIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Clock rates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define MVSD_CLOCKRATE_MAX			50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define MVSD_BASE_DIV_MAX			0x7ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MVSD_SYS_ADDR_LOW			0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MVSD_SYS_ADDR_HI			0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MVSD_BLK_SIZE				0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MVSD_BLK_COUNT				0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MVSD_ARG_LOW				0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MVSD_ARG_HI				0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MVSD_XFER_MODE				0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MVSD_CMD				0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MVSD_RSP(i)				(0x020 + ((i)<<2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MVSD_RSP0				0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MVSD_RSP1				0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MVSD_RSP2				0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MVSD_RSP3				0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MVSD_RSP4				0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MVSD_RSP5				0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MVSD_RSP6				0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MVSD_RSP7				0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MVSD_FIFO				0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MVSD_RSP_CRC7				0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MVSD_HW_STATE				0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MVSD_HOST_CTRL				0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MVSD_BLK_GAP_CTRL			0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MVSD_CLK_CTRL				0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MVSD_SW_RESET				0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MVSD_NOR_INTR_STATUS			0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MVSD_ERR_INTR_STATUS			0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MVSD_NOR_STATUS_EN			0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MVSD_ERR_STATUS_EN			0x06c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MVSD_NOR_INTR_EN			0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MVSD_ERR_INTR_EN			0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MVSD_AUTOCMD12_ERR_STATUS		0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MVSD_CURR_BYTE_LEFT			0x07c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MVSD_CURR_BLK_LEFT			0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MVSD_AUTOCMD12_ARG_LOW			0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MVSD_AUTOCMD12_ARG_HI			0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MVSD_AUTOCMD12_CMD			0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MVSD_AUTO_RSP(i)			(0x090 + ((i)<<2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MVSD_AUTO_RSP0				0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MVSD_AUTO_RSP1				0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MVSD_AUTO_RSP2				0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MVSD_CLK_DIV				0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MVSD_WINDOW_CTRL(i)			(0x108 + ((i) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MVSD_WINDOW_BASE(i)			(0x10c + ((i) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * MVSD_CMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MVSD_CMD_RSP_NONE			(0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MVSD_CMD_RSP_136			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MVSD_CMD_RSP_48				(2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define MVSD_CMD_RSP_48BUSY			(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define MVSD_CMD_CHECK_DATACRC16		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MVSD_CMD_CHECK_CMDCRC			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MVSD_CMD_INDX_CHECK			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MVSD_CMD_DATA_PRESENT			(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MVSD_UNEXPECTED_RESP			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MVSD_CMD_INDEX(x)			((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * MVSD_AUTOCMD12_CMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MVSD_AUTOCMD12_BUSY			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define MVSD_AUTOCMD12_INDX_CHECK		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MVSD_AUTOCMD12_INDEX(x)			((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * MVSD_XFER_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define MVSD_XFER_MODE_WR_DATA_START		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define MVSD_XFER_MODE_HW_WR_DATA_EN		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define MVSD_XFER_MODE_AUTO_CMD12		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define MVSD_XFER_MODE_INT_CHK_EN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MVSD_XFER_MODE_TO_HOST			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MVSD_XFER_MODE_STOP_CLK			(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MVSD_XFER_MODE_PIO			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * MVSD_HOST_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MVSD_HOST_CTRL_PUSH_PULL_EN 		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MVSD_HOST_CTRL_CARD_TYPE_MEM_ONLY 	(0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MVSD_HOST_CTRL_CARD_TYPE_IO_ONLY 	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MVSD_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO 	(2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MVSD_HOST_CTRL_CARD_TYPE_IO_MMC 	(3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MVSD_HOST_CTRL_CARD_TYPE_MASK	 	(3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MVSD_HOST_CTRL_BIG_ENDIAN 		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MVSD_HOST_CTRL_LSB_FIRST 		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MVSD_HOST_CTRL_DATA_WIDTH_4_BITS 	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MVSD_HOST_CTRL_HI_SPEED_EN 		(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MVSD_HOST_CTRL_TMOUT_MAX 		0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MVSD_HOST_CTRL_TMOUT_MASK 		(0xf << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MVSD_HOST_CTRL_TMOUT(x) 		((x) << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MVSD_HOST_CTRL_TMOUT_EN 		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * MVSD_SW_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MVSD_SW_RESET_NOW			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * Normal interrupt status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MVSD_NOR_CMD_DONE			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MVSD_NOR_XFER_DONE			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MVSD_NOR_BLK_GAP_EVT			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MVSD_NOR_DMA_DONE			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MVSD_NOR_TX_AVAIL			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MVSD_NOR_RX_READY			(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MVSD_NOR_CARD_INT			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MVSD_NOR_READ_WAIT_ON			(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MVSD_NOR_RX_FIFO_8W			(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MVSD_NOR_TX_FIFO_8W			(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MVSD_NOR_SUSPEND_ON			(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MVSD_NOR_AUTOCMD12_DONE			(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MVSD_NOR_UNEXP_RSP			(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MVSD_NOR_ERROR				(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * Error status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MVSD_ERR_CMD_TIMEOUT			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MVSD_ERR_CMD_CRC			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MVSD_ERR_CMD_ENDBIT			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MVSD_ERR_CMD_INDEX			(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MVSD_ERR_DATA_TIMEOUT			(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MVSD_ERR_DATA_CRC			(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MVSD_ERR_DATA_ENDBIT			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MVSD_ERR_AUTOCMD12			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MVSD_ERR_CMD_STARTBIT			(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MVSD_ERR_XFER_SIZE			(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MVSD_ERR_RESP_T_BIT			(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MVSD_ERR_CRC_ENDBIT			(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MVSD_ERR_CRC_STARTBIT			(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MVSD_ERR_CRC_STATUS			(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  * CMD12 error status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MVSD_AUTOCMD12_ERR_NOTEXE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MVSD_AUTOCMD12_ERR_TIMEOUT		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MVSD_AUTOCMD12_ERR_CRC			(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MVSD_AUTOCMD12_ERR_ENDBIT		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MVSD_AUTOCMD12_ERR_INDEX		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MVSD_AUTOCMD12_ERR_RESP_T_BIT		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MVSD_AUTOCMD12_ERR_RESP_STARTBIT	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #endif