^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell MMC/SD/SDIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors: Maen Suleiman, Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008-2009 Marvell Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "mvsdio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRIVER_NAME "mvsdio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int maxfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int nodma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct mvsd_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int xfer_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int intr_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int pio_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void *pio_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int sg_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int ns_per_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int base_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define mvsd_write(offs, val) writel(val, iobase + (offs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define mvsd_read(offs) readl(iobase + (offs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void __iomem *iobase = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int tmout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int tmout_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * register is sometimes not set before a while when some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * "unusual" data block sizes are used (such as with the SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * command), even despite the fact that the XFER_DONE interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * was raised. And if another data transfer starts before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * this bit comes to good sense (which eventually happens by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * itself) then the new transfer simply fails with a timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long t = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int hw_state, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) hw_state = mvsd_read(MVSD_HW_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (time_after(jiffies, t)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dev_warn(host->dev, "FIFO_EMPTY bit missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } while (!(hw_state & (1 << 13)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "(hw=0x%04x, count=%d, jiffies=%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) hw_state, count, jiffies - (t - HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* If timeout=0 then maximum timeout index is used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) tmout += data->timeout_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) tmout_index = fls(tmout - 1) - 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (tmout_index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) tmout_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (data->flags & MMC_DATA_READ) ? "read" : "write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (u32)sg_virt(data->sg), data->blocks, data->blksz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) tmout, tmout_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mvsd_write(MVSD_HOST_CTRL, host->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mvsd_write(MVSD_BLK_COUNT, data->blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mvsd_write(MVSD_BLK_SIZE, data->blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (nodma || (data->blksz | data->sg->offset) & 3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ((!(data->flags & MMC_DATA_READ) && data->sg->offset & 0x3f))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * We cannot do DMA on a buffer which offset or size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * is not aligned on a 4-byte boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * It also appears the host to card DMA can corrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * data when the buffer is not aligned on a 64 byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) host->pio_size = data->blocks * data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) host->pio_ptr = sg_virt(data->sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!nodma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_dbg(host->dev, "fallback to PIO for data at 0x%p size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) host->pio_ptr, host->pio_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dma_addr_t phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) host->sg_frags = dma_map_sg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) phys_addr = sg_dma_address(data->sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct mvsd_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void __iomem *iobase = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct mmc_command *cmd = mrq->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 cmdreg = 0, xfer = 0, intr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) BUG_ON(host->mrq != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) host->mrq = mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) cmd->opcode, mvsd_read(MVSD_HW_STATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) cmdreg = MVSD_CMD_INDEX(cmd->opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (cmd->flags & MMC_RSP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cmdreg |= MVSD_CMD_RSP_48BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) else if (cmd->flags & MMC_RSP_136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cmdreg |= MVSD_CMD_RSP_136;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) else if (cmd->flags & MMC_RSP_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) cmdreg |= MVSD_CMD_RSP_48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) cmdreg |= MVSD_CMD_RSP_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (cmd->flags & MMC_RSP_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) cmdreg |= MVSD_CMD_CHECK_CMDCRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (cmd->flags & MMC_RSP_OPCODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) cmdreg |= MVSD_CMD_INDX_CHECK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) cmdreg |= MVSD_UNEXPECTED_RESP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) intr |= MVSD_NOR_UNEXP_RSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (mrq->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct mmc_data *data = mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) xfer |= MVSD_XFER_MODE_TO_HOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pio = mvsd_setup_data(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (pio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) xfer |= MVSD_XFER_MODE_PIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* PIO section of mvsd_irq has comments on those bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (data->flags & MMC_DATA_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) intr |= MVSD_NOR_TX_AVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) else if (host->pio_size > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) intr |= MVSD_NOR_RX_FIFO_8W;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) intr |= MVSD_NOR_RX_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (data->stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct mmc_command *stop = data->stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 cmd12reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (stop->flags & MMC_RSP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) cmd12reg |= MVSD_AUTOCMD12_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (stop->flags & MMC_RSP_OPCODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) xfer |= MVSD_XFER_MODE_AUTO_CMD12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) intr |= MVSD_NOR_AUTOCMD12_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) intr |= MVSD_NOR_XFER_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) intr |= MVSD_NOR_CMD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mvsd_write(MVSD_ARG_HI, cmd->arg >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) host->xfer_mode |= xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mvsd_write(MVSD_CMD, cmdreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) host->intr_en &= MVSD_NOR_CARD_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) host->intr_en |= intr | MVSD_NOR_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) timeout = cmd->busy_timeout ? cmd->busy_timeout : 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 err_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void __iomem *iobase = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned int response[8], i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) response[i] = mvsd_read(MVSD_RSP(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) cmd->resp[0] = ((response[0] & 0x03ff) << 22) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ((response[1] & 0xffff) << 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ((response[2] & 0xfc00) >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) cmd->resp[1] = ((response[2] & 0x03ff) << 22) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ((response[3] & 0xffff) << 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ((response[4] & 0xfc00) >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) cmd->resp[2] = ((response[4] & 0x03ff) << 22) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ((response[5] & 0xffff) << 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ((response[6] & 0xfc00) >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) cmd->resp[3] = ((response[6] & 0x03ff) << 22) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ((response[7] & 0x3fff) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) } else if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int response[3], i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) response[i] = mvsd_read(MVSD_RSP(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ((response[1] & 0xffff) << (14 - 8)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ((response[0] & 0x03ff) << (30 - 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) cmd->resp[1] = ((response[0] & 0xfc00) >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) cmd->resp[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) cmd->resp[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (err_status & MVSD_ERR_CMD_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MVSD_ERR_CMD_STARTBIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return err_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 err_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) void __iomem *iobase = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (host->pio_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) host->pio_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) host->pio_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (err_status & MVSD_ERR_DATA_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) data->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) else if (err_status & MVSD_ERR_XFER_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) data->error = -EBADE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) data->bytes_xfered =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* We can't be sure about the last block when errors are detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (data->bytes_xfered && data->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) data->bytes_xfered -= data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Handle Auto cmd 12 response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (data->stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int response[3], i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) response[i] = mvsd_read(MVSD_AUTO_RSP(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ((response[1] & 0xffff) << (14 - 8)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ((response[0] & 0x03ff) << (30 - 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) data->stop->resp[1] = ((response[0] & 0xfc00) >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) data->stop->resp[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) data->stop->resp[3] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (err_status & MVSD_ERR_AUTOCMD12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) data->stop->error = -ENOEXEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) data->stop->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) else if (err_cmd12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) data->stop->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) err_status &= ~MVSD_ERR_AUTOCMD12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return err_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static irqreturn_t mvsd_irq(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct mvsd_host *host = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) void __iomem *iobase = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 intr_status, intr_done_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int irq_handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) intr_status, mvsd_read(MVSD_NOR_INTR_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mvsd_read(MVSD_HW_STATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * It looks like, SDIO IP can issue one late, spurious irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * although all irqs should be disabled. To work around this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * bail out early, if we didn't expect any irqs to occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!mvsd_read(MVSD_NOR_INTR_EN) && !mvsd_read(MVSD_ERR_INTR_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_dbg(host->dev, "spurious irq detected intr 0x%04x intr_en 0x%04x erri 0x%04x erri_en 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) mvsd_read(MVSD_NOR_INTR_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) mvsd_read(MVSD_NOR_INTR_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) mvsd_read(MVSD_ERR_INTR_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mvsd_read(MVSD_ERR_INTR_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* PIO handling, if needed. Messy business... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (host->pio_size &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) (intr_status & host->intr_en &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u16 *p = host->pio_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int s = host->pio_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) readsw(iobase + MVSD_FIFO, p, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) p += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) s -= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * Normally we'd use < 32 here, but the RX_FIFO_8W bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * doesn't appear to assert when there is exactly 32 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * (8 words) left to fetch in a transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (s <= 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) put_unaligned(mvsd_read(MVSD_FIFO), p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) put_unaligned(mvsd_read(MVSD_FIFO), p++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) s -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u16 val[2] = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) val[0] = mvsd_read(MVSD_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) val[1] = mvsd_read(MVSD_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) memcpy(p, ((void *)&val) + 4 - s, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) s = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (s == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) host->intr_en &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) host->intr_en |= MVSD_NOR_RX_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) s, intr_status, mvsd_read(MVSD_HW_STATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) host->pio_ptr = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) host->pio_size = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) irq_handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) } else if (host->pio_size &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) (intr_status & host->intr_en &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u16 *p = host->pio_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int s = host->pio_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * The TX_FIFO_8W bit is unreliable. When set, bursting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * 16 halfwords all at once in the FIFO drops data. Actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * TX_AVAIL does go off after only one word is pushed even if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * TX_FIFO_8W remains set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mvsd_write(MVSD_FIFO, get_unaligned(p++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mvsd_write(MVSD_FIFO, get_unaligned(p++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) s -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (s < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u16 val[2] = {0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) memcpy(((void *)&val) + 4 - s, p, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mvsd_write(MVSD_FIFO, val[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mvsd_write(MVSD_FIFO, val[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) s = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (s == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) host->intr_en &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) s, intr_status, mvsd_read(MVSD_HW_STATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) host->pio_ptr = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) host->pio_size = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) irq_handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (intr_status & host->intr_en & ~intr_done_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct mmc_request *mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct mmc_command *cmd = mrq->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u32 err_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) del_timer(&host->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) host->intr_en &= MVSD_NOR_CARD_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) mvsd_write(MVSD_ERR_INTR_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (intr_status & MVSD_NOR_UNEXP_RSP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) cmd->error = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) } else if (intr_status & MVSD_NOR_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_dbg(host->dev, "err 0x%04x\n", err_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) err_status = mvsd_finish_cmd(host, cmd, err_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (mrq->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) err_status = mvsd_finish_data(host, mrq->data, err_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (err_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev_err(host->dev, "unhandled error status %#04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) err_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) cmd->error = -ENOMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) irq_handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (intr_status & MVSD_NOR_CARD_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) mmc_signal_sdio_irq(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) irq_handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (irq_handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_err(host->dev, "unhandled interrupt status=0x%04x en=0x%04x pio=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) intr_status, host->intr_en, host->pio_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static void mvsd_timeout_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct mvsd_host *host = from_timer(host, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) void __iomem *iobase = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (mrq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dev_err(host->dev, "Timeout waiting for hardware interrupt.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev_err(host->dev, "hw_state=0x%04x, intr_status=0x%04x intr_en=0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) mvsd_read(MVSD_HW_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) mvsd_read(MVSD_NOR_INTR_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mvsd_read(MVSD_NOR_INTR_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) host->intr_en &= MVSD_NOR_CARD_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) mvsd_write(MVSD_ERR_INTR_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mrq->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mvsd_finish_cmd(host, mrq->cmd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (mrq->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mrq->data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mvsd_finish_data(host, mrq->data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct mvsd_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) void __iomem *iobase = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) host->intr_en |= MVSD_NOR_CARD_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) host->intr_en &= ~MVSD_NOR_CARD_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static void mvsd_power_up(struct mvsd_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) void __iomem *iobase = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_dbg(host->dev, "power up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) mvsd_write(MVSD_NOR_INTR_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) mvsd_write(MVSD_ERR_INTR_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) mvsd_write(MVSD_XFER_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static void mvsd_power_down(struct mvsd_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) void __iomem *iobase = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev_dbg(host->dev, "power down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) mvsd_write(MVSD_NOR_INTR_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mvsd_write(MVSD_ERR_INTR_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) mvsd_write(MVSD_NOR_STATUS_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) mvsd_write(MVSD_ERR_STATUS_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct mvsd_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) void __iomem *iobase = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u32 ctrl_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (ios->power_mode == MMC_POWER_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) mvsd_power_up(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (ios->clock == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) host->clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_dbg(host->dev, "clock off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) } else if (ios->clock != host->clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (m > MVSD_BASE_DIV_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) m = MVSD_BASE_DIV_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) mvsd_write(MVSD_CLK_DIV, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) host->clock = ios->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ios->clock, host->base_clock / (m+1), m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* default transfer mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* default to maximum timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (ios->bus_width == MMC_BUS_WIDTH_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * The HI_SPEED_EN bit is causing trouble with many (but not all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * high speed SD, SDHC and SDIO cards. Not enabling that bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * makes all cards work. So let's just ignore that bit for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * and revisit this issue if problems for not enabling this bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * are ever reported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (ios->timing == MMC_TIMING_MMC_HS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ios->timing == MMC_TIMING_SD_HS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) host->ctrl = ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) "push-pull" : "open-drain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) "4bit-width" : "1bit-width",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) "high-speed" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (ios->power_mode == MMC_POWER_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) mvsd_power_down(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static const struct mmc_host_ops mvsd_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .request = mvsd_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .get_ro = mmc_gpio_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .set_ios = mvsd_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .enable_sdio_irq = mvsd_enable_sdio_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mv_conf_mbus_windows(struct mvsd_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) const struct mbus_dram_target_info *dram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) void __iomem *iobase = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) writel(0, iobase + MVSD_WINDOW_CTRL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) writel(0, iobase + MVSD_WINDOW_BASE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) for (i = 0; i < dram->num_cs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) const struct mbus_dram_window *cs = dram->cs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) writel(((cs->size - 1) & 0xffff0000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) (cs->mbus_attr << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) (dram->mbus_dram_target_id << 4) | 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) iobase + MVSD_WINDOW_CTRL(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int mvsd_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct mmc_host *mmc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct mvsd_host *host = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) const struct mbus_dram_target_info *dram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_err(&pdev->dev, "no DT node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (!mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) host->mmc = mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) host->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * Some non-DT platforms do not pass a clock, and the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * frequency is passed through platform_data. On DT platforms,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * a clock must always be passed, even if there is no gatable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * clock associated to the SDIO interface (it can simply be a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * fixed rate clock).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) host->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (IS_ERR(host->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dev_err(&pdev->dev, "no clock associated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) clk_prepare_enable(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) mmc->ops = &mvsd_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) mmc->f_max = MVSD_CLOCKRATE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) mmc->max_blk_size = 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) mmc->max_blk_count = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) mmc->max_segs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) host->base_clock = clk_get_rate(host->clk) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ret = mmc_of_parse(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (maxfreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mmc->f_max = maxfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) spin_lock_init(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) host->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (IS_ERR(host->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = PTR_ERR(host->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* (Re-)program MBUS remapping windows if we are asked to. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dram = mv_mbus_dram_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (dram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) mv_conf_mbus_windows(host, dram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mvsd_power_down(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_err(&pdev->dev, "cannot assign irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) timer_setup(&host->timer, mvsd_timeout_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) platform_set_drvdata(pdev, mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret = mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (!(mmc->caps & MMC_CAP_NEEDS_POLL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_dbg(&pdev->dev, "using GPIO for card detection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev_dbg(&pdev->dev, "lacking card detect (fall back to polling)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!IS_ERR(host->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) clk_disable_unprepare(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int mvsd_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct mmc_host *mmc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct mvsd_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) mmc_remove_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) del_timer_sync(&host->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) mvsd_power_down(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (!IS_ERR(host->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) clk_disable_unprepare(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const struct of_device_id mvsdio_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) { .compatible = "marvell,orion-sdio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) MODULE_DEVICE_TABLE(of, mvsdio_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static struct platform_driver mvsd_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .probe = mvsd_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .remove = mvsd_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .of_match_table = mvsdio_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) module_platform_driver(mvsd_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* maximum card clock frequency (default 50MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) module_param(maxfreq, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* force PIO transfers all the time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) module_param(nodma, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) MODULE_ALIAS("platform:mvsdio");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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