^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * MOXA ART MMC host driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Jonas Jensen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Jonas Jensen <jonas.jensen@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on code from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Moxa Technologies Co., Ltd. <www.moxa.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mmc/sd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_COMMAND 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_ARGUMENT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_RESPONSE0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_RESPONSE1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_RESPONSE2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define REG_RESPONSE3 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REG_RESPONSE_COMMAND 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REG_DATA_CONTROL 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_DATA_TIMER 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_DATA_LENGTH 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_STATUS 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_CLEAR 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_INTERRUPT_MASK 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_POWER_CONTROL 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_CLOCK_CONTROL 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_BUS_WIDTH 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_DATA_WINDOW 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_FEATURE 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_REVISION 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* REG_COMMAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CMD_SDC_RESET BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CMD_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CMD_APP_CMD BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CMD_LONG_RSP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CMD_NEED_RSP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CMD_IDX_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* REG_RESPONSE_COMMAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RSP_CMD_APP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RSP_CMD_IDX_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* REG_DATA_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DCR_DATA_FIFO_RESET BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DCR_DATA_THRES BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DCR_DATA_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DCR_DMA_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DCR_DATA_WRITE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DCR_BLK_SIZE 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* REG_DATA_LENGTH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DATA_LEN_MASK 0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* REG_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define WRITE_PROT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CARD_DETECT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* 1-10 below can be sent to either registers, interrupt or clear. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CARD_CHANGE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define FIFO_ORUN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define FIFO_URUN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DATA_END BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CMD_SENT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DATA_CRC_OK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RSP_CRC_OK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DATA_TIMEOUT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RSP_TIMEOUT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DATA_CRC_FAIL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RSP_CRC_FAIL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MASK_RSP (RSP_TIMEOUT | RSP_CRC_FAIL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) RSP_CRC_OK | CARD_DETECT | CMD_SENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MASK_DATA (DATA_CRC_OK | DATA_END | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) DATA_CRC_FAIL | DATA_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MASK_INTR_PIO (FIFO_URUN | FIFO_ORUN | CARD_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* REG_POWER_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SD_POWER_ON BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SD_POWER_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* REG_CLOCK_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_HISPD BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_OFF BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_SD BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_DIV_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* REG_BUS_WIDTH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BUS_WIDTH_8 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BUS_WIDTH_4 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BUS_WIDTH_1 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MMC_VDD_360 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MIN_POWER (MMC_VDD_360 - SD_POWER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MAX_RETRIES 500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct moxart_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) phys_addr_t reg_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct dma_chan *dma_chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct dma_chan *dma_chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct dma_async_tx_descriptor *tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct scatterlist *cur_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct completion dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct completion pio_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 num_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 data_remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 fifo_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) long sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bool have_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bool is_removed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline void moxart_init_sg(struct moxart_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) host->cur_sg = data->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) host->num_sg = data->sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) host->data_remain = host->cur_sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (host->data_remain > host->data_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) host->data_remain = host->data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static inline int moxart_next_sg(struct moxart_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct mmc_data *data = host->mrq->cmd->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) host->cur_sg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) host->num_sg--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (host->num_sg > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) host->data_remain = host->cur_sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) remain = host->data_len - data->bytes_xfered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (remain > 0 && remain < host->data_remain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) host->data_remain = remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return host->num_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int moxart_wait_for_status(struct moxart_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 mask, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) for (i = 0; i < MAX_RETRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *status = readl(host->base + REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!(*status & mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) writel(*status & mask, host->base + REG_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(mmc_dev(host->mmc), "timed out waiting for status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void moxart_send_command(struct moxart_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 status, cmdctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) writel(RSP_TIMEOUT | RSP_CRC_OK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) RSP_CRC_FAIL | CMD_SENT, host->base + REG_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel(cmd->arg, host->base + REG_ARGUMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) cmdctrl = cmd->opcode & CMD_IDX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (cmdctrl == SD_APP_SET_BUS_WIDTH || cmdctrl == SD_APP_OP_COND ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cmdctrl == SD_APP_SEND_SCR || cmdctrl == SD_APP_SD_STATUS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) cmdctrl == SD_APP_SEND_NUM_WR_BLKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) cmdctrl |= CMD_APP_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (cmd->flags & MMC_RSP_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) cmdctrl |= CMD_NEED_RSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (cmd->flags & MMC_RSP_136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cmdctrl |= CMD_LONG_RSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel(cmdctrl | CMD_EN, host->base + REG_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (moxart_wait_for_status(host, MASK_RSP, &status) == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (status & RSP_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (status & RSP_CRC_FAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) cmd->error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (status & RSP_CRC_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) cmd->resp[3] = readl(host->base + REG_RESPONSE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) cmd->resp[2] = readl(host->base + REG_RESPONSE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) cmd->resp[1] = readl(host->base + REG_RESPONSE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cmd->resp[0] = readl(host->base + REG_RESPONSE3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) cmd->resp[0] = readl(host->base + REG_RESPONSE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static void moxart_dma_complete(void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct moxart_host *host = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) complete(&host->dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void moxart_transfer_dma(struct mmc_data *data, struct moxart_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 len, dir_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) long dma_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct dma_async_tx_descriptor *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct dma_chan *dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (host->data_len == data->bytes_xfered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (data->flags & MMC_DATA_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dma_chan = host->dma_chan_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dir_slave = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dma_chan = host->dma_chan_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dir_slave = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) len = dma_map_sg(dma_chan->device->dev, data->sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) data->sg_len, mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) desc = dmaengine_prep_slave_sg(dma_chan, data->sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) len, dir_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DMA_PREP_INTERRUPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) host->tx_desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) desc->callback = moxart_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) desc->callback_param = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dmaengine_submit(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dma_async_issue_pending(dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) data->bytes_xfered += host->data_remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dma_time = wait_for_completion_interruptible_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) &host->dma_complete, host->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dma_unmap_sg(dma_chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void moxart_transfer_pio(struct moxart_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct mmc_data *data = host->mrq->cmd->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 *sgp, len = 0, remain, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (host->data_len == data->bytes_xfered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) sgp = sg_virt(host->cur_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) remain = host->data_remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (data->flags & MMC_DATA_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) while (remain > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (moxart_wait_for_status(host, FIFO_URUN, &status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) complete(&host->pio_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) for (len = 0; len < remain && len < host->fifo_width;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) iowrite32(*sgp, host->base + REG_DATA_WINDOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) sgp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) len += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) remain -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) while (remain > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (moxart_wait_for_status(host, FIFO_ORUN, &status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) complete(&host->pio_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) for (len = 0; len < remain && len < host->fifo_width;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* SCR data must be read in big endian. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (data->mrq->cmd->opcode == SD_APP_SEND_SCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *sgp = ioread32be(host->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) REG_DATA_WINDOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) *sgp = ioread32(host->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) REG_DATA_WINDOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) sgp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) len += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) remain -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) data->bytes_xfered += host->data_remain - remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) host->data_remain = remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (host->data_len != data->bytes_xfered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) moxart_next_sg(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) complete(&host->pio_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void moxart_prepare_data(struct moxart_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct mmc_data *data = host->mrq->cmd->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 datactrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int blksz_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) host->data_len = data->blocks * data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) blksz_bits = ffs(data->blksz) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) BUG_ON(1 << blksz_bits != data->blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) moxart_init_sg(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) datactrl = DCR_DATA_EN | (blksz_bits & DCR_BLK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (data->flags & MMC_DATA_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) datactrl |= DCR_DATA_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if ((host->data_len > host->fifo_width) && host->have_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) datactrl |= DCR_DMA_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) writel(host->rate, host->base + REG_DATA_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) writel(host->data_len, host->base + REG_DATA_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) writel(datactrl, host->base + REG_DATA_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static void moxart_request(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct moxart_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) long pio_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) init_completion(&host->dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) init_completion(&host->pio_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) host->mrq = mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (readl(host->base + REG_STATUS) & CARD_DETECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) mrq->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) goto request_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) moxart_prepare_data(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) moxart_send_command(host, host->mrq->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (mrq->cmd->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if ((host->data_len > host->fifo_width) && host->have_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) moxart_transfer_dma(mrq->cmd->data, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* PIO transfers start from interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pio_time = wait_for_completion_interruptible_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) &host->pio_complete, host->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (host->is_removed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_err(mmc_dev(host->mmc), "card removed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mrq->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) goto request_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (moxart_wait_for_status(host, MASK_DATA, &status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mrq->cmd->data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) goto request_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (status & DATA_CRC_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mrq->cmd->data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (mrq->cmd->data->stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) moxart_send_command(host, mrq->cmd->data->stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) request_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static irqreturn_t moxart_irq(int irq, void *devid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct moxart_host *host = (struct moxart_host *)devid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) status = readl(host->base + REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (status & CARD_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) host->is_removed = status & CARD_DETECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (host->is_removed && host->have_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dmaengine_terminate_all(host->dma_chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dmaengine_terminate_all(host->dma_chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) writel(MASK_INTR_PIO, host->base + REG_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mmc_detect_change(host->mmc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (status & (FIFO_ORUN | FIFO_URUN) && host->mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) moxart_transfer_pio(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static void moxart_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct moxart_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 power, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (ios->clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) for (div = 0; div < CLK_DIV_MASK; ++div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (ios->clock >= host->sysclk / (2 * (div + 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ctrl = CLK_SD | div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) host->rate = host->sysclk / (2 * (div + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (host->rate > host->sysclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ctrl |= CLK_HISPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) writel(ctrl, host->base + REG_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (ios->power_mode == MMC_POWER_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) host->base + REG_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (ios->vdd < MIN_POWER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) power = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) power = ios->vdd - MIN_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) writel(SD_POWER_ON | (u32) power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) host->base + REG_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) switch (ios->bus_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case MMC_BUS_WIDTH_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case MMC_BUS_WIDTH_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) writel(BUS_WIDTH_8, host->base + REG_BUS_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int moxart_get_ro(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct moxart_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return !!(readl(host->base + REG_STATUS) & WRITE_PROT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static const struct mmc_host_ops moxart_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .request = moxart_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .set_ios = moxart_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .get_ro = moxart_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int moxart_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct resource res_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct moxart_host *host = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) void __iomem *reg_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mmc = mmc_alloc_host(sizeof(struct moxart_host), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (!mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dev_err(dev, "mmc_alloc_host failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) goto out_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = of_address_to_resource(node, 0, &res_mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_err(dev, "of_address_to_resource failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) goto out_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_err(dev, "irq_of_parse_and_map failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) goto out_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) goto out_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) reg_mmc = devm_ioremap_resource(dev, &res_mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (IS_ERR(reg_mmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ret = PTR_ERR(reg_mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) goto out_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ret = mmc_of_parse(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) goto out_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) host->mmc = mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) host->base = reg_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) host->reg_phys = res_mmc.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) host->timeout = msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) host->sysclk = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) host->fifo_width = readl(host->base + REG_FEATURE) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) host->dma_chan_tx = dma_request_chan(dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) host->dma_chan_rx = dma_request_chan(dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) spin_lock_init(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) mmc->ops = &moxart_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mmc->f_max = DIV_ROUND_CLOSEST(host->sysclk, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) mmc->f_min = DIV_ROUND_CLOSEST(host->sysclk, CLK_DIV_MASK * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mmc->ocr_avail = 0xffff00; /* Support 2.0v - 3.6v power. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (IS_ERR(host->dma_chan_tx) || IS_ERR(host->dma_chan_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (PTR_ERR(host->dma_chan_tx) == -EPROBE_DEFER ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PTR_ERR(host->dma_chan_rx) == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!IS_ERR(host->dma_chan_tx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dma_release_channel(host->dma_chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) host->dma_chan_tx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (!IS_ERR(host->dma_chan_rx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dma_release_channel(host->dma_chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) host->dma_chan_rx = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_dbg(dev, "PIO mode transfer enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) host->have_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dev_dbg(dev, "DMA channels found (%p,%p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) host->dma_chan_tx, host->dma_chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) host->have_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) memset(&cfg, 0, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) cfg.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) cfg.src_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) cfg.dst_addr = host->reg_phys + REG_DATA_WINDOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dmaengine_slave_config(host->dma_chan_tx, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) cfg.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) cfg.src_addr = host->reg_phys + REG_DATA_WINDOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) cfg.dst_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dmaengine_slave_config(host->dma_chan_rx, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) switch ((readl(host->base + REG_BUS_WIDTH) >> 3) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) mmc->caps |= MMC_CAP_4_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) writel(0, host->base + REG_INTERRUPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) writel(CMD_SDC_RESET, host->base + REG_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) for (i = 0; i < MAX_RETRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!(readl(host->base + REG_COMMAND) & CMD_SDC_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = devm_request_irq(dev, irq, moxart_irq, 0, "moxart-mmc", host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_set_drvdata(dev, mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dev_dbg(dev, "IRQ=%d, FIFO is %d bytes\n", irq, host->fifo_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (!IS_ERR_OR_NULL(host->dma_chan_tx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dma_release_channel(host->dma_chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (!IS_ERR_OR_NULL(host->dma_chan_rx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dma_release_channel(host->dma_chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) out_mmc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static int moxart_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct mmc_host *mmc = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct moxart_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_set_drvdata(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (!IS_ERR_OR_NULL(host->dma_chan_tx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dma_release_channel(host->dma_chan_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (!IS_ERR_OR_NULL(host->dma_chan_rx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dma_release_channel(host->dma_chan_rx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mmc_remove_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) writel(0, host->base + REG_INTERRUPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) writel(0, host->base + REG_POWER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) host->base + REG_CLOCK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static const struct of_device_id moxart_mmc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) { .compatible = "moxa,moxart-mmc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) { .compatible = "faraday,ftsdc010" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) MODULE_DEVICE_TABLE(of, moxart_mmc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static struct platform_driver moxart_mmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .probe = moxart_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .remove = moxart_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .name = "mmc-moxart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .of_match_table = moxart_mmc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) module_platform_driver(moxart_mmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) MODULE_ALIAS("platform:mmc-moxart");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) MODULE_DESCRIPTION("MOXA ART MMC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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