Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define MMCIPOWER		0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define MCI_PWR_OFF		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define MCI_PWR_UP		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define MCI_PWR_ON		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define MCI_OD			(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define MCI_ROD			(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * The ST Micro version does not have ROD and reuse the voltage registers for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * direction settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MCI_ST_DATA2DIREN	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MCI_ST_CMDDIREN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MCI_ST_DATA0DIREN	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MCI_ST_DATA31DIREN	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MCI_ST_FBCLKEN		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MCI_ST_DATA74DIREN	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * The STM32 sdmmc does not have PWR_UP/OD/ROD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * and uses the power register for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MCI_STM32_PWR_CYC	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MCI_STM32_VSWITCH	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MCI_STM32_VSWITCHEN	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MCI_STM32_DIRPOL	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MMCICLOCK		0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MCI_CLK_ENABLE		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MCI_CLK_PWRSAVE		(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MCI_CLK_BYPASS		(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MCI_4BIT_BUS		(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * 8bit wide buses, hardware flow contronl, negative edges and clock inversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * supported in ST Micro U300 and Ux500 versions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MCI_ST_8BIT_BUS		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MCI_ST_U300_HWFCEN	(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MCI_ST_UX500_NEG_EDGE	(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MCI_ST_UX500_HWFCEN	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MCI_ST_UX500_CLK_INV	(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* Modified PL180 on Versatile Express platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MCI_ARM_HWFCEN		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* Modified on Qualcomm Integrations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MCI_QCOM_CLK_WIDEBUS_8	(BIT(10) | BIT(11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MCI_QCOM_CLK_FLOWENA	BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MCI_QCOM_CLK_INVERTOUT	BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* select in latch data and command in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MCI_QCOM_CLK_SELECT_IN_FBCLK	BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MCI_QCOM_CLK_SELECT_IN_DDR_MODE	(BIT(14) | BIT(15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* Modified on STM32 sdmmc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MCI_STM32_CLK_CLKDIV_MSK	GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MCI_STM32_CLK_WIDEBUS_4		BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MCI_STM32_CLK_WIDEBUS_8		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MCI_STM32_CLK_NEGEDGE		BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MCI_STM32_CLK_HWFCEN		BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MCI_STM32_CLK_DDR		BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MCI_STM32_CLK_BUSSPEED		BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MCI_STM32_CLK_SEL_MSK		GENMASK(21, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MCI_STM32_CLK_SELCK		(0 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MCI_STM32_CLK_SELCKIN		(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MCI_STM32_CLK_SELFBCK		(2 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define MMCIARGUMENT		0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* The command register controls the Command Path State Machine (CPSM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define MMCICOMMAND		0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MCI_CPSM_RESPONSE	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define MCI_CPSM_LONGRSP	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MCI_CPSM_INTERRUPT	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MCI_CPSM_PENDING	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MCI_CPSM_ENABLE		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /* Command register flag extenstions in the ST Micro versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MCI_CPSM_ST_SDIO_SUSP		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MCI_CPSM_ST_ENCMD_COMPL		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define MCI_CPSM_ST_NIEN		BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define MCI_CPSM_ST_CE_ATACMD		BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* Command register flag extensions in the Qualcomm versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define MCI_CPSM_QCOM_PROGENA		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MCI_CPSM_QCOM_DATCMD		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MCI_CPSM_QCOM_MCIABORT		BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define MCI_CPSM_QCOM_CCSENABLE		BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MCI_CPSM_QCOM_CCSDISABLE	BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define MCI_CPSM_QCOM_AUTO_CMD19	BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define MCI_CPSM_QCOM_AUTO_CMD21	BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* Command register in STM32 sdmmc versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define MCI_CPSM_STM32_CMDTRANS		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define MCI_CPSM_STM32_CMDSTOP		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define MCI_CPSM_STM32_WAITRESP_MASK	GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define MCI_CPSM_STM32_NORSP		(0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define MCI_CPSM_STM32_SRSP_CRC		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define MCI_CPSM_STM32_SRSP		(2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MCI_CPSM_STM32_LRSP_CRC		(3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MCI_CPSM_STM32_ENABLE		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MMCIRESPCMD		0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MMCIRESPONSE0		0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MMCIRESPONSE1		0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MMCIRESPONSE2		0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MMCIRESPONSE3		0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MMCIDATATIMER		0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MMCIDATALENGTH		0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* The data control register controls the Data Path State Machine (DPSM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MMCIDATACTRL		0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MCI_DPSM_ENABLE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MCI_DPSM_DIRECTION	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MCI_DPSM_MODE		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MCI_DPSM_DMAENABLE	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MCI_DPSM_BLOCKSIZE	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Control register extensions in the ST Micro U300 and Ux500 versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MCI_DPSM_ST_RWSTART	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MCI_DPSM_ST_RWSTOP	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MCI_DPSM_ST_RWMOD	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MCI_DPSM_ST_SDIOEN	BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Control register extensions in the ST Micro Ux500 versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MCI_DPSM_ST_DMAREQCTL	BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MCI_DPSM_ST_DBOOTMODEEN	BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MCI_DPSM_ST_BUSYMODE	BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MCI_DPSM_ST_DDRMODE	BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Control register extensions in the Qualcomm versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MCI_DPSM_QCOM_DATA_PEND	BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Control register extensions in STM32 versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MCI_DPSM_STM32_MODE_BLOCK	(0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MCI_DPSM_STM32_MODE_SDIO	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MCI_DPSM_STM32_MODE_STREAM	(2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MCI_DPSM_STM32_MODE_BLOCK_STOP	(3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MMCIDATACNT		0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MMCISTATUS		0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MCI_CMDCRCFAIL		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MCI_DATACRCFAIL		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MCI_CMDTIMEOUT		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MCI_DATATIMEOUT		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MCI_TXUNDERRUN		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MCI_RXOVERRUN		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MCI_CMDRESPEND		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MCI_CMDSENT		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MCI_DATAEND		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MCI_STARTBITERR		(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MCI_DATABLOCKEND	(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MCI_CMDACTIVE		(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MCI_TXACTIVE		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MCI_RXACTIVE		(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MCI_TXFIFOHALFEMPTY	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MCI_RXFIFOHALFFULL	(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MCI_TXFIFOFULL		(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MCI_RXFIFOFULL		(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MCI_TXFIFOEMPTY		(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MCI_RXFIFOEMPTY		(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MCI_TXDATAAVLBL		(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MCI_RXDATAAVLBL		(1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Extended status bits for the ST Micro variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MCI_ST_SDIOIT		(1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MCI_ST_CEATAEND		(1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MCI_ST_CARDBUSY		(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Extended status bits for the STM32 variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MCI_STM32_BUSYD0	BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MCI_STM32_BUSYD0END	BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MCI_STM32_VSWEND	BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MMCICLEAR		0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MCI_CMDCRCFAILCLR	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MCI_DATACRCFAILCLR	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MCI_CMDTIMEOUTCLR	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MCI_DATATIMEOUTCLR	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MCI_TXUNDERRUNCLR	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MCI_RXOVERRUNCLR	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MCI_CMDRESPENDCLR	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MCI_CMDSENTCLR		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MCI_DATAENDCLR		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MCI_STARTBITERRCLR	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MCI_DATABLOCKENDCLR	(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Extended status bits for the ST Micro variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MCI_ST_SDIOITC		(1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MCI_ST_CEATAENDC	(1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MCI_ST_BUSYENDC		(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Extended clear bits for the STM32 variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MCI_STM32_VSWENDC	BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MCI_STM32_CKSTOPC	BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MMCIMASK0		0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MCI_CMDCRCFAILMASK	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MCI_DATACRCFAILMASK	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MCI_CMDTIMEOUTMASK	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MCI_DATATIMEOUTMASK	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MCI_TXUNDERRUNMASK	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MCI_RXOVERRUNMASK	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MCI_CMDRESPENDMASK	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MCI_CMDSENTMASK		(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MCI_DATAENDMASK		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MCI_STARTBITERRMASK	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MCI_DATABLOCKENDMASK	(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MCI_CMDACTIVEMASK	(1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MCI_TXACTIVEMASK	(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MCI_RXACTIVEMASK	(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MCI_TXFIFOHALFEMPTYMASK	(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MCI_RXFIFOHALFFULLMASK	(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MCI_TXFIFOFULLMASK	(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MCI_RXFIFOFULLMASK	(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MCI_TXFIFOEMPTYMASK	(1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MCI_RXFIFOEMPTYMASK	(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MCI_TXDATAAVLBLMASK	(1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MCI_RXDATAAVLBLMASK	(1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Extended status bits for the ST Micro variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MCI_ST_SDIOITMASK	(1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MCI_ST_CEATAENDMASK	(1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MCI_ST_BUSYENDMASK	(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Extended status bits for the STM32 variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MCI_STM32_BUSYD0ENDMASK	BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MMCIMASK1		0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MMCIFIFOCNT		0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MMCIFIFO		0x080 /* to 0x0bc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* STM32 sdmmc registers for IDMA (Internal DMA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MMCI_STM32_IDMACTRLR	0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MMCI_STM32_IDMAEN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MMCI_STM32_IDMALLIEN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MMCI_STM32_IDMABSIZER		0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MMCI_STM32_IDMABNDT_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MMCI_STM32_IDMABNDT_MASK	GENMASK(12, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MMCI_STM32_IDMABASE0R	0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MMCI_STM32_IDMALAR	0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MMCI_STM32_IDMALA_MASK	GENMASK(13, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MMCI_STM32_ABR		BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MMCI_STM32_ULS		BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MMCI_STM32_ULA		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MMCI_STM32_IDMABAR	0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MCI_IRQENABLE	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	(MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	MCI_CMDRESPENDMASK | MCI_CMDSENTMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* These interrupts are directed to IRQ1 when two IRQ lines are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MCI_IRQ_PIO_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	(MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	 MCI_TXFIFOHALFEMPTYMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MCI_IRQ_PIO_STM32_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	(MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define NR_SG		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct mmci_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  * struct variant_data - MMCI variant-specific quirks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  * @clkreg: default value for MCICLOCK register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  * @clkreg_enable: enable value for MMCICLOCK register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  * @clkreg_8bit_bus_enable: enable value for 8 bit bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  * @cmdreg_cpsm_enable: enable value for CPSM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * @cmdreg_lrsp_crc: enable value for long response with crc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * @cmdreg_srsp_crc: enable value for short response with crc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * @cmdreg_srsp: enable value for short response without crc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * @cmdreg_stop: enable value for stop and abort transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  * @datalength_bits: number of bits in the MMCIDATALENGTH register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  *	      is asserted (likewise for RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  *		  is asserted (likewise for RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  * @data_cmd_enable: enable value for data commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  * @st_sdio: enable ST specific SDIO logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  * @st_clkdiv: true if using a ST-specific clock divider algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)  * @stm32_clkdiv: true if using a STM32-specific clock divider algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  * @datactrl_mask_sdio: SDIO enable mask in datactrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  * @datactrl_blocksz: block size in power of two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  * @datactrl_any_blocksz: true if block any block sizes are accepted by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  *		  hardware, such as with some SDIO traffic that send
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  *		  odd packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  * @dma_power_of_2: DMA only works with blocks that are a power of 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)  * @datactrl_first: true if data must be setup before send command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)  * @datacnt_useless: true if you could not use datacnt register to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)  *		     remaining data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)  * @pwrreg_powerup: power up value for MMCIPOWER register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)  * @f_max: maximum clk frequency supported by the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)  * @signal_direction: input/out direction of bus signals can be indicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)  * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)  * @busy_detect: true if the variant supports busy detection on DAT0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)  * @busy_timeout: true if the variant starts data timer when the DPSM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)  *		  enter in Wait_R or Busy state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)  * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)  * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  *		      indicating that the card is busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)  *		      getting busy end detection interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)  * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)  * @explicit_mclk_control: enable explicit mclk control in driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)  * @qcom_fifo: enables qcom specific fifo pio read logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  * @qcom_dml: enables qcom specific dma glue for dma transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)  * @reversed_irq_handling: handle data irq before cmd irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)  * @mmcimask1: true if variant have a MMCIMASK1 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)  * @irq_pio_mask: bitmask used to manage interrupt pio transfert in mmcimask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)  *		  register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)  * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)  *	       register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)  * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)  * @dma_lli: true if variant has dma link list feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct variant_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	unsigned int		clkreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	unsigned int		clkreg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	unsigned int		clkreg_8bit_bus_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	unsigned int		clkreg_neg_edge_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	unsigned int		cmdreg_cpsm_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	unsigned int		cmdreg_lrsp_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	unsigned int		cmdreg_srsp_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	unsigned int		cmdreg_srsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	unsigned int		cmdreg_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	unsigned int		datalength_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	unsigned int		fifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	unsigned int		fifohalfsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	unsigned int		data_cmd_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	unsigned int		datactrl_mask_ddrmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	unsigned int		datactrl_mask_sdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	unsigned int		datactrl_blocksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	u8			datactrl_any_blocksz:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	u8			dma_power_of_2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	u8			datactrl_first:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	u8			datacnt_useless:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	u8			st_sdio:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	u8			st_clkdiv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	u8			stm32_clkdiv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	u32			pwrreg_powerup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	u32			f_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	u8			signal_direction:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	u8			pwrreg_clkgate:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	u8			busy_detect:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	u8			busy_timeout:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	u32			busy_dpsm_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	u32			busy_detect_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	u32			busy_detect_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	u8			pwrreg_nopower:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	u8			explicit_mclk_control:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	u8			qcom_fifo:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	u8			qcom_dml:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	u8			reversed_irq_handling:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	u8			mmcimask1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	unsigned int		irq_pio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	u32			start_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	u32			opendrain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	u8			dma_lli:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	u32			stm32_idmabsize_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	void (*init)(struct mmci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* mmci variant callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct mmci_host_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	int (*validate_data)(struct mmci_host *host, struct mmc_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	int (*prep_data)(struct mmci_host *host, struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			 bool next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	void (*unprep_data)(struct mmci_host *host, struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			    int err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	u32 (*get_datactrl_cfg)(struct mmci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	void (*get_next_data)(struct mmci_host *host, struct mmc_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	int (*dma_setup)(struct mmci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	void (*dma_release)(struct mmci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	int (*dma_start)(struct mmci_host *host, unsigned int *datactrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	void (*dma_finalize)(struct mmci_host *host, struct mmc_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	void (*dma_error)(struct mmci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	void (*set_clkreg)(struct mmci_host *host, unsigned int desired);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	void (*set_pwrreg)(struct mmci_host *host, unsigned int pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	bool (*busy_complete)(struct mmci_host *host, u32 status, u32 err_msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	void (*pre_sig_volt_switch)(struct mmci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	int (*post_sig_volt_switch)(struct mmci_host *host, struct mmc_ios *ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct mmci_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	phys_addr_t		phybase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	void __iomem		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	struct mmc_request	*mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	struct mmc_command	*cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	struct mmc_command	stop_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	struct mmc_data		*data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	struct mmc_host		*mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	struct clk		*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	u8			singleirq:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	struct reset_control	*rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	spinlock_t		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	unsigned int		mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	/* cached value of requested clk in set_ios */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	unsigned int		clock_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	unsigned int		cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	u32			pwr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	u32			pwr_reg_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	u32			clk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	u32			clk_reg_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	u32			datactrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	u32			busy_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	u32			mask1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	u8			vqmmc_enabled:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	struct mmci_platform_data *plat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	struct mmc_host_ops	*mmc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	struct mmci_host_ops	*ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	struct variant_data	*variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	void			*variant_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	struct pinctrl		*pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	struct pinctrl_state	*pins_opendrain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	u8			hw_designer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	u8			hw_revision:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	struct timer_list	timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	unsigned int		oldstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	u32			irq_action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	/* pio stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	struct sg_mapping_iter	sg_miter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	unsigned int		size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	u8			use_dma:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	u8			dma_in_progress:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	void			*dma_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	s32			next_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define dma_inprogress(host)	((host)->dma_in_progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) void mmci_write_clkreg(struct mmci_host *host, u32 clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) void mmci_write_pwrreg(struct mmci_host *host, u32 pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static inline u32 mmci_dctrl_blksz(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	return (ffs(host->data->blksz) - 1) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #ifdef CONFIG_DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 			bool next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) void mmci_dmae_unprep_data(struct mmci_host *host, struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 			   int err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int mmci_dmae_setup(struct mmci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) void mmci_dmae_release(struct mmci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) void mmci_dmae_error(struct mmci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #ifdef CONFIG_MMC_QCOM_DML
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) void qcom_variant_init(struct mmci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static inline void qcom_variant_init(struct mmci_host *host) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #ifdef CONFIG_MMC_STM32_SDMMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) void sdmmc_variant_init(struct mmci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static inline void sdmmc_variant_init(struct mmci_host *host) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #endif