^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 ST-Ericsson SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mmc/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mmc/card.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mmc/sd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/amba/bus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/amba/mmci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/div64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "mmci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRIVER_NAME "mmci-pl18x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void mmci_variant_init(struct mmci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void ux500_variant_init(struct mmci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void ux500v2_variant_init(struct mmci_host *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static unsigned int fmax = 515633;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct variant_data variant_arm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .fifosize = 16 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .fifohalfsize = 8 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .cmdreg_srsp = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .datalength_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .datactrl_blocksz = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .pwrreg_powerup = MCI_PWR_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .f_max = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .reversed_irq_handling = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .mmcimask1 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .irq_pio_mask = MCI_IRQ_PIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .start_err = MCI_STARTBITERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .opendrain = MCI_ROD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .init = mmci_variant_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static struct variant_data variant_arm_extended_fifo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .fifosize = 128 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .fifohalfsize = 64 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .cmdreg_srsp = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .datalength_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .datactrl_blocksz = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .pwrreg_powerup = MCI_PWR_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .f_max = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .mmcimask1 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .irq_pio_mask = MCI_IRQ_PIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .start_err = MCI_STARTBITERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .opendrain = MCI_ROD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .init = mmci_variant_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static struct variant_data variant_arm_extended_fifo_hwfc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .fifosize = 128 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .fifohalfsize = 64 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .clkreg_enable = MCI_ARM_HWFCEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .cmdreg_srsp = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .datalength_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .datactrl_blocksz = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .pwrreg_powerup = MCI_PWR_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .f_max = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .mmcimask1 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .irq_pio_mask = MCI_IRQ_PIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .start_err = MCI_STARTBITERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .opendrain = MCI_ROD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .init = mmci_variant_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct variant_data variant_u300 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .fifosize = 16 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .fifohalfsize = 8 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .clkreg_enable = MCI_ST_U300_HWFCEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .cmdreg_srsp = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .datalength_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .datactrl_blocksz = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .st_sdio = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .pwrreg_powerup = MCI_PWR_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .f_max = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .signal_direction = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .pwrreg_clkgate = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .pwrreg_nopower = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .mmcimask1 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .irq_pio_mask = MCI_IRQ_PIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .start_err = MCI_STARTBITERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .opendrain = MCI_OD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .init = mmci_variant_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct variant_data variant_nomadik = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .fifosize = 16 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .fifohalfsize = 8 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .clkreg = MCI_CLK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .cmdreg_srsp = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .datalength_bits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .datactrl_blocksz = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .st_sdio = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .st_clkdiv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .pwrreg_powerup = MCI_PWR_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .f_max = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .signal_direction = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .pwrreg_clkgate = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .pwrreg_nopower = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .mmcimask1 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .irq_pio_mask = MCI_IRQ_PIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .start_err = MCI_STARTBITERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .opendrain = MCI_OD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .init = mmci_variant_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct variant_data variant_ux500 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .fifosize = 30 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .fifohalfsize = 8 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .clkreg = MCI_CLK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .clkreg_enable = MCI_ST_UX500_HWFCEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .cmdreg_srsp = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .datalength_bits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .datactrl_blocksz = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .datactrl_any_blocksz = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .dma_power_of_2 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .st_sdio = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .st_clkdiv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .pwrreg_powerup = MCI_PWR_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .f_max = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .signal_direction = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .pwrreg_clkgate = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .busy_detect = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .busy_detect_flag = MCI_ST_CARDBUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .busy_detect_mask = MCI_ST_BUSYENDMASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .pwrreg_nopower = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .mmcimask1 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .irq_pio_mask = MCI_IRQ_PIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .start_err = MCI_STARTBITERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .opendrain = MCI_OD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .init = ux500_variant_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static struct variant_data variant_ux500v2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .fifosize = 30 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .fifohalfsize = 8 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .clkreg = MCI_CLK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .clkreg_enable = MCI_ST_UX500_HWFCEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .cmdreg_srsp = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .datalength_bits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .datactrl_blocksz = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .datactrl_any_blocksz = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .dma_power_of_2 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .st_sdio = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .st_clkdiv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .pwrreg_powerup = MCI_PWR_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .f_max = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .signal_direction = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .pwrreg_clkgate = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .busy_detect = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .busy_detect_flag = MCI_ST_CARDBUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .busy_detect_mask = MCI_ST_BUSYENDMASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .pwrreg_nopower = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .mmcimask1 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .irq_pio_mask = MCI_IRQ_PIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .start_err = MCI_STARTBITERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .opendrain = MCI_OD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .init = ux500v2_variant_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct variant_data variant_stm32 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .fifosize = 32 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .fifohalfsize = 8 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .clkreg = MCI_CLK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .clkreg_enable = MCI_ST_UX500_HWFCEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .cmdreg_srsp = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .irq_pio_mask = MCI_IRQ_PIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .datalength_bits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .datactrl_blocksz = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .st_sdio = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .st_clkdiv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .pwrreg_powerup = MCI_PWR_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .f_max = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .pwrreg_clkgate = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .pwrreg_nopower = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .init = mmci_variant_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct variant_data variant_stm32_sdmmc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .fifosize = 16 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .fifohalfsize = 8 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .f_max = 208000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .stm32_clkdiv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .cmdreg_srsp = MCI_CPSM_STM32_SRSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .datactrl_first = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .datacnt_useless = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .datalength_bits = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .datactrl_blocksz = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .datactrl_any_blocksz = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .stm32_idmabsize_mask = GENMASK(12, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .busy_timeout = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .busy_detect = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .busy_detect_flag = MCI_STM32_BUSYD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .init = sdmmc_variant_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct variant_data variant_stm32_sdmmcv2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .fifosize = 16 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .fifohalfsize = 8 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .f_max = 208000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .stm32_clkdiv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .cmdreg_srsp = MCI_CPSM_STM32_SRSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .datactrl_first = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .datacnt_useless = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .datalength_bits = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .datactrl_blocksz = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .datactrl_any_blocksz = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .stm32_idmabsize_mask = GENMASK(16, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .dma_lli = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .busy_timeout = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .busy_detect = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .busy_detect_flag = MCI_STM32_BUSYD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .busy_detect_mask = MCI_STM32_BUSYD0ENDMASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .init = sdmmc_variant_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static struct variant_data variant_qcom = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .fifosize = 16 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .fifohalfsize = 8 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .clkreg = MCI_CLK_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MCI_QCOM_CLK_SELECT_IN_FBCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .cmdreg_srsp = MCI_CPSM_RESPONSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .data_cmd_enable = MCI_CPSM_QCOM_DATCMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .datalength_bits = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .datactrl_blocksz = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .datactrl_any_blocksz = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .pwrreg_powerup = MCI_PWR_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .f_max = 208000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .explicit_mclk_control = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .qcom_fifo = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .qcom_dml = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .mmcimask1 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .irq_pio_mask = MCI_IRQ_PIO_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .start_err = MCI_STARTBITERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .opendrain = MCI_ROD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .init = qcom_variant_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Busy detection for the ST Micro variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int mmci_card_busy(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct mmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) busy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static void mmci_reg_delay(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * According to the spec, at least three feedback clock cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Worst delay time during card init is at 100 kHz => 30 us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * Worst delay time when up and running is at 25 MHz => 120 ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (host->cclk < 25000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) udelay(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ndelay(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * This must be called with host->lock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) void mmci_write_clkreg(struct mmci_host *host, u32 clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (host->clk_reg != clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) host->clk_reg = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) writel(clk, host->base + MMCICLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * This must be called with host->lock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (host->pwr_reg != pwr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) host->pwr_reg = pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) writel(pwr, host->base + MMCIPOWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * This must be called with host->lock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Keep busy mode in DPSM if enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (host->datactrl_reg != datactrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) host->datactrl_reg = datactrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) writel(datactrl, host->base + MMCIDATACTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * This must be called with host->lock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct variant_data *variant = host->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 clk = variant->clkreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Make sure cclk reflects the current calculated clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) host->cclk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (desired) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (variant->explicit_mclk_control) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) host->cclk = host->mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) } else if (desired >= host->mclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) clk = MCI_CLK_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (variant->st_clkdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) clk |= MCI_ST_UX500_NEG_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) host->cclk = host->mclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) } else if (variant->st_clkdiv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * DB8500 TRM says f = mclk / (clkdiv + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * => clkdiv = (mclk / f) - 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * Round the divider up so we don't exceed the max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) clk = DIV_ROUND_UP(host->mclk, desired) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (clk >= 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) clk = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) host->cclk = host->mclk / (clk + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * => clkdiv = mclk / (2 * f) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) clk = host->mclk / (2 * desired) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (clk >= 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) clk = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) host->cclk = host->mclk / (2 * (clk + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) clk |= variant->clkreg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) clk |= MCI_CLK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* This hasn't proven to be worthwhile */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* clk |= MCI_CLK_PWRSAVE; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Set actual clock for debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) host->mmc->actual_clock = host->cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) clk |= MCI_4BIT_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) clk |= variant->clkreg_8bit_bus_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) clk |= variant->clkreg_neg_edge_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mmci_write_clkreg(host, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static void mmci_dma_release(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (host->ops && host->ops->dma_release)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) host->ops->dma_release(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) host->use_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static void mmci_dma_setup(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (!host->ops || !host->ops->dma_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (host->ops->dma_setup(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* initialize pre request cookie */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) host->next_cookie = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) host->use_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * Validate mmc prerequisites
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int mmci_validate_data(struct mmci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct variant_data *variant = host->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!is_power_of_2(data->blksz) && !variant->datactrl_any_blocksz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) "unsupported block size (%d bytes)\n", data->blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (host->ops && host->ops->validate_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return host->ops->validate_data(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (!host->ops || !host->ops->prep_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) err = host->ops->prep_data(host, data, next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (next && !err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) data->host_cookie = ++host->next_cookie < 0 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 1 : host->next_cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (host->ops && host->ops->unprep_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) host->ops->unprep_data(host, data, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) data->host_cookie = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (host->ops && host->ops->get_next_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) host->ops->get_next_data(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int mmci_dma_start(struct mmci_host *host, unsigned int datactrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct mmc_data *data = host->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (!host->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ret = mmci_prep_data(host, data, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (!host->ops || !host->ops->dma_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Okay, go for it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_vdbg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) data->sg_len, data->blksz, data->blocks, data->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = host->ops->dma_start(host, &datactrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Trigger the DMA transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mmci_write_datactrlreg(host, datactrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * Let the MMCI say when the data is ended and it's time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * to fire next DMA request. When that happens, MMCI will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * call mmci_data_end()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) host->base + MMCIMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (!host->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (host->ops && host->ops->dma_finalize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) host->ops->dma_finalize(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static void mmci_dma_error(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (!host->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (host->ops && host->ops->dma_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) host->ops->dma_error(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) writel(0, host->base + MMCICOMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) BUG_ON(host->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) void __iomem *base = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct variant_data *variant = host->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (host->singleirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned int mask0 = readl(base + MMCIMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mask0 &= ~variant->irq_pio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) mask0 |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) writel(mask0, base + MMCIMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (variant->mmcimask1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) writel(mask, base + MMCIMASK1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) host->mask1_reg = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static void mmci_stop_data(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) mmci_write_datactrlreg(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) mmci_set_mask1(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) host->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) unsigned int flags = SG_MITER_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) flags |= SG_MITER_TO_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) flags |= SG_MITER_FROM_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static u32 mmci_get_dctrl_cfg(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return MCI_DPSM_ENABLE | (host->data->blksz << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static bool ux500_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) void __iomem *base = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * Before unmasking for the busy end IRQ, confirm that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * command was sent successfully. To keep track of having a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * command in-progress, waiting for busy signaling to end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * store the status in host->busy_status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Note that, the card may need a couple of clock cycles before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * it starts signaling busy on DAT0, hence re-read the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * MMCISTATUS register here, to allow the busy bit to be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * Potentially we may even need to poll the register for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * while, to allow it to be set, but tests indicates that it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * isn't needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (!host->busy_status && !(status & err_msk) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) writel(readl(base + MMCIMASK0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) host->variant->busy_detect_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) base + MMCIMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * If there is a command in-progress that has been successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * sent, then bail out if busy status is set and wait for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * busy end IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * Note that, the HW triggers an IRQ on both edges while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * monitoring DAT0 for busy completion, but there is only one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * status bit in MMCISTATUS for the busy state. Therefore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * both the start and the end interrupts needs to be cleared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * one after the other. So, clear the busy start IRQ here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (host->busy_status &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) (status & host->variant->busy_detect_flag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) writel(host->variant->busy_detect_mask, base + MMCICLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * If there is a command in-progress that has been successfully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * sent and the busy bit isn't set, it means we have received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * the busy end IRQ. Clear and mask the IRQ, then continue to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * process the command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (host->busy_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) writel(host->variant->busy_detect_mask, base + MMCICLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) writel(readl(base + MMCIMASK0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ~host->variant->busy_detect_mask, base + MMCIMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) host->busy_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * All the DMA operation mode stuff goes inside this ifdef.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * This assumes that you have a generic DMA device interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * no custom DMA interfaces are supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #ifdef CONFIG_DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct mmci_dmae_next {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct mmci_dmae_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct dma_chan *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct dma_chan *rx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct dma_chan *tx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct dma_async_tx_descriptor *desc_current;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct mmci_dmae_next next_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int mmci_dmae_setup(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) const char *rxname, *txname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct mmci_dmae_priv *dmae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (!dmae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) host->dma_priv = dmae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (IS_ERR(dmae->rx_channel)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) int ret = PTR_ERR(dmae->rx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dmae->rx_channel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (IS_ERR(dmae->tx_channel)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (PTR_ERR(dmae->tx_channel) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dev_warn(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) "Deferred probe for TX channel ignored\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dmae->tx_channel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * If only an RX channel is specified, the driver will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * attempt to use it bidirectionally, however if it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * is specified but cannot be located, DMA will be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (dmae->rx_channel && !dmae->tx_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dmae->tx_channel = dmae->rx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (dmae->rx_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) rxname = dma_chan_name(dmae->rx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) rxname = "none";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (dmae->tx_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) txname = dma_chan_name(dmae->tx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) txname = "none";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) rxname, txname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * Limit the maximum segment size in any SG entry according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * the parameters of the DMA engine device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (dmae->tx_channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct device *dev = dmae->tx_channel->device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) unsigned int max_seg_size = dma_get_max_seg_size(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (max_seg_size < host->mmc->max_seg_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) host->mmc->max_seg_size = max_seg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (dmae->rx_channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct device *dev = dmae->rx_channel->device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) unsigned int max_seg_size = dma_get_max_seg_size(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (max_seg_size < host->mmc->max_seg_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) host->mmc->max_seg_size = max_seg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (!dmae->tx_channel || !dmae->rx_channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) mmci_dmae_release(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * This is used in or so inline it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * so it can be discarded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) void mmci_dmae_release(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct mmci_dmae_priv *dmae = host->dma_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (dmae->rx_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dma_release_channel(dmae->rx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (dmae->tx_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dma_release_channel(dmae->tx_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dmae->rx_channel = dmae->tx_channel = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct mmci_dmae_priv *dmae = host->dma_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) chan = dmae->rx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) chan = dmae->tx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) void mmci_dmae_error(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct mmci_dmae_priv *dmae = host->dma_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (!dma_inprogress(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dmaengine_terminate_all(dmae->cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) host->dma_in_progress = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dmae->cur = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) dmae->desc_current = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) host->data->host_cookie = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) mmci_dma_unmap(host, host->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct mmci_dmae_priv *dmae = host->dma_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (!dma_inprogress(host))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* Wait up to 1ms for the DMA to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) for (i = 0; ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) status = readl(host->base + MMCISTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * Check to see whether we still have some data left in the FIFO -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * this catches DMA controllers which are unable to monitor the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * contiguous buffers. On TX, we'll get a FIFO underrun error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (status & MCI_RXDATAAVLBLMASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) mmci_dma_error(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (!data->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) data->error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) } else if (!data->host_cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mmci_dma_unmap(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * Use of DMA with scatter-gather is impossible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * Give up with DMA and switch back to PIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (status & MCI_RXDATAAVLBLMASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) mmci_dma_release(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) host->dma_in_progress = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dmae->cur = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dmae->desc_current = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct dma_chan **dma_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct dma_async_tx_descriptor **dma_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct mmci_dmae_priv *dmae = host->dma_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct variant_data *variant = host->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct dma_slave_config conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .src_addr = host->phybase + MMCIFIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .dst_addr = host->phybase + MMCIFIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .device_fc = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct dma_device *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct dma_async_tx_descriptor *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) int nr_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) unsigned long flags = DMA_CTRL_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (data->flags & MMC_DATA_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) conf.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) chan = dmae->rx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) conf.direction = DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) chan = dmae->tx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* If there's no DMA channel, fall back to PIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* If less than or equal to the fifo size, don't bother with DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (data->blksz * data->blocks <= variant->fifosize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * This is necessary to get SDIO working on the Ux500. We do not yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * know if this is a bug in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * - The Ux500 DMA controller (DMA40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * - The MMCI DMA interface on the Ux500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * some power of two blocks (such as 64 bytes) are sent regularly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * during SDIO traffic and those work fine so for these we enable DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) device = chan->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (nr_sg == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (host->variant->qcom_dml)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) flags |= DMA_PREP_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) dmaengine_slave_config(chan, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) conf.direction, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) goto unmap_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) *dma_chan = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) *dma_desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) unmap_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dma_unmap_sg(device->dev, data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) int mmci_dmae_prep_data(struct mmci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) bool next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct mmci_dmae_priv *dmae = host->dma_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct mmci_dmae_next *nd = &dmae->next_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (!host->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* Check if next job is already prepared. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (dmae->cur && dmae->desc_current)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* No job were prepared thus do it now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return _mmci_dmae_prep_data(host, data, &dmae->cur,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) &dmae->desc_current);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct mmci_dmae_priv *dmae = host->dma_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) host->dma_in_progress = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ret = dma_submit_error(dmaengine_submit(dmae->desc_current));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) host->dma_in_progress = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) dma_async_issue_pending(dmae->cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) *datactrl |= MCI_DPSM_DMAENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct mmci_dmae_priv *dmae = host->dma_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct mmci_dmae_next *next = &dmae->next_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (!host->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) WARN_ON(!data->host_cookie && (next->desc || next->chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dmae->desc_current = next->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) dmae->cur = next->chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) next->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) next->chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) void mmci_dmae_unprep_data(struct mmci_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct mmc_data *data, int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct mmci_dmae_priv *dmae = host->dma_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (!host->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) mmci_dma_unmap(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct mmci_dmae_next *next = &dmae->next_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (data->flags & MMC_DATA_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) chan = dmae->rx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) chan = dmae->tx_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) dmaengine_terminate_all(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (dmae->desc_current == next->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) dmae->desc_current = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (dmae->cur == next->chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) host->dma_in_progress = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dmae->cur = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) next->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) next->chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static struct mmci_host_ops mmci_variant_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .prep_data = mmci_dmae_prep_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .unprep_data = mmci_dmae_unprep_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .get_datactrl_cfg = mmci_get_dctrl_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .get_next_data = mmci_dmae_get_next_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .dma_setup = mmci_dmae_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .dma_release = mmci_dmae_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .dma_start = mmci_dmae_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .dma_finalize = mmci_dmae_finalize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .dma_error = mmci_dmae_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static struct mmci_host_ops mmci_variant_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .get_datactrl_cfg = mmci_get_dctrl_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static void mmci_variant_init(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) host->ops = &mmci_variant_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static void ux500_variant_init(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) host->ops = &mmci_variant_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) host->ops->busy_complete = ux500_busy_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static void ux500v2_variant_init(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) host->ops = &mmci_variant_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) host->ops->busy_complete = ux500_busy_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct mmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct mmc_data *data = mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) WARN_ON(data->host_cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (mmci_validate_data(host, data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) mmci_prep_data(host, data, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct mmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct mmc_data *data = mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (!data || !data->host_cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) mmci_unprep_data(host, data, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct variant_data *variant = host->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) unsigned int datactrl, timeout, irqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) unsigned long long clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) data->blksz, data->blocks, data->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) host->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) host->size = data->blksz * data->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) data->bytes_xfered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) clks = (unsigned long long)data->timeout_ns * host->cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) do_div(clks, NSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) timeout = data->timeout_clks + (unsigned int)clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) base = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) writel(timeout, base + MMCIDATATIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) writel(host->size, base + MMCIDATALENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) datactrl = host->ops->get_datactrl_cfg(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) u32 clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) datactrl |= variant->datactrl_mask_sdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * The ST Micro variant for SDIO small write transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * needs to have clock H/W flow control disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * otherwise the transfer will not start. The threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * depends on the rate of MCLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) (host->size < 8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) (host->size <= 8 && host->mclk > 50000000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) clk = host->clk_reg & ~variant->clkreg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) clk = host->clk_reg | variant->clkreg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) mmci_write_clkreg(host, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) datactrl |= variant->datactrl_mask_ddrmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * Attempt to use DMA operation mode, if this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * should fail, fall back to PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (!mmci_dma_start(host, datactrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* IRQ mode, map the SG list for CPU reading/writing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) mmci_init_sg(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (data->flags & MMC_DATA_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) irqmask = MCI_RXFIFOHALFFULLMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * If we have less than the fifo 'half-full' threshold to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * transfer, trigger a PIO interrupt as soon as any data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (host->size < variant->fifohalfsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) irqmask |= MCI_RXDATAAVLBLMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * We don't actually need to include "FIFO empty" here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * since its implicit in "FIFO half empty".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) irqmask = MCI_TXFIFOHALFEMPTYMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) mmci_write_datactrlreg(host, datactrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) mmci_set_mask1(host, irqmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) void __iomem *base = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) unsigned long long clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) cmd->opcode, cmd->arg, cmd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) writel(0, base + MMCICOMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) mmci_reg_delay(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (host->variant->cmdreg_stop &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) cmd->opcode == MMC_STOP_TRANSMISSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) c |= host->variant->cmdreg_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) c |= cmd->opcode | host->variant->cmdreg_cpsm_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (cmd->flags & MMC_RSP_136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) c |= host->variant->cmdreg_lrsp_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) else if (cmd->flags & MMC_RSP_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) c |= host->variant->cmdreg_srsp_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) c |= host->variant->cmdreg_srsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (host->variant->busy_timeout && cmd->flags & MMC_RSP_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (!cmd->busy_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) cmd->busy_timeout = 10 * MSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (cmd->busy_timeout > host->mmc->max_busy_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) clks = (unsigned long long)host->mmc->max_busy_timeout * host->cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) clks = (unsigned long long)cmd->busy_timeout * host->cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) do_div(clks, MSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) writel_relaxed(clks, host->base + MMCIDATATIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (host->ops->pre_sig_volt_switch && cmd->opcode == SD_SWITCH_VOLTAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) host->ops->pre_sig_volt_switch(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (/*interrupt*/0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) c |= MCI_CPSM_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) c |= host->variant->data_cmd_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) host->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) writel(cmd->arg, base + MMCIARGUMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) writel(c, base + MMCICOMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static void mmci_stop_command(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) host->stop_abort.error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) mmci_start_command(host, &host->stop_abort, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) unsigned int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) unsigned int status_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /* Make sure we have data to handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /* First check for errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) status_err = status & (host->variant->start_err |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) MCI_DATACRCFAIL | MCI_DATATIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) MCI_TXUNDERRUN | MCI_RXOVERRUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (status_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u32 remain, success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /* Terminate the DMA transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) mmci_dma_error(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * Calculate how far we are into the transfer. Note that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * the data counter gives the number of bytes transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * on the MMC bus, not on the host side. On reads, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * can be as much as a FIFO-worth of data ahead. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * matters for FIFO overruns only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (!host->variant->datacnt_useless) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) remain = readl(host->base + MMCIDATACNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) success = data->blksz * data->blocks - remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) success = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) status_err, success);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (status_err & MCI_DATACRCFAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* Last block was not successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) success -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) data->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) } else if (status_err & MCI_DATATIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) } else if (status_err & MCI_STARTBITERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) data->error = -ECOMM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) } else if (status_err & MCI_TXUNDERRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) data->error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) } else if (status_err & MCI_RXOVERRUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (success > host->variant->fifosize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) success -= host->variant->fifosize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) success = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) data->error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) data->bytes_xfered = round_down(success, data->blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (status & MCI_DATABLOCKEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (status & MCI_DATAEND || data->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) mmci_dma_finalize(host, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) mmci_stop_data(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (!data->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) /* The error clause is handled above, success! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) data->bytes_xfered = data->blksz * data->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (!data->stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (host->variant->cmdreg_stop && data->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) mmci_stop_command(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) mmci_request_end(host, data->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) } else if (host->mrq->sbc && !data->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) mmci_request_end(host, data->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) mmci_start_command(host, data->stop, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) unsigned int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) u32 err_msk = MCI_CMDCRCFAIL | MCI_CMDTIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) void __iomem *base = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) bool sbc, busy_resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (!cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) sbc = (cmd == host->mrq->sbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) busy_resp = !!(cmd->flags & MMC_RSP_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * We need to be one of these interrupts to be considered worth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * handling. Note that we tag on any latent IRQs postponed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * due to waiting for busy status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (host->variant->busy_timeout && busy_resp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) err_msk |= MCI_DATATIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (!((status | host->busy_status) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) (err_msk | MCI_CMDSENT | MCI_CMDRESPEND)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /* Handle busy detection on DAT0 if the variant supports it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (busy_resp && host->variant->busy_detect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (!host->ops->busy_complete(host, status, err_msk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (status & MCI_CMDTIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) } else if (host->variant->busy_timeout && busy_resp &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) status & MCI_DATATIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) host->irq_action = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) cmd->resp[0] = readl(base + MMCIRESPONSE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) cmd->resp[1] = readl(base + MMCIRESPONSE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) cmd->resp[2] = readl(base + MMCIRESPONSE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) cmd->resp[3] = readl(base + MMCIRESPONSE3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if ((!sbc && !cmd->data) || cmd->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (host->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /* Terminate the DMA transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) mmci_dma_error(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) mmci_stop_data(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (host->variant->cmdreg_stop && cmd->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) mmci_stop_command(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (host->irq_action != IRQ_WAKE_THREAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) mmci_request_end(host, host->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) } else if (sbc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) mmci_start_command(host, host->mrq->cmd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) } else if (!host->variant->datactrl_first &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) !(cmd->data->flags & MMC_DATA_READ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) mmci_start_data(host, cmd->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return remain - (readl(host->base + MMCIFIFOCNT) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * from the fifo range should be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (status & MCI_RXFIFOHALFFULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return host->variant->fifohalfsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) else if (status & MCI_RXDATAAVLBL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) void __iomem *base = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) char *ptr = buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) u32 status = readl(host->base + MMCISTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) int host_remain = host->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) int count = host->get_rx_fifocnt(host, status, host_remain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (count > remain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) count = remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (count <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) * SDIO especially may want to send something that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) * not divisible by 4 (as opposed to card sectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) * etc). Therefore make sure to always read the last bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) * while only doing full 32-bit reads towards the FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (unlikely(count & 0x3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (count < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) unsigned char buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) ioread32_rep(base + MMCIFIFO, buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) memcpy(ptr, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) count &= ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) ptr += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) remain -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) host_remain -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (remain == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) status = readl(base + MMCISTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) } while (status & MCI_RXDATAAVLBL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return ptr - buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) struct variant_data *variant = host->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) void __iomem *base = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) char *ptr = buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) unsigned int count, maxcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) maxcnt = status & MCI_TXFIFOEMPTY ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) variant->fifosize : variant->fifohalfsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) count = min(remain, maxcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * SDIO especially may want to send something that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * not divisible by 4 (as opposed to card sectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) * etc), and the FIFO only accept full 32-bit writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) * So compensate by adding +3 on the count, a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) * byte become a 32bit write, 7 bytes will be two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) * 32bit writes etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) ptr += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) remain -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (remain == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) status = readl(base + MMCISTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) } while (status & MCI_TXFIFOHALFEMPTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) return ptr - buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * PIO data transfer IRQ handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) struct mmci_host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) struct sg_mapping_iter *sg_miter = &host->sg_miter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct variant_data *variant = host->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) void __iomem *base = host->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) status = readl(base + MMCISTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) unsigned int remain, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) char *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * For write, we only need to test the half-empty flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * here - if the FIFO is completely empty, then by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * definition it is more than half empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * For read, check for data available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (!sg_miter_next(sg_miter))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) buffer = sg_miter->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) remain = sg_miter->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (status & MCI_RXACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) len = mmci_pio_read(host, buffer, remain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (status & MCI_TXACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) len = mmci_pio_write(host, buffer, remain, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) sg_miter->consumed = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) host->size -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) remain -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (remain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) status = readl(base + MMCISTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) sg_miter_stop(sg_miter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) * If we have less than the fifo 'half-full' threshold to transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) * trigger a PIO interrupt as soon as any data is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) * If we run out of data, disable the data IRQs; this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) * prevents a race where the FIFO becomes empty before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) * the chip itself has disabled the data path, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) * stops us racing with our data end IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) if (host->size == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) mmci_set_mask1(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) * Handle completion of command and data transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static irqreturn_t mmci_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) struct mmci_host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) spin_lock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) host->irq_action = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) status = readl(host->base + MMCISTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (host->singleirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (status & host->mask1_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) mmci_pio_irq(irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) status &= ~host->variant->irq_pio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) * Busy detection is managed by mmci_cmd_irq(), including to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) * clear the corresponding IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) status &= readl(host->base + MMCIMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (host->variant->busy_detect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) writel(status & ~host->variant->busy_detect_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) host->base + MMCICLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) writel(status, host->base + MMCICLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (host->variant->reversed_irq_handling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) mmci_data_irq(host, host->data, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) mmci_cmd_irq(host, host->cmd, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) mmci_cmd_irq(host, host->cmd, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) mmci_data_irq(host, host->data, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * Busy detection has been handled by mmci_cmd_irq() above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * Clear the status bit to prevent polling in IRQ context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if (host->variant->busy_detect_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) status &= ~host->variant->busy_detect_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) } while (status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) spin_unlock(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) return host->irq_action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) * mmci_irq_thread() - A threaded IRQ handler that manages a reset of the HW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * A reset is needed for some variants, where a datatimeout for a R1B request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * causes the DPSM to stay busy (non-functional).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static irqreturn_t mmci_irq_thread(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) struct mmci_host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (host->rst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) reset_control_assert(host->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) reset_control_deassert(host->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) writel(host->clk_reg, host->base + MMCICLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) writel(host->pwr_reg, host->base + MMCIPOWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) writel(MCI_IRQENABLE | host->variant->start_err,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) host->base + MMCIMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) host->irq_action = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) mmci_request_end(host, host->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return host->irq_action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) struct mmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) WARN_ON(host->mrq != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) mrq->cmd->error = mmci_validate_data(host, mrq->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (mrq->cmd->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) mmc_request_done(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) host->mrq = mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (mrq->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) mmci_get_next_data(host, mrq->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (mrq->data &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) mmci_start_data(host, mrq->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (mrq->sbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) mmci_start_command(host, mrq->sbc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) mmci_start_command(host, mrq->cmd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static void mmci_set_max_busy_timeout(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) struct mmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) u32 max_busy_timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (!host->variant->busy_detect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) if (host->variant->busy_timeout && mmc->actual_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) max_busy_timeout = ~0UL / (mmc->actual_clock / MSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) mmc->max_busy_timeout = max_busy_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) struct mmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) struct variant_data *variant = host->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) u32 pwr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (host->plat->ios_handler &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) host->plat->ios_handler(mmc_dev(mmc), ios))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) switch (ios->power_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) case MMC_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (!IS_ERR(mmc->supply.vmmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) regulator_disable(mmc->supply.vqmmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) host->vqmmc_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) case MMC_POWER_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (!IS_ERR(mmc->supply.vmmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) * and instead uses MCI_PWR_ON so apply whatever value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * configured in the variant data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) pwr |= variant->pwrreg_powerup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) case MMC_POWER_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) ret = regulator_enable(mmc->supply.vqmmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) dev_err(mmc_dev(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) "failed to enable vqmmc regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) host->vqmmc_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) pwr |= MCI_PWR_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * The ST Micro variant has some additional bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) * indicating signal direction for the signals in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) * the SD/MMC bus and feedback-clock usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) pwr |= host->pwr_reg_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) if (ios->bus_width == MMC_BUS_WIDTH_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) pwr &= ~MCI_ST_DATA74DIREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) else if (ios->bus_width == MMC_BUS_WIDTH_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) pwr &= (~MCI_ST_DATA74DIREN &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) ~MCI_ST_DATA31DIREN &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) ~MCI_ST_DATA2DIREN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (variant->opendrain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) pwr |= variant->opendrain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) * If the variant cannot configure the pads by its own, then we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) * expect the pinctrl to be able to do that for us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) pinctrl_select_state(host->pinctrl, host->pins_opendrain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) pinctrl_select_default_state(mmc_dev(mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) * If clock = 0 and the variant requires the MMCIPOWER to be used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) * gating the clock, the MCI_PWR_ON bit is cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (!ios->clock && variant->pwrreg_clkgate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) pwr &= ~MCI_PWR_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (host->variant->explicit_mclk_control &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) ios->clock != host->clock_cache) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) ret = clk_set_rate(host->clk, ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) dev_err(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) "Error setting clock rate (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) host->mclk = clk_get_rate(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) host->clock_cache = ios->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if (host->ops && host->ops->set_clkreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) host->ops->set_clkreg(host, ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) mmci_set_clkreg(host, ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) mmci_set_max_busy_timeout(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (host->ops && host->ops->set_pwrreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) host->ops->set_pwrreg(host, pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) mmci_write_pwrreg(host, pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) mmci_reg_delay(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static int mmci_get_cd(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) struct mmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct mmci_platform_data *plat = host->plat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) unsigned int status = mmc_gpio_get_cd(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (status == -ENOSYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) if (!plat->status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) return 1; /* Assume always present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) status = plat->status(mmc_dev(host->mmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) struct mmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) ret = mmc_regulator_set_vqmmc(mmc, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) if (!ret && host->ops && host->ops->post_sig_volt_switch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) ret = host->ops->post_sig_volt_switch(host, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) else if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) static struct mmc_host_ops mmci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .request = mmci_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .pre_req = mmci_pre_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .post_req = mmci_post_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .set_ios = mmci_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .get_ro = mmc_gpio_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .get_cd = mmci_get_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .start_signal_voltage_switch = mmci_sig_volt_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) struct mmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) int ret = mmc_of_parse(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) if (of_get_property(np, "st,sig-dir-dat0", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) host->pwr_reg_add |= MCI_ST_DATA0DIREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) if (of_get_property(np, "st,sig-dir-dat2", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) host->pwr_reg_add |= MCI_ST_DATA2DIREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (of_get_property(np, "st,sig-dir-dat31", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) host->pwr_reg_add |= MCI_ST_DATA31DIREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) if (of_get_property(np, "st,sig-dir-dat74", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) host->pwr_reg_add |= MCI_ST_DATA74DIREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) if (of_get_property(np, "st,sig-dir-cmd", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) host->pwr_reg_add |= MCI_ST_CMDDIREN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (of_get_property(np, "st,sig-pin-fbclk", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) host->pwr_reg_add |= MCI_ST_FBCLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (of_get_property(np, "st,sig-dir", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) host->pwr_reg_add |= MCI_STM32_DIRPOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) if (of_get_property(np, "st,neg-edge", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) if (of_get_property(np, "st,use-ckin", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) host->clk_reg_add |= MCI_STM32_CLK_SELCKIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) mmc->caps |= MMC_CAP_SD_HIGHSPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static int mmci_probe(struct amba_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) const struct amba_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) struct mmci_platform_data *plat = dev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) struct device_node *np = dev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) struct variant_data *variant = id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) struct mmci_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /* Must have platform data or Device Tree. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) if (!plat && !np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) dev_err(&dev->dev, "No plat data or DT found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) if (!plat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (!plat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) if (!mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) ret = mmci_of_parse(np, mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) goto host_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) host->mmc = mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) host->mmc_ops = &mmci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) mmc->ops = &mmci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) * Some variant (STM32) doesn't have opendrain bit, nevertheless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) * pins can be set accordingly using pinctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) if (!variant->opendrain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) host->pinctrl = devm_pinctrl_get(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) if (IS_ERR(host->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) dev_err(&dev->dev, "failed to get pinctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) ret = PTR_ERR(host->pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) goto host_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) host->pins_opendrain = pinctrl_lookup_state(host->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) MMCI_PINCTRL_STATE_OPENDRAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (IS_ERR(host->pins_opendrain)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) dev_err(mmc_dev(mmc), "Can't select opendrain pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ret = PTR_ERR(host->pins_opendrain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) goto host_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) host->hw_designer = amba_manf(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) host->hw_revision = amba_rev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) host->clk = devm_clk_get(&dev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) if (IS_ERR(host->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) ret = PTR_ERR(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) goto host_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) ret = clk_prepare_enable(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) goto host_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (variant->qcom_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) host->get_rx_fifocnt = mmci_get_rx_fifocnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) host->plat = plat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) host->variant = variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) host->mclk = clk_get_rate(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) * According to the spec, mclk is max 100 MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) * so we try to adjust the clock down to this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) * (if possible).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) if (host->mclk > variant->f_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) ret = clk_set_rate(host->clk, variant->f_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) host->mclk = clk_get_rate(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) host->mclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) host->phybase = dev->res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) host->base = devm_ioremap_resource(&dev->dev, &dev->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) if (IS_ERR(host->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) ret = PTR_ERR(host->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (variant->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) variant->init(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) * The ARM and ST versions of the block have slightly different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) * clock divider equations which means that the minimum divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) * differs too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) * on Qualcomm like controllers get the nearest minimum clock to 100Khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) if (variant->st_clkdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) else if (variant->stm32_clkdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) mmc->f_min = DIV_ROUND_UP(host->mclk, 2046);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) else if (variant->explicit_mclk_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) mmc->f_min = clk_round_rate(host->clk, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) * If no maximum operating frequency is supplied, fall back to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) * the module parameter, which has a (low) default value in case it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) * is not specified. Either value must not exceed the clock rate into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) * the block, of course.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) if (mmc->f_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) mmc->f_max = variant->explicit_mclk_control ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) min(variant->f_max, mmc->f_max) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) min(host->mclk, mmc->f_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) mmc->f_max = variant->explicit_mclk_control ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) fmax : min(host->mclk, fmax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (IS_ERR(host->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) ret = PTR_ERR(host->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) /* Get regulators and the supported OCR mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) ret = mmc_regulator_get_supply(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) if (!mmc->ocr_avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) mmc->ocr_avail = plat->ocr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) else if (plat->ocr_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) /* We support these capabilities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) mmc->caps |= MMC_CAP_CMD23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) * Enable busy detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) if (variant->busy_detect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) mmci_ops.card_busy = mmci_card_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) * Not all variants have a flag to enable busy detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) * in the DPSM, but if they do, set it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (variant->busy_dpsm_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) mmci_write_datactrlreg(host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) host->variant->busy_dpsm_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) /* Variants with mandatory busy timeout in HW needs R1B responses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if (variant->busy_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) /* Prepare a CMD12 - needed to clear the DPSM on some variants. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) host->stop_abort.opcode = MMC_STOP_TRANSMISSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) host->stop_abort.arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) /* We support these PM capabilities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) mmc->pm_caps |= MMC_PM_KEEP_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) * We can do SGIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) mmc->max_segs = NR_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) * Since only a certain number of bits are valid in the data length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) * register, we must ensure that we don't exceed 2^num-1 bytes in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) * single request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) mmc->max_req_size = (1 << variant->datalength_bits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) * Set the maximum segment size. Since we aren't doing DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) * (yet) we are only limited by the data length register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) mmc->max_seg_size = mmc->max_req_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) * Block size can be up to 2048 bytes, but must be a power of two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) mmc->max_blk_size = 1 << variant->datactrl_blocksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) * Limit the number of blocks transferred so that we don't overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) * the maximum request size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) spin_lock_init(&host->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) writel(0, host->base + MMCIMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) if (variant->mmcimask1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) writel(0, host->base + MMCIMASK1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) writel(0xfff, host->base + MMCICLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) * If:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) * - not using DT but using a descriptor table, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) * - using a table of descriptors ALONGSIDE DT, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) * look up these descriptors named "cd" and "wp" right here, fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) * silently of these do not exist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) ret = devm_request_threaded_irq(&dev->dev, dev->irq[0], mmci_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) mmci_irq_thread, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) DRIVER_NAME " (cmd)", host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) if (!dev->irq[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) host->singleirq = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) IRQF_SHARED, DRIVER_NAME " (pio)", host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) amba_set_drvdata(dev, mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) amba_rev(dev), (unsigned long long)dev->res.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) dev->irq[0], dev->irq[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) mmci_dma_setup(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) pm_runtime_set_autosuspend_delay(&dev->dev, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) pm_runtime_use_autosuspend(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) pm_runtime_put(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) clk_disable_unprepare(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) host_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) static void mmci_remove(struct amba_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) struct mmc_host *mmc = amba_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) if (mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) struct mmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) struct variant_data *variant = host->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) * Undo pm_runtime_put() in probe. We use the _sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) * version here so that we can access the primecell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) pm_runtime_get_sync(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) mmc_remove_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) writel(0, host->base + MMCIMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) if (variant->mmcimask1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) writel(0, host->base + MMCIMASK1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) writel(0, host->base + MMCICOMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) writel(0, host->base + MMCIDATACTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) mmci_dma_release(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) clk_disable_unprepare(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) static void mmci_save(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) writel(0, host->base + MMCIMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) if (host->variant->pwrreg_nopower) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) writel(0, host->base + MMCIDATACTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) writel(0, host->base + MMCIPOWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) writel(0, host->base + MMCICLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) mmci_reg_delay(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) static void mmci_restore(struct mmci_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) spin_lock_irqsave(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) if (host->variant->pwrreg_nopower) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) writel(host->clk_reg, host->base + MMCICLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) writel(host->datactrl_reg, host->base + MMCIDATACTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) writel(host->pwr_reg, host->base + MMCIPOWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) writel(MCI_IRQENABLE | host->variant->start_err,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) host->base + MMCIMASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) mmci_reg_delay(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) spin_unlock_irqrestore(&host->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) static int mmci_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) struct amba_device *adev = to_amba_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) struct mmc_host *mmc = amba_get_drvdata(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) if (mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) struct mmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) mmci_save(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) clk_disable_unprepare(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) static int mmci_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) struct amba_device *adev = to_amba_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) struct mmc_host *mmc = amba_get_drvdata(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) if (mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) struct mmci_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) clk_prepare_enable(host->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) mmci_restore(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) pinctrl_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) static const struct dev_pm_ops mmci_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) static const struct amba_id mmci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .id = 0x00041180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .mask = 0xff0fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .data = &variant_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .id = 0x01041180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .mask = 0xff0fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .data = &variant_arm_extended_fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .id = 0x02041180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .mask = 0xff0fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .data = &variant_arm_extended_fifo_hwfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .id = 0x00041181,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .mask = 0x000fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .data = &variant_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) /* ST Micro variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .id = 0x00180180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .mask = 0x00ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .data = &variant_u300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .id = 0x10180180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) .mask = 0xf0ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .data = &variant_nomadik,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .id = 0x00280180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .mask = 0x00ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .data = &variant_nomadik,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .id = 0x00480180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .mask = 0xf0ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .data = &variant_ux500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .id = 0x10480180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .mask = 0xf0ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .data = &variant_ux500v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .id = 0x00880180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .mask = 0x00ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .data = &variant_stm32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .id = 0x10153180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .mask = 0xf0ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .data = &variant_stm32_sdmmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .id = 0x00253180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .mask = 0xf0ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .data = &variant_stm32_sdmmcv2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) /* Qualcomm variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .id = 0x00051180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .mask = 0x000fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .data = &variant_qcom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) MODULE_DEVICE_TABLE(amba, mmci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) static struct amba_driver mmci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .pm = &mmci_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .probe = mmci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .remove = mmci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .id_table = mmci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) module_amba_driver(mmci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) module_param(fmax, uint, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags