^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * meson-mx-sdio.c - Meson6, Meson8 and Meson8b SDIO/MMC Host Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Endless Mobile, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Carlo Caione <carlo@endlessm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mmc/sdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MESON_MX_SDIO_ARGU 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MESON_MX_SDIO_SEND 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7 BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MESON_MX_SDIO_SEND_RESP_HAS_DATA BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8 BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MESON_MX_SDIO_SEND_DATA BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MESON_MX_SDIO_SEND_USE_INT_WINDOW BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MESON_MX_SDIO_CONF 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MESON_MX_SDIO_CONF_CMD_DISABLE_CRC BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MESON_MX_SDIO_CONF_CMD_OUT_AT_POSITIVE_EDGE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK GENMASK(17, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MESON_MX_SDIO_CONF_RESP_LATCH_AT_NEGATIVE_EDGE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MESON_MX_SDIO_CONF_DATA_LATCH_AT_NEGATIVE_EDGE BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MESON_MX_SDIO_CONF_BUS_WIDTH BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MESON_MX_SDIO_CONF_M_ENDIAN_MASK GENMASK(22, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MESON_MX_SDIO_CONF_WRITE_NWR_MASK GENMASK(28, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK GENMASK(31, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MESON_MX_SDIO_IRQS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MESON_MX_SDIO_IRQS_STATUS_STATE_MACHINE_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MESON_MX_SDIO_IRQS_CMD_BUSY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MESON_MX_SDIO_IRQS_RESP_CRC7_OK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MESON_MX_SDIO_IRQS_IF_INT BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MESON_MX_SDIO_IRQS_CMD_INT BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MESON_MX_SDIO_IRQS_STATUS_INFO_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MESON_MX_SDIO_IRQS_TIMING_OUT_INT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MESON_MX_SDIO_IRQS_AMRISC_TIMING_OUT_INT_EN BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MESON_MX_SDIO_IRQS_ARC_TIMING_OUT_INT_EN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MESON_MX_SDIO_IRQS_TIMING_OUT_COUNT_MASK GENMASK(31, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MESON_MX_SDIO_IRQC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MESON_MX_SDIO_IRQC_ARC_IF_INT_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MESON_MX_SDIO_IRQC_IF_CONFIG_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MESON_MX_SDIO_IRQC_FORCE_DATA_CLK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MESON_MX_SDIO_IRQC_FORCE_DATA_CMD BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK GENMASK(13, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MESON_MX_SDIO_IRQC_SOFT_RESET BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MESON_MX_SDIO_IRQC_FORCE_HALT BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MESON_MX_SDIO_IRQC_HALT_HOLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MESON_MX_SDIO_MULT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MESON_MX_SDIO_MULT_PORT_SEL_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MESON_MX_SDIO_MULT_MEMORY_STICK_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MESON_MX_SDIO_MULT_MEMORY_STICK_SCLK_ALWAYS BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MESON_MX_SDIO_MULT_STREAM_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MESON_MX_SDIO_MULT_STREAM_8BITS_MODE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MESON_MX_SDIO_MULT_DAT0_DAT1_SWAPPED BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MESON_MX_SDIO_MULT_DAT1_DAT0_SWAPPED BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MESON_MX_SDIO_ADDR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MESON_MX_SDIO_EXT 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK GENMASK(29, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MESON_MX_SDIO_BOUNCE_REQ_SIZE (128 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MESON_MX_SDIO_RESPONSE_CRC16_BITS (16 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MESON_MX_SDIO_MAX_SLOTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct meson_mx_mmc_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct device *controller_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct clk *parent_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct clk *core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct clk_divider cfg_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct clk *cfg_div_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct clk_fixed_factor fixed_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct clk *fixed_factor_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) spinlock_t irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct timer_list cmd_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int slot_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct mmc_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void meson_mx_mmc_mask_bits(struct mmc_host *mmc, char reg, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct meson_mx_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) regval = readl(host->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) regval &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) regval |= (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(regval, host->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void meson_mx_mmc_soft_reset(struct meson_mx_mmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) writel(MESON_MX_SDIO_IRQC_SOFT_RESET, host->base + MESON_MX_SDIO_IRQC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct mmc_command *meson_mx_mmc_get_next_cmd(struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return cmd->mrq->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) else if (mmc_op_multi(cmd->opcode) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) (!cmd->mrq->sbc || cmd->error || cmd->data->error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return cmd->mrq->stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void meson_mx_mmc_start_cmd(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct meson_mx_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int pack_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned long irqflags, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 mult, send = 0, ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) host->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (cmd->busy_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) timeout = msecs_to_jiffies(cmd->busy_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) timeout = msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) switch (mmc_resp_type(cmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case MMC_RSP_R1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case MMC_RSP_R1B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case MMC_RSP_R3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* 7 (CMD) + 32 (response) + 7 (CRC) -1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case MMC_RSP_R2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* 7 (CMD) + 120 (response) + 7 (CRC) -1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 133);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) send |= MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (!(cmd->flags & MMC_RSP_CRC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) send |= MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (cmd->flags & MMC_RSP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) send |= MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (cmd->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) send |= FIELD_PREP(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (cmd->data->blocks - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pack_size = cmd->data->blksz * BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ext |= FIELD_PREP(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pack_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (cmd->data->flags & MMC_DATA_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) send |= MESON_MX_SDIO_SEND_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) send |= MESON_MX_SDIO_SEND_RESP_HAS_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) cmd->data->bytes_xfered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) send |= FIELD_PREP(MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) (0x40 | cmd->opcode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) spin_lock_irqsave(&host->irq_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mult = readl(host->base + MESON_MX_SDIO_MULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mult &= ~MESON_MX_SDIO_MULT_PORT_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mult |= FIELD_PREP(MESON_MX_SDIO_MULT_PORT_SEL_MASK, host->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) mult |= BIT(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) writel(mult, host->base + MESON_MX_SDIO_MULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* enable the CMD done interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* clear pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MESON_MX_SDIO_IRQS_CMD_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MESON_MX_SDIO_IRQS_CMD_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) writel(cmd->arg, host->base + MESON_MX_SDIO_ARGU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) writel(ext, host->base + MESON_MX_SDIO_EXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) writel(send, host->base + MESON_MX_SDIO_SEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) spin_unlock_irqrestore(&host->irq_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mod_timer(&host->cmd_timeout, jiffies + timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void meson_mx_mmc_request_done(struct meson_mx_mmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (host->cmd->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) meson_mx_mmc_soft_reset(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void meson_mx_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct meson_mx_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned short vdd = ios->vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long clk_rate = ios->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) switch (ios->bus_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case MMC_BUS_WIDTH_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MESON_MX_SDIO_CONF_BUS_WIDTH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case MMC_BUS_WIDTH_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MESON_MX_SDIO_CONF_BUS_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MESON_MX_SDIO_CONF_BUS_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case MMC_BUS_WIDTH_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev_err(mmc_dev(mmc), "unsupported bus width: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ios->bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) host->error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) host->error = clk_set_rate(host->cfg_div_clk, ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (host->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_warn(mmc_dev(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "failed to set MMC clock to %lu: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) clk_rate, host->error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mmc->actual_clock = clk_get_rate(host->cfg_div_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) switch (ios->power_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case MMC_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) vdd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case MMC_POWER_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!IS_ERR(mmc->supply.vmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) host->error = mmc_regulator_set_ocr(mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mmc->supply.vmmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (host->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int meson_mx_mmc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct mmc_data *data = mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) sg = data->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (sg->offset & 3 || sg->length & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_err(mmc_dev(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "unaligned scatterlist: offset %x length %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) sg->offset, sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (dma_len <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_err(mmc_dev(mmc), "dma_map_sg failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void meson_mx_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct meson_mx_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct mmc_command *cmd = mrq->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (!host->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) host->error = meson_mx_mmc_map_dma(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (host->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) cmd->error = host->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) mmc_request_done(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) host->mrq = mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (mrq->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) writel(sg_dma_address(mrq->data->sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) host->base + MESON_MX_SDIO_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (mrq->sbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) meson_mx_mmc_start_cmd(mmc, mrq->sbc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) meson_mx_mmc_start_cmd(mmc, mrq->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static void meson_mx_mmc_read_response(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct meson_mx_mmc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int i, resp[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mult = readl(host->base + MESON_MX_SDIO_MULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mult |= MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mult &= ~MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mult |= FIELD_PREP(MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) writel(mult, host->base + MESON_MX_SDIO_MULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) for (i = 0; i <= 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) resp[3 - i] = readl(host->base + MESON_MX_SDIO_ARGU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) cmd->resp[0] = (resp[0] << 8) | ((resp[1] >> 24) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) cmd->resp[1] = (resp[1] << 8) | ((resp[2] >> 24) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) cmd->resp[2] = (resp[2] << 8) | ((resp[3] >> 24) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cmd->resp[3] = (resp[3] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) cmd->resp[0] = readl(host->base + MESON_MX_SDIO_ARGU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static irqreturn_t meson_mx_mmc_process_cmd_irq(struct meson_mx_mmc_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u32 irqs, u32 send)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct mmc_command *cmd = host->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * NOTE: even though it shouldn't happen we sometimes get command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * interrupts twice (at least this is what it looks like). Ideally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * we find out why this happens and warn here as soon as it occurs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cmd->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) meson_mx_mmc_read_response(host->mmc, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (cmd->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (!((irqs & MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) (irqs & MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!((irqs & MESON_MX_SDIO_IRQS_RESP_CRC7_OK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) (send & MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static irqreturn_t meson_mx_mmc_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct meson_mx_mmc_host *host = (void *) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 irqs, send;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) irqreturn_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) spin_lock_irqsave(&host->irq_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) irqs = readl(host->base + MESON_MX_SDIO_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) send = readl(host->base + MESON_MX_SDIO_SEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (irqs & MESON_MX_SDIO_IRQS_CMD_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret = meson_mx_mmc_process_cmd_irq(host, irqs, send);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* finally ACK all pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) writel(irqs, host->base + MESON_MX_SDIO_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) spin_unlock_irqrestore(&host->irq_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static irqreturn_t meson_mx_mmc_irq_thread(int irq, void *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct meson_mx_mmc_host *host = (void *) irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct mmc_command *cmd = host->cmd, *next_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (WARN_ON(!cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) del_timer_sync(&host->cmd_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (cmd->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) cmd->data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mmc_get_dma_dir(cmd->data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) next_cmd = meson_mx_mmc_get_next_cmd(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (next_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) meson_mx_mmc_start_cmd(host->mmc, next_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) meson_mx_mmc_request_done(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static void meson_mx_mmc_timeout(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct meson_mx_mmc_host *host = from_timer(host, t, cmd_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) spin_lock_irqsave(&host->irq_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* disable the CMD interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) irqc = readl(host->base + MESON_MX_SDIO_IRQC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) irqc &= ~MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) writel(irqc, host->base + MESON_MX_SDIO_IRQC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) spin_unlock_irqrestore(&host->irq_lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * skip the timeout handling if the interrupt handler already processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * the command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!host->cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_dbg(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "Timeout on CMD%u (IRQS = 0x%08x, ARGU = 0x%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) host->cmd->opcode, readl(host->base + MESON_MX_SDIO_IRQS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) readl(host->base + MESON_MX_SDIO_ARGU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) host->cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) meson_mx_mmc_request_done(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static struct mmc_host_ops meson_mx_mmc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .request = meson_mx_mmc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .set_ios = meson_mx_mmc_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .get_cd = mmc_gpio_get_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .get_ro = mmc_gpio_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static struct platform_device *meson_mx_mmc_slot_pdev(struct device *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct device_node *slot_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * TODO: the MMC core framework currently does not support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * controllers with multiple slots properly. So we only register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * the first slot for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) slot_node = of_get_compatible_child(parent->of_node, "mmc-slot");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (!slot_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dev_warn(parent, "no 'mmc-slot' sub-node found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pdev = of_platform_device_create(slot_node, NULL, parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) of_node_put(slot_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int meson_mx_mmc_add_host(struct meson_mx_mmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct device *slot_dev = mmc_dev(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (of_property_read_u32(slot_dev->of_node, "reg", &host->slot_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev_err(slot_dev, "missing 'reg' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (host->slot_id >= MESON_MX_SDIO_MAX_SLOTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dev_err(slot_dev, "invalid 'reg' property value %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) host->slot_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Get regulators and the supported OCR mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = mmc_regulator_get_supply(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) mmc->max_req_size = MESON_MX_SDIO_BOUNCE_REQ_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mmc->max_seg_size = mmc->max_req_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) mmc->max_blk_count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) FIELD_GET(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mmc->max_blk_size = FIELD_GET(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mmc->max_blk_size -= (4 * MESON_MX_SDIO_RESPONSE_CRC16_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mmc->max_blk_size /= BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Get the min and max supported clock rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mmc->f_min = clk_round_rate(host->cfg_div_clk, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mmc->f_max = clk_round_rate(host->cfg_div_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) clk_get_rate(host->parent_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mmc->ops = &meson_mx_mmc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = mmc_of_parse(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int meson_mx_mmc_register_clks(struct meson_mx_mmc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) const char *clk_div_parent, *clk_fixed_factor_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) clk_fixed_factor_parent = __clk_get_name(host->parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) "%s#fixed_factor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_name(host->controller_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (!init.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) init.ops = &clk_fixed_factor_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) init.parent_names = &clk_fixed_factor_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) host->fixed_factor.div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) host->fixed_factor.mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) host->fixed_factor.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) host->fixed_factor_clk = devm_clk_register(host->controller_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) &host->fixed_factor.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (WARN_ON(IS_ERR(host->fixed_factor_clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return PTR_ERR(host->fixed_factor_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) clk_div_parent = __clk_get_name(host->fixed_factor_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) "%s#div", dev_name(host->controller_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (!init.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) init.ops = &clk_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) init.parent_names = &clk_div_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) host->cfg_div.reg = host->base + MESON_MX_SDIO_CONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) host->cfg_div.shift = MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) host->cfg_div.width = MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) host->cfg_div.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) host->cfg_div.flags = CLK_DIVIDER_ALLOW_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) host->cfg_div_clk = devm_clk_register(host->controller_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) &host->cfg_div.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (WARN_ON(IS_ERR(host->cfg_div_clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return PTR_ERR(host->cfg_div_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int meson_mx_mmc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct platform_device *slot_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct meson_mx_mmc_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) slot_pdev = meson_mx_mmc_slot_pdev(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (!slot_pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) else if (IS_ERR(slot_pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return PTR_ERR(slot_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) mmc = mmc_alloc_host(sizeof(*host), &slot_pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (!mmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) goto error_unregister_slot_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) host->mmc = mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) host->controller_dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) spin_lock_init(&host->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) timer_setup(&host->cmd_timeout, meson_mx_mmc_timeout, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) platform_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) host->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (IS_ERR(host->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ret = PTR_ERR(host->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) goto error_free_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) goto error_free_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = devm_request_threaded_irq(host->controller_dev, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) meson_mx_mmc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) meson_mx_mmc_irq_thread, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) NULL, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) goto error_free_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) host->core_clk = devm_clk_get(host->controller_dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (IS_ERR(host->core_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ret = PTR_ERR(host->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) goto error_free_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) host->parent_clk = devm_clk_get(host->controller_dev, "clkin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (IS_ERR(host->parent_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ret = PTR_ERR(host->parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) goto error_free_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = meson_mx_mmc_register_clks(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) goto error_free_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ret = clk_prepare_enable(host->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_err(host->controller_dev, "Failed to enable core clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) goto error_free_mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ret = clk_prepare_enable(host->cfg_div_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) dev_err(host->controller_dev, "Failed to enable MMC clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) goto error_disable_core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) conf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) conf |= FIELD_PREP(MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK, 39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) conf |= FIELD_PREP(MESON_MX_SDIO_CONF_M_ENDIAN_MASK, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_NWR_MASK, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) writel(conf, host->base + MESON_MX_SDIO_CONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) meson_mx_mmc_soft_reset(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ret = meson_mx_mmc_add_host(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) goto error_disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) error_disable_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) clk_disable_unprepare(host->cfg_div_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) error_disable_core_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) clk_disable_unprepare(host->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) error_free_mmc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) error_unregister_slot_pdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) of_platform_device_destroy(&slot_pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int meson_mx_mmc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct meson_mx_mmc_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct device *slot_dev = mmc_dev(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) del_timer_sync(&host->cmd_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) mmc_remove_host(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) of_platform_device_destroy(slot_dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) clk_disable_unprepare(host->cfg_div_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) clk_disable_unprepare(host->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) mmc_free_host(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static const struct of_device_id meson_mx_mmc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) { .compatible = "amlogic,meson8-sdio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) { .compatible = "amlogic,meson8b-sdio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) MODULE_DEVICE_TABLE(of, meson_mx_mmc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static struct platform_driver meson_mx_mmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .probe = meson_mx_mmc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .remove = meson_mx_mmc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .name = "meson-mx-sdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .of_match_table = of_match_ptr(meson_mx_mmc_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) module_platform_driver(meson_mx_mmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) MODULE_DESCRIPTION("Meson6, Meson8 and Meson8b SDIO/MMC Host Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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