^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _MESON_MX_SDHC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _MESON_MX_SDHC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MESON_SDHC_ARGU 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MESON_SDHC_SEND 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MESON_SDHC_SEND_CMD_INDEX GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MESON_SDHC_SEND_CMD_HAS_RESP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MESON_SDHC_SEND_CMD_HAS_DATA BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MESON_SDHC_SEND_RESP_LEN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MESON_SDHC_SEND_RESP_NO_CRC BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MESON_SDHC_SEND_DATA_DIR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MESON_SDHC_SEND_DATA_STOP BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MESON_SDHC_SEND_R1B BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MESON_SDHC_SEND_TOTAL_PACK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MESON_SDHC_CTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MESON_SDHC_CTRL_DAT_TYPE GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MESON_SDHC_CTRL_DDR_MODE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MESON_SDHC_CTRL_TX_CRC_NOCHECK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MESON_SDHC_CTRL_PACK_LEN GENMASK(12, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MESON_SDHC_CTRL_RX_TIMEOUT GENMASK(19, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MESON_SDHC_CTRL_RX_PERIOD GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MESON_SDHC_CTRL_RX_ENDIAN GENMASK(26, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MESON_SDHC_CTRL_SDIO_IRQ_MODE BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MESON_SDHC_CTRL_DAT0_IRQ_SEL BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MESON_SDHC_CTRL_TX_ENDIAN GENMASK(31, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MESON_SDHC_STAT 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MESON_SDHC_STAT_CMD_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MESON_SDHC_STAT_DAT3_0 GENMASK(4, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MESON_SDHC_STAT_CMD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MESON_SDHC_STAT_RXFIFO_CNT GENMASK(12, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MESON_SDHC_STAT_TXFIFO_CNT GENMASK(19, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MESON_SDHC_STAT_DAT7_4 GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MESON_SDHC_CLKC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MESON_SDHC_CLKC_CLK_DIV GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MESON_SDHC_CLKC_CLK_JIC BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MESON_SDHC_CLKC_MEM_PWR_OFF GENMASK(26, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MESON_SDHC_ADDR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MESON_SDHC_PDMA 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MESON_SDHC_PDMA_DMA_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MESON_SDHC_PDMA_PIO_RDRESP GENMASK(3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MESON_SDHC_PDMA_DMA_URGENT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MESON_SDHC_PDMA_WR_BURST GENMASK(9, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MESON_SDHC_PDMA_RD_BURST GENMASK(14, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MESON_SDHC_PDMA_RXFIFO_TH GENMASK(21, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MESON_SDHC_PDMA_TXFIFO_TH GENMASK(28, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH GENMASK(30, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MESON_SDHC_PDMA_TXFIFO_FILL BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MESON_SDHC_MISC 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MESON_SDHC_MISC_WCRC_ERR_PATT GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MESON_SDHC_MISC_WCRC_OK_PATT GENMASK(9, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MESON_SDHC_MISC_BURST_NUM GENMASK(21, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MESON_SDHC_MISC_THREAD_ID GENMASK(27, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MESON_SDHC_MISC_MANUAL_STOP BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MESON_SDHC_MISC_TXSTART_THRES GENMASK(31, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MESON_SDHC_DATA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MESON_SDHC_ICTL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MESON_SDHC_ICTL_RESP_OK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MESON_SDHC_ICTL_RESP_TIMEOUT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MESON_SDHC_ICTL_RESP_ERR_CRC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MESON_SDHC_ICTL_RESP_OK_NOCLEAR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MESON_SDHC_ICTL_DATA_1PACK_OK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MESON_SDHC_ICTL_DATA_TIMEOUT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MESON_SDHC_ICTL_DATA_ERR_CRC BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MESON_SDHC_ICTL_DATA_XFER_OK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MESON_SDHC_ICTL_RX_HIGHER BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MESON_SDHC_ICTL_RX_LOWER BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MESON_SDHC_ICTL_DAT1_IRQ BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MESON_SDHC_ICTL_DMA_DONE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MESON_SDHC_ICTL_RXFIFO_FULL BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MESON_SDHC_ICTL_TXFIFO_EMPTY BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MESON_SDHC_ICTL_ADDI_DAT1_IRQ BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MESON_SDHC_ICTL_ALL_IRQS GENMASK(14, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MESON_SDHC_ICTL_DAT1_IRQ_DELAY GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MESON_SDHC_ISTA 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MESON_SDHC_ISTA_RESP_OK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MESON_SDHC_ISTA_RESP_TIMEOUT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MESON_SDHC_ISTA_RESP_ERR_CRC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MESON_SDHC_ISTA_RESP_OK_NOCLEAR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MESON_SDHC_ISTA_DATA_1PACK_OK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MESON_SDHC_ISTA_DATA_TIMEOUT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MESON_SDHC_ISTA_DATA_ERR_CRC BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MESON_SDHC_ISTA_DATA_XFER_OK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MESON_SDHC_ISTA_RX_HIGHER BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MESON_SDHC_ISTA_RX_LOWER BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MESON_SDHC_ISTA_DAT1_IRQ BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MESON_SDHC_ISTA_DMA_DONE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MESON_SDHC_ISTA_RXFIFO_FULL BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MESON_SDHC_ISTA_TXFIFO_EMPTY BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MESON_SDHC_ISTA_ADDI_DAT1_IRQ BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MESON_SDHC_ISTA_ALL_IRQS GENMASK(14, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MESON_SDHC_SRST 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MESON_SDHC_SRST_MAIN_CTRL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MESON_SDHC_SRST_RXFIFO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MESON_SDHC_SRST_TXFIFO BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MESON_SDHC_SRST_DPHY_RX BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MESON_SDHC_SRST_DPHY_TX BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MESON_SDHC_SRST_DMA_IF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MESON_SDHC_ESTA 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MESON_SDHC_ESTA_11_13 GENMASK(13, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MESON_SDHC_ENHC 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MESON_SDHC_ENHC_MESON8M2_WRRSP_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MESON_SDHC_ENHC_MESON8M2_CHK_WRRSP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MESON_SDHC_ENHC_MESON8M2_CHK_DMA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MESON_SDHC_ENHC_MESON8M2_DEBUG GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MESON_SDHC_ENHC_MESON6_RX_TIMEOUT GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MESON_SDHC_ENHC_MESON6_DMA_RD_RESP BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MESON_SDHC_ENHC_MESON6_DMA_WR_RESP BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MESON_SDHC_ENHC_SDIO_IRQ_PERIOD GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MESON_SDHC_ENHC_RXFIFO_TH GENMASK(24, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MESON_SDHC_ENHC_TXFIFO_TH GENMASK(31, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MESON_SDHC_CLK2 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MESON_SDHC_CLK2_RX_CLK_PHASE GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MESON_SDHC_CLK2_SD_CLK_PHASE GENMASK(23, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct clk_bulk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int meson_mx_sdhc_register_clkc(struct device *dev, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct clk_bulk_data *clk_bulk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif /* _MESON_MX_SDHC_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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