^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Amlogic Meson6/Meson8/Meson8b/Meson8m2 SDHC MMC host controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mmc/sdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "meson-mx-sdhc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MESON_SDHC_NUM_BULK_CLKS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MESON_SDHC_MAX_BLK_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MESON_SDHC_NUM_TUNING_TRIES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MESON_SDHC_WAIT_CMD_READY_SLEEP_US 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct meson_mx_sdhc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void (*init_hw)(struct mmc_host *mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void (*set_pdma)(struct mmc_host *mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void (*wait_before_send)(struct mmc_host *mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bool hardware_flush_all_cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct meson_mx_sdhc_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct mmc_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk *sd_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk_bulk_data bulk_clks[MESON_SDHC_NUM_BULK_CLKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) bool bulk_clks_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const struct meson_mx_sdhc_data *platform;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct regmap_config meson_mx_sdhc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .max_register = MESON_SDHC_CLK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void meson_mx_sdhc_hw_reset(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) regmap_write(host->regmap, MESON_SDHC_SRST, MESON_SDHC_SRST_MAIN_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MESON_SDHC_SRST_RXFIFO | MESON_SDHC_SRST_TXFIFO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MESON_SDHC_SRST_DPHY_RX | MESON_SDHC_SRST_DPHY_TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MESON_SDHC_SRST_DMA_IF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) usleep_range(10, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) regmap_write(host->regmap, MESON_SDHC_SRST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) usleep_range(10, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void meson_mx_sdhc_clear_fifo(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (!FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) !FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) regmap_write(host->regmap, MESON_SDHC_SRST, MESON_SDHC_SRST_RXFIFO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MESON_SDHC_SRST_TXFIFO | MESON_SDHC_SRST_MAIN_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_warn(mmc_dev(host->mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "Failed to clear FIFOs, RX: %lu, TX: %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void meson_mx_sdhc_wait_cmd_ready(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 stat, esta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_STAT, stat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) !(stat & MESON_SDHC_STAT_CMD_BUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MESON_SDHC_WAIT_CMD_READY_SLEEP_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_warn(mmc_dev(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "Failed to poll for CMD_BUSY while processing CMD%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) host->cmd->opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) meson_mx_sdhc_hw_reset(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_ESTA, esta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) !(esta & MESON_SDHC_ESTA_11_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MESON_SDHC_WAIT_CMD_READY_SLEEP_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev_warn(mmc_dev(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "Failed to poll for ESTA[13:11] while processing CMD%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) host->cmd->opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) meson_mx_sdhc_hw_reset(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void meson_mx_sdhc_start_cmd(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool manual_stop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 ictl, send;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int pack_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) host->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ictl = MESON_SDHC_ICTL_DATA_TIMEOUT | MESON_SDHC_ICTL_DATA_ERR_CRC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MESON_SDHC_ICTL_RXFIFO_FULL | MESON_SDHC_ICTL_TXFIFO_EMPTY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MESON_SDHC_ICTL_RESP_TIMEOUT | MESON_SDHC_ICTL_RESP_ERR_CRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) send = FIELD_PREP(MESON_SDHC_SEND_CMD_INDEX, cmd->opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (cmd->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) send |= MESON_SDHC_SEND_CMD_HAS_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) send |= FIELD_PREP(MESON_SDHC_SEND_TOTAL_PACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) cmd->data->blocks - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (cmd->data->blksz < MESON_SDHC_MAX_BLK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pack_len = cmd->data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pack_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (cmd->data->flags & MMC_DATA_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) send |= MESON_SDHC_SEND_DATA_DIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * If command with no data, just wait response done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * interrupt(int[0]), and if command with data transfer, just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * wait dma done interrupt(int[11]), don't need care about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * dat0 busy or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (host->platform->hardware_flush_all_cmds ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) cmd->data->flags & MMC_DATA_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* hardware flush: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ictl |= MESON_SDHC_ICTL_DMA_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* software flush: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ictl |= MESON_SDHC_ICTL_DATA_XFER_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Mimic the logic from the vendor driver where (only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * SD_IO_RW_EXTENDED commands with more than one block set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * MESON_SDHC_MISC_MANUAL_STOP bit. This fixes the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * download in the brcmfmac driver for a BCM43362/1 card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Without this sdio_memcpy_toio() (with a size of 219557
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * bytes) times out if MESON_SDHC_MISC_MANUAL_STOP is not set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) manual_stop = cmd->data->blocks > 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) cmd->opcode == SD_IO_RW_EXTENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pack_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ictl |= MESON_SDHC_ICTL_RESP_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) regmap_update_bits(host->regmap, MESON_SDHC_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MESON_SDHC_MISC_MANUAL_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) manual_stop ? MESON_SDHC_MISC_MANUAL_STOP : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (cmd->opcode == MMC_STOP_TRANSMISSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) send |= MESON_SDHC_SEND_DATA_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (cmd->flags & MMC_RSP_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) send |= MESON_SDHC_SEND_CMD_HAS_RESP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) send |= MESON_SDHC_SEND_RESP_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) send |= MESON_SDHC_SEND_RESP_NO_CRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!(cmd->flags & MMC_RSP_CRC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) send |= MESON_SDHC_SEND_RESP_NO_CRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (cmd->flags & MMC_RSP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) send |= MESON_SDHC_SEND_R1B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* enable the new IRQs and mask all pending ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) regmap_write(host->regmap, MESON_SDHC_ICTL, ictl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) regmap_write(host->regmap, MESON_SDHC_ISTA, MESON_SDHC_ISTA_ALL_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) regmap_write(host->regmap, MESON_SDHC_ARGU, cmd->arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MESON_SDHC_CTRL_PACK_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) FIELD_PREP(MESON_SDHC_CTRL_PACK_LEN, pack_len));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (cmd->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) regmap_write(host->regmap, MESON_SDHC_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) sg_dma_address(cmd->data->sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) meson_mx_sdhc_wait_cmd_ready(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (cmd->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) host->platform->set_pdma(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (host->platform->wait_before_send)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) host->platform->wait_before_send(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) regmap_write(host->regmap, MESON_SDHC_SEND, send);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void meson_mx_sdhc_disable_clks(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!host->bulk_clks_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) clk_bulk_disable_unprepare(MESON_SDHC_NUM_BULK_CLKS, host->bulk_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) host->bulk_clks_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int meson_mx_sdhc_enable_clks(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (host->bulk_clks_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = clk_bulk_prepare_enable(MESON_SDHC_NUM_BULK_CLKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) host->bulk_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) host->bulk_clks_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 rx_clk_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) meson_mx_sdhc_disable_clks(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (ios->clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = clk_set_rate(host->sd_clk, ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_warn(mmc_dev(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "Failed to set MMC clock to %uHz: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ios->clock, host->error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ret = meson_mx_sdhc_enable_clks(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mmc->actual_clock = clk_get_rate(host->sd_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * according to Amlogic the following latching points are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * selected with empirical values, there is no (known) formula
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * to calculate these.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (mmc->actual_clock > 100000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) rx_clk_phase = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) } else if (mmc->actual_clock > 45000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) rx_clk_phase = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) rx_clk_phase = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) } else if (mmc->actual_clock >= 25000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) rx_clk_phase = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) } else if (mmc->actual_clock > 5000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) rx_clk_phase = 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) } else if (mmc->actual_clock > 1000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) rx_clk_phase = 55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) rx_clk_phase = 1061;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MESON_SDHC_CLK2_RX_CLK_PHASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) rx_clk_phase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mmc->actual_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void meson_mx_sdhc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned short vdd = ios->vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) switch (ios->power_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case MMC_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) vdd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case MMC_POWER_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!IS_ERR(mmc->supply.vmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) host->error = mmc_regulator_set_ocr(mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mmc->supply.vmmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (host->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case MMC_POWER_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) host->error = meson_mx_sdhc_set_clk(mmc, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (host->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) switch (ios->bus_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case MMC_BUS_WIDTH_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MESON_SDHC_CTRL_DAT_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case MMC_BUS_WIDTH_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MESON_SDHC_CTRL_DAT_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case MMC_BUS_WIDTH_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MESON_SDHC_CTRL_DAT_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_err(mmc_dev(mmc), "unsupported bus width: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ios->bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) host->error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int meson_mx_sdhc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct mmc_data *data = mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (dma_len <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_err(mmc_dev(mmc), "dma_map_sg failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static void meson_mx_sdhc_request(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct mmc_command *cmd = mrq->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!host->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) host->error = meson_mx_sdhc_map_dma(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (host->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) cmd->error = host->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mmc_request_done(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) host->mrq = mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) meson_mx_sdhc_start_cmd(mmc, mrq->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int meson_mx_sdhc_card_busy(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return FIELD_GET(MESON_SDHC_STAT_DAT3_0, stat) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static bool meson_mx_sdhc_tuning_point_matches(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned int i, num_matches = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) for (i = 0; i < MESON_SDHC_NUM_TUNING_TRIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = mmc_send_tuning(mmc, opcode, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) num_matches++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return num_matches == MESON_SDHC_NUM_TUNING_TRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int meson_mx_sdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int div, start, len, best_start, best_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int curr_phase, old_phase, new_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) best_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) regmap_read(host->regmap, MESON_SDHC_CLK2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) old_phase = FIELD_GET(MESON_SDHC_CLK2_RX_CLK_PHASE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) regmap_read(host->regmap, MESON_SDHC_CLKC, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) div = FIELD_GET(MESON_SDHC_CLKC_CLK_DIV, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) for (curr_phase = 0; curr_phase <= div; curr_phase++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MESON_SDHC_CLK2_RX_CLK_PHASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) curr_phase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (meson_mx_sdhc_tuning_point_matches(mmc, opcode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (!len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) start = curr_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_dbg(mmc_dev(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "New RX phase window starts at %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (len > best_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) best_start = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) best_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_dbg(mmc_dev(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "New best RX phase window: %u - %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) best_start, best_start + best_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* reset the current window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (len > best_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* the last window is the best (or possibly only) window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) new_phase = start + (len / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) else if (best_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* there was a better window than the last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) new_phase = best_start + (best_len / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* no window was found at all, reset to the original phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) new_phase = old_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) MESON_SDHC_CLK2_RX_CLK_PHASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) new_phase));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (!len && !best_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_dbg(mmc_dev(mmc), "Tuned RX clock phase to %u\n", new_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const struct mmc_host_ops meson_mx_sdhc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .hw_reset = meson_mx_sdhc_hw_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .request = meson_mx_sdhc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .set_ios = meson_mx_sdhc_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .card_busy = meson_mx_sdhc_card_busy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .execute_tuning = meson_mx_sdhc_execute_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .get_cd = mmc_gpio_get_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .get_ro = mmc_gpio_get_ro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void meson_mx_sdhc_request_done(struct meson_mx_sdhc_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct mmc_request *mrq = host->mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* disable interrupts and mask all pending ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) regmap_update_bits(host->regmap, MESON_SDHC_ICTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MESON_SDHC_ICTL_ALL_IRQS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) regmap_update_bits(host->regmap, MESON_SDHC_ISTA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MESON_SDHC_ISTA_ALL_IRQS, MESON_SDHC_ISTA_ALL_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) host->mrq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mmc_request_done(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static u32 meson_mx_sdhc_read_response(struct meson_mx_sdhc_host *host, u8 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MESON_SDHC_PDMA_DMA_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MESON_SDHC_PDMA_PIO_RDRESP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) FIELD_PREP(MESON_SDHC_PDMA_PIO_RDRESP, idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) regmap_read(host->regmap, MESON_SDHC_ARGU, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static irqreturn_t meson_mx_sdhc_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct meson_mx_sdhc_host *host = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct mmc_command *cmd = host->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 ictl, ista;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) regmap_read(host->regmap, MESON_SDHC_ICTL, &ictl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) regmap_read(host->regmap, MESON_SDHC_ISTA, &ista);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!(ictl & ista))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (ista & MESON_SDHC_ISTA_RXFIFO_FULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ista & MESON_SDHC_ISTA_TXFIFO_EMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) cmd->error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) else if (ista & MESON_SDHC_ISTA_RESP_ERR_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) else if (ista & MESON_SDHC_ISTA_RESP_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (cmd->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ista & MESON_SDHC_ISTA_DATA_ERR_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) cmd->data->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) else if (ista & MESON_SDHC_ISTA_DATA_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) cmd->data->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (cmd->error || (cmd->data && cmd->data->error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev_dbg(mmc_dev(host->mmc), "CMD%d error, ISTA: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) cmd->opcode, ista);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static irqreturn_t meson_mx_sdhc_irq_thread(int irq, void *irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct meson_mx_sdhc_host *host = irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct mmc_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) cmd = host->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (WARN_ON(!cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (cmd->data && !cmd->data->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (!host->platform->hardware_flush_all_cmds &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) cmd->data->flags & MMC_DATA_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) meson_mx_sdhc_wait_cmd_ready(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * If MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * previously 0x1 then it has to be set to 0x3. If it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * was 0x0 before then it has to be set to 0x2. Without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * this reading SD cards sometimes transfers garbage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * which results in cards not being detected due to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * unrecognised SCR structure version <random number>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) val = FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) regmap_update_bits(host->regmap, MESON_SDHC_PDMA, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) cmd->data->sg_len, mmc_get_dma_dir(cmd->data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) meson_mx_sdhc_wait_cmd_ready(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) cmd->resp[0] = meson_mx_sdhc_read_response(host, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) cmd->resp[1] = meson_mx_sdhc_read_response(host, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) cmd->resp[2] = meson_mx_sdhc_read_response(host, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) cmd->resp[3] = meson_mx_sdhc_read_response(host, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) cmd->resp[0] = meson_mx_sdhc_read_response(host, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (cmd->error == -EIO || cmd->error == -ETIMEDOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) meson_mx_sdhc_hw_reset(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) else if (cmd->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * Clear the FIFOs after completing data transfers to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * corrupting data on write access. It's not clear why this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * needed (for reads and writes), but it mimics what the BSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * kernel did.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) meson_mx_sdhc_clear_fifo(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) meson_mx_sdhc_request_done(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static void meson_mx_sdhc_init_hw_meson8(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) regmap_write(host->regmap, MESON_SDHC_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) FIELD_PREP(MESON_SDHC_MISC_TXSTART_THRES, 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) FIELD_PREP(MESON_SDHC_MISC_WCRC_ERR_PATT, 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) FIELD_PREP(MESON_SDHC_MISC_WCRC_OK_PATT, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) regmap_write(host->regmap, MESON_SDHC_ENHC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) FIELD_PREP(MESON_SDHC_ENHC_RXFIFO_TH, 63) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) MESON_SDHC_ENHC_MESON6_DMA_WR_RESP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) FIELD_PREP(MESON_SDHC_ENHC_MESON6_RX_TIMEOUT, 255) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) FIELD_PREP(MESON_SDHC_ENHC_SDIO_IRQ_PERIOD, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static void meson_mx_sdhc_set_pdma_meson8(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (host->cmd->data->flags & MMC_DATA_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) MESON_SDHC_PDMA_DMA_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) MESON_SDHC_PDMA_RD_BURST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MESON_SDHC_PDMA_TXFIFO_FILL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MESON_SDHC_PDMA_DMA_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 31) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) MESON_SDHC_PDMA_TXFIFO_FILL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) MESON_SDHC_PDMA_DMA_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) MESON_SDHC_PDMA_DMA_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (host->cmd->data->flags & MMC_DATA_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) MESON_SDHC_PDMA_RD_BURST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static void meson_mx_sdhc_wait_before_send_meson8(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_ESTA, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) val == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_warn(mmc_dev(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) "Failed to wait for ESTA to clear: 0x%08x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (host->cmd->data && host->cmd->data->flags & MMC_DATA_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) val, val & MESON_SDHC_STAT_TXFIFO_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_warn(mmc_dev(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) "Failed to wait for TX FIFO to fill\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static void meson_mx_sdhc_init_hw_meson8m2(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) regmap_write(host->regmap, MESON_SDHC_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) FIELD_PREP(MESON_SDHC_MISC_TXSTART_THRES, 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) FIELD_PREP(MESON_SDHC_MISC_WCRC_ERR_PATT, 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) FIELD_PREP(MESON_SDHC_MISC_WCRC_OK_PATT, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) regmap_write(host->regmap, MESON_SDHC_ENHC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) FIELD_PREP(MESON_SDHC_ENHC_RXFIFO_TH, 64) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) FIELD_PREP(MESON_SDHC_ENHC_MESON8M2_DEBUG, 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) MESON_SDHC_ENHC_MESON8M2_WRRSP_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) FIELD_PREP(MESON_SDHC_ENHC_SDIO_IRQ_PERIOD, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static void meson_mx_sdhc_set_pdma_meson8m2(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) MESON_SDHC_PDMA_DMA_MODE, MESON_SDHC_PDMA_DMA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static void meson_mx_sdhc_init_hw(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct meson_mx_sdhc_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) meson_mx_sdhc_hw_reset(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) regmap_write(host->regmap, MESON_SDHC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) FIELD_PREP(MESON_SDHC_CTRL_RX_PERIOD, 0xf) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) FIELD_PREP(MESON_SDHC_CTRL_RX_TIMEOUT, 0x7f) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) FIELD_PREP(MESON_SDHC_CTRL_RX_ENDIAN, 0x7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) FIELD_PREP(MESON_SDHC_CTRL_TX_ENDIAN, 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * start with a valid divider and enable the memory (un-setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * MESON_SDHC_CLKC_MEM_PWR_OFF).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) regmap_write(host->regmap, MESON_SDHC_CLKC, MESON_SDHC_CLKC_CLK_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) regmap_write(host->regmap, MESON_SDHC_CLK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) FIELD_PREP(MESON_SDHC_CLK2_SD_CLK_PHASE, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) regmap_write(host->regmap, MESON_SDHC_PDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) MESON_SDHC_PDMA_DMA_URGENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) FIELD_PREP(MESON_SDHC_PDMA_WR_BURST, 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) FIELD_PREP(MESON_SDHC_PDMA_TXFIFO_TH, 49) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 15) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_TH, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* some initialization bits depend on the SoC: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) host->platform->init_hw(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* disable and mask all interrupts: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) regmap_write(host->regmap, MESON_SDHC_ICTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) regmap_write(host->regmap, MESON_SDHC_ISTA, MESON_SDHC_ISTA_ALL_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static int meson_mx_sdhc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct meson_mx_sdhc_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mmc = mmc_alloc_host(sizeof(*host), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (!mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ret = devm_add_action_or_reset(dev, (void(*)(void *))mmc_free_host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_err(dev, "Failed to register mmc_free_host action\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) host->mmc = mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) platform_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) host->platform = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (!host->platform)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) host->regmap = devm_regmap_init_mmio(dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) &meson_mx_sdhc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (IS_ERR(host->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return PTR_ERR(host->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) host->pclk = devm_clk_get(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (IS_ERR(host->pclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return PTR_ERR(host->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* accessing any register requires the module clock to be enabled: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ret = clk_prepare_enable(host->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dev_err(dev, "Failed to enable 'pclk' clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) meson_mx_sdhc_init_hw(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ret = meson_mx_sdhc_register_clkc(dev, base, host->bulk_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) goto err_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) host->sd_clk = host->bulk_clks[1].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Get regulators and the supported OCR mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ret = mmc_regulator_get_supply(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) goto err_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) mmc->max_req_size = SZ_128K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) mmc->max_seg_size = mmc->max_req_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) mmc->max_blk_count = FIELD_GET(MESON_SDHC_SEND_TOTAL_PACK, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) mmc->max_blk_size = MESON_SDHC_MAX_BLK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) mmc->max_busy_timeout = 30 * MSEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) mmc->f_min = clk_round_rate(host->sd_clk, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) mmc->f_max = clk_round_rate(host->sd_clk, ULONG_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) mmc->max_current_180 = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) mmc->max_current_330 = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_HW_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) mmc->ops = &meson_mx_sdhc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ret = mmc_of_parse(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) goto err_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) goto err_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ret = devm_request_threaded_irq(dev, irq, meson_mx_sdhc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) meson_mx_sdhc_irq_thread, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) NULL, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) goto err_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) goto err_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) err_disable_pclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) clk_disable_unprepare(host->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static int meson_mx_sdhc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct meson_mx_sdhc_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) mmc_remove_host(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) meson_mx_sdhc_disable_clks(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) clk_disable_unprepare(host->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static const struct meson_mx_sdhc_data meson_mx_sdhc_data_meson8 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .init_hw = meson_mx_sdhc_init_hw_meson8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .set_pdma = meson_mx_sdhc_set_pdma_meson8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .wait_before_send = meson_mx_sdhc_wait_before_send_meson8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .hardware_flush_all_cmds = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const struct meson_mx_sdhc_data meson_mx_sdhc_data_meson8m2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .init_hw = meson_mx_sdhc_init_hw_meson8m2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .set_pdma = meson_mx_sdhc_set_pdma_meson8m2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .hardware_flush_all_cmds = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static const struct of_device_id meson_mx_sdhc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .compatible = "amlogic,meson8-sdhc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .data = &meson_mx_sdhc_data_meson8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .compatible = "amlogic,meson8b-sdhc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .data = &meson_mx_sdhc_data_meson8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .compatible = "amlogic,meson8m2-sdhc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .data = &meson_mx_sdhc_data_meson8m2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) MODULE_DEVICE_TABLE(of, meson_mx_sdhc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static struct platform_driver meson_mx_sdhc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .probe = meson_mx_sdhc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .remove = meson_mx_sdhc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .name = "meson-mx-sdhc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .of_match_table = of_match_ptr(meson_mx_sdhc_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) module_platform_driver(meson_mx_sdhc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) MODULE_DESCRIPTION("Meson6, Meson8, Meson8b and Meson8m2 SDHC Host Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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