^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Amlogic SD/eMMC driver for the GX/S905 family SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Kevin Hilman <khilman@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mmc/sdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRIVER_NAME "meson-gx-mmc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SD_EMMC_CLOCK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_DIV_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_SRC_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_CORE_PHASE_MASK GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_TX_PHASE_MASK GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_RX_PHASE_MASK GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_PHASE_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_PHASE_180 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_V2_ALWAYS_ON BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_V3_ALWAYS_ON BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_ALWAYS_ON(h) (h->data->always_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SD_EMMC_DELAY 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SD_EMMC_ADJUST 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ADJUST_DS_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ADJUST_ADJ_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SD_EMMC_DELAY1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SD_EMMC_DELAY2 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SD_EMMC_V3_ADJUST 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SD_EMMC_CALOUT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SD_EMMC_START 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define START_DESC_INIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define START_DESC_BUSY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define START_DESC_ADDR_MASK GENMASK(31, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SD_EMMC_CFG 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CFG_BUS_WIDTH_1 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CFG_BUS_WIDTH_4 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CFG_BUS_WIDTH_8 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CFG_DDR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CFG_BLK_LEN_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CFG_RC_CC_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CFG_STOP_CLOCK BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CFG_CLK_ALWAYS_ON BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CFG_CHK_DS BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CFG_AUTO_CLK BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CFG_ERR_ABORT BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SD_EMMC_STATUS 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define STATUS_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define STATUS_DESC_BUSY BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define STATUS_DATI GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SD_EMMC_IRQ_EN 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IRQ_RXD_ERR_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IRQ_TXD_ERR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IRQ_DESC_ERR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IRQ_RESP_ERR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IRQ_CRC_ERR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IRQ_RESP_TIMEOUT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IRQ_DESC_TIMEOUT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IRQ_TIMEOUTS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IRQ_END_OF_CHAIN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IRQ_RESP_STATUS BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IRQ_SDIO BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IRQ_EN_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) IRQ_SDIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SD_EMMC_CMD_CFG 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SD_EMMC_CMD_ARG 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SD_EMMC_CMD_DAT 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SD_EMMC_CMD_RSP 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SD_EMMC_CMD_RSP1 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SD_EMMC_CMD_RSP2 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SD_EMMC_CMD_RSP3 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SD_EMMC_RXD 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SD_EMMC_TXD 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SD_EMMC_LAST_REG SD_EMMC_TXD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SD_EMMC_SRAM_DATA_BUF_LEN 1536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SD_EMMC_SRAM_DATA_BUF_OFF 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SD_EMMC_PRE_REQ_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SD_EMMC_DESC_CHAIN_MODE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MUX_CLK_NUM_PARENTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct meson_mmc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int tx_delay_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int rx_delay_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int always_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct sd_emmc_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 cmd_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 cmd_arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 cmd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 cmd_resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct meson_host {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct meson_mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct mmc_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct clk *core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct clk *mux_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct clk *mmc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned long req_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) bool ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bool dram_access_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct pinctrl_state *pins_clk_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int bounce_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void *bounce_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void __iomem *bounce_iomem_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dma_addr_t bounce_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct sd_emmc_desc *descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dma_addr_t descs_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) bool vqmmc_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) bool needs_pre_post_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CMD_CFG_BLOCK_MODE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CMD_CFG_R1B BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CMD_CFG_END_OF_CHAIN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CMD_CFG_NO_RESP BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CMD_CFG_NO_CMD BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CMD_CFG_DATA_IO BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CMD_CFG_DATA_WR BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CMD_CFG_RESP_NOCRC BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CMD_CFG_RESP_128 BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CMD_CFG_RESP_NUM BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CMD_CFG_DATA_NUM BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CMD_CFG_ERROR BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CMD_CFG_OWNER BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CMD_DATA_MASK GENMASK(31, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CMD_DATA_BIG_ENDIAN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CMD_DATA_SRAM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CMD_RESP_MASK GENMASK(31, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CMD_RESP_SRAM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return SD_EMMC_CMD_TIMEOUT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) timeout = roundup_pow_of_two(timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return min(timeout, 32768U); /* max. 2^15 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return cmd->mrq->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) else if (mmc_op_multi(cmd->opcode) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) (!cmd->mrq->sbc || cmd->error || cmd->data->error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return cmd->mrq->stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct meson_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct mmc_data *data = mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) bool use_desc_chain_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * When Controller DMA cannot directly access DDR memory, disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * support for Chain Mode to directly use the internal SRAM using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * the bounce buffer mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (host->dram_access_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * reported. For some strange reason this occurs in descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * chain mode only. So let's fall back to bounce buffer mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * for command SD_IO_RW_EXTENDED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (mrq->cmd->opcode == SD_IO_RW_EXTENDED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) for_each_sg(data->sg, sg, data->sg_len, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* check for 8 byte alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (sg->offset & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) WARN_ONCE(1, "unaligned scatterlist buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) use_desc_chain_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (use_desc_chain_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return data && data->flags & MMC_DATA_READ &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) !meson_mmc_desc_chain_mode(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct mmc_data *data = mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) meson_mmc_get_transfer_mode(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!meson_mmc_desc_chain_mode(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!data->sg_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev_err(mmc_dev(mmc), "dma_map_sg failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct mmc_data *data = mrq->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mmc_get_dma_dir(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * Gating the clock on this controller is tricky. It seems the mmc clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * is also used by the controller. It may crash during some operation if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * clock is stopped. The safest thing to do, whenever possible, is to keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * clock running at stop it at the pad using the pinmux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static void meson_mmc_clk_gate(struct meson_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (host->pins_clk_gate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * If the pinmux is not provided - default to the classic and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * unsafe method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) cfg = readl(host->regs + SD_EMMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) cfg |= CFG_STOP_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) writel(cfg, host->regs + SD_EMMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void meson_mmc_clk_ungate(struct meson_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (host->pins_clk_gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pinctrl_select_default_state(host->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Make sure the clock is not stopped in the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) cfg = readl(host->regs + SD_EMMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) cfg &= ~CFG_STOP_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) writel(cfg, host->regs + SD_EMMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bool ddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct mmc_host *mmc = host->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Same request - bail-out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (host->ddr == ddr && host->req_rate == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* stop clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) meson_mmc_clk_gate(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) host->req_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mmc->actual_clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* return with clock being stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Stop the clock during rate change to avoid glitches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) cfg = readl(host->regs + SD_EMMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) cfg |= CFG_STOP_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writel(cfg, host->regs + SD_EMMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (ddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* DDR modes require higher module clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) rate <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) cfg |= CFG_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) cfg &= ~CFG_DDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) writel(cfg, host->regs + SD_EMMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) host->ddr = ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = clk_set_rate(host->mmc_clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) rate, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) host->req_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mmc->actual_clock = clk_get_rate(host->mmc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* We should report the real output frequency of the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (ddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) host->req_rate >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) mmc->actual_clock >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (rate != mmc->actual_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_dbg(host->dev, "requested rate was %lu\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* (re)start clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) meson_mmc_clk_ungate(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * The SD/eMMC IP block has an internal mux and divider used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * generating the MMC clock. Use the clock framework to create and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * manage these clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int meson_mmc_clk_init(struct meson_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct clk_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct clk_divider *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) char clk_name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) const char *clk_parent[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 clk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) clk_reg = CLK_ALWAYS_ON(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) clk_reg |= CLK_DIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) writel(clk_reg, host->regs + SD_EMMC_CLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* get the mux parents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) char name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) snprintf(name, sizeof(name), "clkin%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) clk = devm_clk_get(host->dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return dev_err_probe(host->dev, PTR_ERR(clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "Missing clock %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) mux_parent_names[i] = __clk_get_name(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* create the mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) init.name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) init.ops = &clk_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) init.parent_names = mux_parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) init.num_parents = MUX_CLK_NUM_PARENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mux->reg = host->regs + SD_EMMC_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) mux->shift = __ffs(CLK_SRC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mux->mask = CLK_SRC_MASK >> mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) mux->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) host->mux_clk = devm_clk_register(host->dev, &mux->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (WARN_ON(IS_ERR(host->mux_clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return PTR_ERR(host->mux_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* create the divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (!div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) init.name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) init.ops = &clk_divider_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) clk_parent[0] = __clk_get_name(host->mux_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) init.parent_names = clk_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) div->reg = host->regs + SD_EMMC_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) div->shift = __ffs(CLK_DIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) div->width = __builtin_popcountl(CLK_DIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) div->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) div->flags = CLK_DIVIDER_ONE_BASED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) host->mmc_clk = devm_clk_register(host->dev, &div->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (WARN_ON(IS_ERR(host->mmc_clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return PTR_ERR(host->mmc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return clk_prepare_enable(host->mmc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static void meson_mmc_disable_resampling(struct meson_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) unsigned int val = readl(host->regs + host->data->adjust);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) val &= ~ADJUST_ADJ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) writel(val, host->regs + host->data->adjust);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static void meson_mmc_reset_resampling(struct meson_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) meson_mmc_disable_resampling(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) val = readl(host->regs + host->data->adjust);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) val &= ~ADJUST_ADJ_DELAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) writel(val, host->regs + host->data->adjust);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct meson_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) unsigned int val, dly, max_dly, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Resampling is done using the source clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) clk_get_rate(host->mmc_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) val = readl(host->regs + host->data->adjust);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) val |= ADJUST_ADJ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) writel(val, host->regs + host->data->adjust);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (mmc_doing_retune(mmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dly = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) for (i = 0; i < max_dly; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) val &= ~ADJUST_ADJ_DELAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) writel(val, host->regs + host->data->adjust);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = mmc_send_tuning(mmc, opcode, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev_dbg(mmc_dev(mmc), "resampling delay: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) (dly + i) % max_dly);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) meson_mmc_reset_resampling(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int meson_mmc_prepare_ios_clock(struct meson_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) bool ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) switch (ios->timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case MMC_TIMING_MMC_DDR52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case MMC_TIMING_UHS_DDR50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ddr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ddr = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return meson_mmc_clk_set(host, ios->clock, ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static void meson_mmc_check_resampling(struct meson_host *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) switch (ios->timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case MMC_TIMING_LEGACY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case MMC_TIMING_MMC_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case MMC_TIMING_SD_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case MMC_TIMING_MMC_DDR52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) meson_mmc_disable_resampling(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct meson_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 bus_width, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * GPIO regulator, only controls switching between 1v8 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) switch (ios->power_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case MMC_POWER_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (!IS_ERR(mmc->supply.vmmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) regulator_disable(mmc->supply.vqmmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) host->vqmmc_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) case MMC_POWER_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (!IS_ERR(mmc->supply.vmmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) case MMC_POWER_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int ret = regulator_enable(mmc->supply.vqmmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dev_err(host->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) "failed to enable vqmmc regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) host->vqmmc_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) switch (ios->bus_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) case MMC_BUS_WIDTH_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) bus_width = CFG_BUS_WIDTH_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) case MMC_BUS_WIDTH_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) bus_width = CFG_BUS_WIDTH_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) case MMC_BUS_WIDTH_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) bus_width = CFG_BUS_WIDTH_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ios->bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) bus_width = CFG_BUS_WIDTH_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) val = readl(host->regs + SD_EMMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) val &= ~CFG_BUS_WIDTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) writel(val, host->regs + SD_EMMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) meson_mmc_check_resampling(host, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) err = meson_mmc_prepare_ios_clock(host, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_err(host->dev, "Failed to set clock: %d\n,", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static void meson_mmc_request_done(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct meson_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) host->cmd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (host->needs_pre_post_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) meson_mmc_post_req(mmc, mrq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) mmc_request_done(host->mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct meson_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 cfg, blksz_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) cfg = readl(host->regs + SD_EMMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (!is_power_of_2(blksz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) blksz = ilog2(blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* check if block-size matches, if not update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (blksz == blksz_old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) blksz_old, blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) cfg &= ~CFG_BLK_LEN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) writel(cfg, host->regs + SD_EMMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (cmd->flags & MMC_RSP_136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) *cmd_cfg |= CMD_CFG_RESP_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) *cmd_cfg |= CMD_CFG_RESP_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (!(cmd->flags & MMC_RSP_CRC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) *cmd_cfg |= CMD_CFG_RESP_NOCRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (cmd->flags & MMC_RSP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) *cmd_cfg |= CMD_CFG_R1B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) *cmd_cfg |= CMD_CFG_NO_RESP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct meson_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct sd_emmc_desc *desc = host->descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct mmc_data *data = host->cmd->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (data->flags & MMC_DATA_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) cmd_cfg |= CMD_CFG_DATA_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (data->blocks > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) cmd_cfg |= CMD_CFG_BLOCK_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) meson_mmc_set_blksz(mmc, data->blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) for_each_sg(data->sg, sg, data->sg_count, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) unsigned int len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (data->blocks > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) len /= data->blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) desc[i].cmd_cfg = cmd_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (i > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) desc[i].cmd_arg = host->cmd->arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) desc[i].cmd_resp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) desc[i].cmd_data = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dma_wmb(); /* ensure descriptor is written before kicked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) start = host->descs_dma_addr | START_DESC_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) writel(start, host->regs + SD_EMMC_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* local sg copy for dram_access_quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) size_t buflen, bool to_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) unsigned int sg_flags = SG_MITER_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct scatterlist *sgl = data->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) unsigned int nents = data->sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct sg_mapping_iter miter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) unsigned int offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (to_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) sg_flags |= SG_MITER_FROM_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) sg_flags |= SG_MITER_TO_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) sg_miter_start(&miter, sgl, nents, sg_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) while ((offset < buflen) && sg_miter_next(&miter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) unsigned int buf_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) unsigned int len, left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u32 *buf = miter.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) len = min(miter.length, buflen - offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) left = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (to_buffer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) writel(*buf++, host->bounce_iomem_buf + offset + buf_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) buf_offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) left -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) } while (left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) *buf++ = readl(host->bounce_iomem_buf + offset + buf_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) buf_offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) left -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) } while (left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) offset += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) sg_miter_stop(&miter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct meson_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct mmc_data *data = cmd->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u32 cmd_cfg = 0, cmd_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) unsigned int xfer_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* Setup descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dma_rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) host->cmd = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) meson_mmc_set_response_bits(cmd, &cmd_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* data? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) data->bytes_xfered = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) cmd_cfg |= CMD_CFG_DATA_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ilog2(meson_mmc_get_timeout_msecs(data)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (meson_mmc_desc_chain_mode(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (data->blocks > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) cmd_cfg |= CMD_CFG_BLOCK_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) data->blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) meson_mmc_set_blksz(mmc, data->blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) xfer_bytes = data->blksz * data->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (data->flags & MMC_DATA_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) cmd_cfg |= CMD_CFG_DATA_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) WARN_ON(xfer_bytes > host->bounce_buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (host->dram_access_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) meson_mmc_copy_buffer(host, data, xfer_bytes, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) sg_copy_to_buffer(data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) host->bounce_buf, xfer_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dma_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ilog2(SD_EMMC_CMD_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* Last descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) cmd_cfg |= CMD_CFG_END_OF_CHAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) writel(0, host->regs + SD_EMMC_CMD_RSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) wmb(); /* ensure descriptor is written before kicked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int meson_mmc_validate_dram_access(struct mmc_host *mmc, struct mmc_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* Reject request if any element offset or size is not 32bit aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) for_each_sg(data->sg, sg, data->sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) !IS_ALIGNED(sg->length, sizeof(u32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) dev_err(mmc_dev(mmc), "unaligned sg offset %u len %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) data->sg->offset, data->sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct meson_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) host->needs_pre_post_req = mrq->data &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * The memory at the end of the controller used as bounce buffer for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * the dram_access_quirk only accepts 32bit read/write access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * check the aligment and length of the data before starting the request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (host->dram_access_quirk && mrq->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (mrq->cmd->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) mmc_request_done(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (host->needs_pre_post_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) meson_mmc_get_transfer_mode(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (!meson_mmc_desc_chain_mode(mrq->data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) host->needs_pre_post_req = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (host->needs_pre_post_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) meson_mmc_pre_req(mmc, mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* Stop execution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) writel(0, host->regs + SD_EMMC_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct meson_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (cmd->flags & MMC_RSP_136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) } else if (cmd->flags & MMC_RSP_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct meson_host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct mmc_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u32 irq_en, status, raw_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) raw_status = readl(host->regs + SD_EMMC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) status = raw_status & irq_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (!status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) dev_dbg(host->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) irq_en, raw_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (WARN_ON(!host) || WARN_ON(!host->cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* ack all raised interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) writel(status, host->regs + SD_EMMC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) cmd = host->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) data = cmd->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) cmd->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (status & IRQ_CRC_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) cmd->error = -EILSEQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (status & IRQ_TIMEOUTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) cmd->error = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) meson_mmc_read_resp(host->mmc, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (status & IRQ_SDIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dev_dbg(host->dev, "IRQ: SDIO TODO.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (data && !cmd->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) data->bytes_xfered = data->blksz * data->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (meson_mmc_bounce_buf_read(data) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) meson_mmc_get_next_command(cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (cmd->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* Stop desc in case of errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u32 start = readl(host->regs + SD_EMMC_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) start &= ~START_DESC_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) writel(start, host->regs + SD_EMMC_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (ret == IRQ_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) meson_mmc_request_done(host->mmc, cmd->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static int meson_mmc_wait_desc_stop(struct meson_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * It may sometimes take a while for it to actually halt. Here, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * are giving it 5ms to comply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * If we don't confirm the descriptor is stopped, it might raise new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * IRQs after we have called mmc_request_done() which is bad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) !(status & (STATUS_BUSY | STATUS_DESC_BUSY)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) 100, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct meson_host *host = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct mmc_command *next_cmd, *cmd = host->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) unsigned int xfer_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (WARN_ON(!cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (cmd->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) meson_mmc_wait_desc_stop(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) meson_mmc_request_done(host->mmc, cmd->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) data = cmd->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (meson_mmc_bounce_buf_read(data)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) xfer_bytes = data->blksz * data->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) WARN_ON(xfer_bytes > host->bounce_buf_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (host->dram_access_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) meson_mmc_copy_buffer(host, data, xfer_bytes, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) sg_copy_from_buffer(data->sg, data->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) host->bounce_buf, xfer_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) next_cmd = meson_mmc_get_next_command(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (next_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) meson_mmc_start_cmd(host->mmc, next_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) meson_mmc_request_done(host->mmc, cmd->mrq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * NOTE: we only need this until the GPIO/pinctrl driver can handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * interrupts. For now, the MMC core will use this for polling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static int meson_mmc_get_cd(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) int status = mmc_gpio_get_cd(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (status == -ENOSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return 1; /* assume present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static void meson_mmc_cfg_init(struct meson_host *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) u32 cfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* abort chain on R/W errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) cfg |= CFG_ERR_ABORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) writel(cfg, host->regs + SD_EMMC_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static int meson_mmc_card_busy(struct mmc_host *mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct meson_host *host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) regval = readl(host->regs + SD_EMMC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /* We are only interrested in lines 0 to 3, so mask the other ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* vqmmc regulator is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (!IS_ERR(mmc->supply.vqmmc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * The usual amlogic setup uses a GPIO to switch from one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * regulator to the other. While the voltage ramp up is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * pretty fast, care must be taken when switching from 3.3v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * to 1.8v. Please make sure the regulator framework is aware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * of your own regulator constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ret = mmc_regulator_set_vqmmc(mmc, ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return ret < 0 ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static const struct mmc_host_ops meson_mmc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .request = meson_mmc_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .set_ios = meson_mmc_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .get_cd = meson_mmc_get_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .pre_req = meson_mmc_pre_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .post_req = meson_mmc_post_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .execute_tuning = meson_mmc_resampling_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .card_busy = meson_mmc_card_busy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .start_signal_voltage_switch = meson_mmc_voltage_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static int meson_mmc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) struct meson_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (!mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) host = mmc_priv(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) host->mmc = mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) host->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dev_set_drvdata(&pdev->dev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* The G12A SDIO Controller needs an SRAM bounce buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) host->dram_access_quirk = device_property_read_bool(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) "amlogic,dram-access-quirk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* Get regulators and the supported OCR mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) host->vqmmc_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ret = mmc_regulator_get_supply(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) goto free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ret = mmc_of_parse(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) goto free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) host->data = (struct meson_mmc_data *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (!host->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) goto free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ret = device_reset_optional(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return dev_err_probe(&pdev->dev, ret, "device reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) host->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (IS_ERR(host->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ret = PTR_ERR(host->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) goto free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) host->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (host->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) goto free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) host->pinctrl = devm_pinctrl_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (IS_ERR(host->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ret = PTR_ERR(host->pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) goto free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) "clk-gate");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (IS_ERR(host->pins_clk_gate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) "can't get clk-gate pinctrl, using clk_stop bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) host->pins_clk_gate = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) host->core_clk = devm_clk_get(&pdev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (IS_ERR(host->core_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ret = PTR_ERR(host->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) goto free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ret = clk_prepare_enable(host->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) goto free_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ret = meson_mmc_clk_init(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) goto err_core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /* set config to sane default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) meson_mmc_cfg_init(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* Stop execution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) writel(0, host->regs + SD_EMMC_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /* clear, ack and enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) writel(0, host->regs + SD_EMMC_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) host->regs + SD_EMMC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) host->regs + SD_EMMC_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ret = request_threaded_irq(host->irq, meson_mmc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) meson_mmc_irq_thread, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dev_name(&pdev->dev), host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) goto err_init_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) mmc->caps |= MMC_CAP_CMD23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (host->dram_access_quirk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* Limit segments to 1 due to low available sram memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) mmc->max_segs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* Limit to the available sram memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) mmc->max_blk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) mmc->max_segs = SD_EMMC_DESC_BUF_LEN /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) sizeof(struct sd_emmc_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) mmc->max_seg_size = mmc->max_req_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * At the moment, we don't know how to reliably enable HS400.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * From the different datasheets, it is not even clear if this mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * is officially supported by any of the SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) mmc->caps2 &= ~MMC_CAP2_HS400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (host->dram_access_quirk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * The MMC Controller embeds 1,5KiB of internal SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * that can be used to be used as bounce buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * In the case of the G12A SDIO controller, use these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * instead of the DDR memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /* data bounce buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) host->bounce_buf_size = mmc->max_req_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) host->bounce_buf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) dma_alloc_coherent(host->dev, host->bounce_buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) &host->bounce_dma_addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (host->bounce_buf == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) goto err_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) &host->descs_dma_addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (!host->descs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) goto err_bounce_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) mmc->ops = &meson_mmc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) mmc_add_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) err_bounce_buf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (!host->dram_access_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) dma_free_coherent(host->dev, host->bounce_buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) host->bounce_buf, host->bounce_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) err_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) free_irq(host->irq, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) err_init_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) clk_disable_unprepare(host->mmc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) err_core_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) clk_disable_unprepare(host->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) free_host:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) mmc_free_host(mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static int meson_mmc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct meson_host *host = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) mmc_remove_host(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) writel(0, host->regs + SD_EMMC_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) free_irq(host->irq, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) host->descs, host->descs_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (!host->dram_access_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) dma_free_coherent(host->dev, host->bounce_buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) host->bounce_buf, host->bounce_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) clk_disable_unprepare(host->mmc_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) clk_disable_unprepare(host->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) mmc_free_host(host->mmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) static const struct meson_mmc_data meson_gx_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .tx_delay_mask = CLK_V2_TX_DELAY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .rx_delay_mask = CLK_V2_RX_DELAY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .always_on = CLK_V2_ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .adjust = SD_EMMC_ADJUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static const struct meson_mmc_data meson_axg_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .tx_delay_mask = CLK_V3_TX_DELAY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .rx_delay_mask = CLK_V3_RX_DELAY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .always_on = CLK_V3_ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .adjust = SD_EMMC_V3_ADJUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static const struct of_device_id meson_mmc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static struct platform_driver meson_mmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .probe = meson_mmc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .remove = meson_mmc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .of_match_table = of_match_ptr(meson_mmc_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) module_platform_driver(meson_mmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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