^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Synopsys DesignWare Multimedia Card Interface driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (Based on NXP driver for lpc 31xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009 NXP Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _DW_MMC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _DW_MMC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mmc/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) enum dw_mci_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) STATE_IDLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) STATE_SENDING_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) STATE_SENDING_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) STATE_DATA_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) STATE_SENDING_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) STATE_DATA_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) STATE_SENDING_CMD11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) STATE_WAITING_CMD11_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) EVENT_CMD_COMPLETE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) EVENT_XFER_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) EVENT_DATA_COMPLETE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) EVENT_DATA_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum dw_mci_cookie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) COOKIE_UNMAPPED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct mmc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) TRANS_MODE_PIO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) TRANS_MODE_IDMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) TRANS_MODE_EDMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct dw_mci_dma_slave {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct dma_chan *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum dma_transfer_direction direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * struct dw_mci - MMC controller state shared between all slots
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @lock: Spinlock protecting the queue and associated data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @irq_lock: Spinlock protecting the INTMASK setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @regs: Pointer to MMIO registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @fifo_reg: Pointer to MMIO registers for data FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @sg: Scatterlist entry currently being processed by PIO code, if any.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @sg_miter: PIO mapping scatterlist iterator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @mrq: The request currently being processed on @slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * or NULL if the controller is idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @cmd: The command currently being sent to the card, or NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @data: The data currently being transferred, or NULL if no data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * transfer is in progress.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @stop_abort: The command currently prepared for stoping transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @prev_blksz: The former transfer blksz record.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @timing: Record of current ios timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @use_dma: Which DMA channel is in use for the current transfer, zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * denotes PIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @using_dma: Whether DMA is in use for the current transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @sg_dma: Bus address of DMA buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @sg_cpu: Virtual address of DMA buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @dma_ops: Pointer to platform-specific DMA callbacks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @cmd_status: Snapshot of SR taken upon completion of the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @ring_size: Buffer size for idma descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * command. Only valid when EVENT_CMD_COMPLETE is pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @dms: structure of slave-dma private data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @phy_regs: physical address of controller's register map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @data_status: Snapshot of SR taken upon completion of the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * data transfer. Only valid when EVENT_DATA_COMPLETE or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * EVENT_DATA_ERROR is pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @stop_cmdr: Value to be loaded into CMDR when the stop command is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * to be sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @dir_status: Direction of current transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @tasklet: Tasklet running the request state machine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @pending_events: Bitmask of events flagged by the interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * to be processed by the tasklet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @completed_events: Bitmask of events which the state machine has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * processed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @state: Tasklet state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @queue: List of slots waiting for access to the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * rate and timeout calculations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @current_speed: Configured rate of the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @fifoth_val: The value of FIFOTH register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @verid: Denote Version ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @dev: Device associated with the MMC controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @pdata: Platform data associated with the MMC controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @drv_data: Driver specific data for identified variant of the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @priv: Implementation defined private data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @biu_clk: Pointer to bus interface unit clock instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @ciu_clk: Pointer to card interface unit clock instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @slot: Slots sharing this MMC controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @fifo_depth: depth of FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @data_addr_override: override fifo reg offset with this value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @wm_aligned: force fifo watermark equal with data length in PIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Set as true if alignment is needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @data_shift: log2 of FIFO item size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @part_buf_start: Start index in part_buf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @part_buf_count: Bytes of partial data in part_buf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @part_buf: Simple buffer for partial fifo reads/writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @push_data: Pointer to FIFO push function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @pull_data: Pointer to FIFO pull function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @vqmmc_enabled: Status of vqmmc, should be true or false.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @irq_flags: The flags to be passed to request_irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @irq: The irq value to be passed to request_irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @sdio_id0: Number of slot0 in the SDIO interrupt registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @cto_timer: Timer for broken command transfer over scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @dto_timer: Timer for broken data transfer over scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Locking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * =======
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @lock is a softirq-safe spinlock protecting @queue as well as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @slot, @mrq and @state. These must always be updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * at the same time while holding @lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * The @mrq field of struct dw_mci_slot is also protected by @lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * and must always be written at the same time as the slot is added to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @irq_lock is an irq-safe spinlock protecting the INTMASK register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * to allow the interrupt handler to modify it directly. Held for only long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * enough to read-modify-write INTMASK and no other locks are grabbed when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * holding this one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @pending_events and @completed_events are accessed using atomic bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * operations, so they don't need any locking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * None of the fields touched by the interrupt handler need any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * locking. However, ordering is important: Before EVENT_DATA_ERROR or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * interrupts must be disabled and @data_status updated with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * CMDRDY interrupt must be disabled and @cmd_status updated with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * bytes_xfered field of @data must be written. This is ensured by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * using barriers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct dw_mci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) spinlock_t irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void __iomem *fifo_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 data_addr_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bool wm_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct sg_mapping_iter sg_miter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct mmc_command *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct mmc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct mmc_command stop_abort;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned int prev_blksz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned char timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* DMA interface members*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int use_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int using_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int dma_64bit_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dma_addr_t sg_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void *sg_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) const struct dw_mci_dma_ops *dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* For idmac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned int ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* For edmac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct dw_mci_dma_slave *dms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Registers's physical base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) resource_size_t phy_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 cmd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 data_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 stop_cmdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 dir_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct tasklet_struct tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned long pending_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned long completed_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) enum dw_mci_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 bus_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 current_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 fifoth_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u16 verid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct dw_mci_board *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) const struct dw_mci_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct clk *biu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct clk *ciu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct dw_mci_slot *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* FIFO push and pull */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int data_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u8 part_buf_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 part_buf_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u16 part_buf16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 part_buf32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u64 part_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void (*push_data)(struct dw_mci *host, void *buf, int cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) bool vqmmc_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long irq_flags; /* IRQ flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int sdio_id0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct timer_list cmd11_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct timer_list cto_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct timer_list dto_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) bool need_xfer_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct timer_list xfer_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) bool is_rv1106_sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* DMA ops for Internal/External DMAC interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct dw_mci_dma_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* DMA Ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int (*init)(struct dw_mci *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int (*start)(struct dw_mci *host, unsigned int sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) void (*complete)(void *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void (*stop)(struct dw_mci *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void (*cleanup)(struct dw_mci *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) void (*exit)(struct dw_mci *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct dma_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Board platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct dw_mci_board {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned int bus_hz; /* Clock speed at the cclk_in pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 caps; /* Capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 caps2; /* More capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 pm_caps; /* PM capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * Override fifo depth. If 0, autodetect it from the FIFOTH register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * but note that this may not be reliable after a bootloader has used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int fifo_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* delay in mS before detecting cards after interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 detect_delay_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct dw_mci_dma_ops *dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct dma_pdata *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DW_MMC_240A 0x240a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DW_MMC_280A 0x280a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SDMMC_CTRL 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SDMMC_PWREN 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SDMMC_CLKDIV 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SDMMC_CLKSRC 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SDMMC_CLKENA 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SDMMC_TMOUT 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SDMMC_CTYPE 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SDMMC_BLKSIZ 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SDMMC_BYTCNT 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SDMMC_INTMASK 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SDMMC_CMDARG 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SDMMC_CMD 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SDMMC_RESP0 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define SDMMC_RESP1 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SDMMC_RESP2 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SDMMC_RESP3 0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SDMMC_MINTSTS 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SDMMC_RINTSTS 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SDMMC_STATUS 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SDMMC_FIFOTH 0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SDMMC_CDETECT 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SDMMC_WRTPRT 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SDMMC_GPIO 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SDMMC_TCBCNT 0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define SDMMC_TBBCNT 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SDMMC_DEBNCE 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define SDMMC_USRID 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SDMMC_VERID 0x06c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SDMMC_HCON 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SDMMC_UHS_REG 0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SDMMC_RST_N 0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SDMMC_BMOD 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SDMMC_PLDMND 0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SDMMC_DBADDR 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SDMMC_IDSTS 0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SDMMC_IDINTEN 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SDMMC_DSCADDR 0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SDMMC_BUFADDR 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SDMMC_CDTHRCTL 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SDMMC_UHS_REG_EXT 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SDMMC_DDR_REG 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SDMMC_ENABLE_SHIFT 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SDMMC_DATA(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Registers to support idmac 64-bit address mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SDMMC_DBADDRL 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SDMMC_DBADDRU 0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SDMMC_IDSTS64 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SDMMC_IDINTEN64 0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SDMMC_DSCADDRL 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SDMMC_DSCADDRU 0x09c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SDMMC_BUFADDRL 0x0A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SDMMC_BUFADDRU 0x0A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Data offset is difference according to Version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Lower than 2.40a : data register offest is 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define DATA_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DATA_240A_OFFSET 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* shift bit field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define _SBF(f, v) ((v) << (f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Control register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SDMMC_CTRL_USE_IDMAC BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SDMMC_CTRL_SEND_CCSD BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SDMMC_CTRL_READ_WAIT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SDMMC_CTRL_DMA_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SDMMC_CTRL_INT_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SDMMC_CTRL_DMA_RESET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SDMMC_CTRL_FIFO_RESET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SDMMC_CTRL_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Clock Enable register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SDMMC_CLKEN_LOW_PWR BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SDMMC_CLKEN_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* time-out register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SDMMC_TMOUT_RESP_MSK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* card-type register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SDMMC_CTYPE_8BIT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SDMMC_CTYPE_4BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SDMMC_CTYPE_1BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Interrupt status & mask register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SDMMC_INT_SDIO(n) BIT(16 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SDMMC_INT_EBE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SDMMC_INT_ACD BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SDMMC_INT_SBE BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SDMMC_INT_HLE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SDMMC_INT_FRUN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SDMMC_INT_HTO BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SDMMC_INT_DRTO BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SDMMC_INT_RTO BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define SDMMC_INT_DCRC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SDMMC_INT_RCRC BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SDMMC_INT_RXDR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SDMMC_INT_TXDR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SDMMC_INT_DATA_OVER BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SDMMC_INT_CMD_DONE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SDMMC_INT_RESP_ERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SDMMC_INT_CD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SDMMC_INT_ERROR 0xbfc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Command register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SDMMC_CMD_START BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SDMMC_CMD_USE_HOLD_REG BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SDMMC_CMD_VOLT_SWITCH BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SDMMC_CMD_CCS_EXP BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SDMMC_CMD_CEATA_RD BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SDMMC_CMD_UPD_CLK BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SDMMC_CMD_INIT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SDMMC_CMD_STOP BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SDMMC_CMD_SEND_STOP BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SDMMC_CMD_STRM_MODE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SDMMC_CMD_DAT_WR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SDMMC_CMD_DAT_EXP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SDMMC_CMD_RESP_CRC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define SDMMC_CMD_RESP_LONG BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SDMMC_CMD_RESP_EXP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SDMMC_CMD_INDX(n) ((n) & 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* Status register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SDMMC_STATUS_DMA_REQ BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define SDMMC_STATUS_BUSY BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* FIFOTH register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ((r) & 0xFFF) << 16 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ((t) & 0xFFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* HCON register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define DMA_INTERFACE_IDMA (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define DMA_INTERFACE_DWDMA (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define DMA_INTERFACE_GDMA (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define DMA_INTERFACE_NODMA (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Internal DMAC interrupt defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SDMMC_IDMAC_INT_AI BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define SDMMC_IDMAC_INT_NI BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define SDMMC_IDMAC_INT_CES BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define SDMMC_IDMAC_INT_DU BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define SDMMC_IDMAC_INT_FBE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define SDMMC_IDMAC_INT_RI BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define SDMMC_IDMAC_INT_TI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Internal DMAC bus mode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define SDMMC_IDMAC_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define SDMMC_IDMAC_FB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define SDMMC_IDMAC_SWRESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* H/W reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define SDMMC_RST_HWACTIVE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Version ID register define */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Card read threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define SDMMC_CARD_WR_THR_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define SDMMC_CARD_RD_THR_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* UHS-1 register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SDMMC_UHS_DDR BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SDMMC_UHS_18V BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* DDR register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define SDMMC_DDR_HS400 BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Enable shift register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SDMMC_ENABLE_PHASE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* All ctrl reset bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SDMMC_CTRL_ALL_RESET_FLAGS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* FIFO register access macros. These should not change the data endian-ness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * as they are written to memory to be dealt with by the upper layers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define mci_fifo_readw(__reg) __raw_readw(__reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define mci_fifo_readl(__reg) __raw_readl(__reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define mci_fifo_readq(__reg) __raw_readq(__reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Register access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define mci_readl(dev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) readl_relaxed((dev)->regs + SDMMC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define mci_writel(dev, reg, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) writel_relaxed((value), (dev)->regs + SDMMC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* 16-bit FIFO access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define mci_readw(dev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) readw_relaxed((dev)->regs + SDMMC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define mci_writew(dev, reg, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) writew_relaxed((value), (dev)->regs + SDMMC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* 64-bit FIFO access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #ifdef readq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define mci_readq(dev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) readq_relaxed((dev)->regs + SDMMC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define mci_writeq(dev, reg, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * Dummy readq implementation for architectures that don't define it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * We would assume that none of these architectures would configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * the IP block with a 64bit FIFO width, so this code will never be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * executed on those machines. Defining these macros here keeps the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * rest of the code free from ifdefs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define mci_readq(dev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define mci_writeq(dev, reg, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define __raw_writeq(__value, __reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) (*(volatile u64 __force *)(__reg) = (__value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) extern int dw_mci_probe(struct dw_mci *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) extern void dw_mci_remove(struct dw_mci *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) extern int dw_mci_runtime_suspend(struct device *device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) extern int dw_mci_runtime_resume(struct device *device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * struct dw_mci_slot - MMC slot state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * @mmc: The mmc_host representing this slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * @host: The MMC controller this slot is using.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * @ctype: Card type for this slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * @mrq: mmc_request currently being processed or waiting to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * processed, or NULL when the slot is idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * @queue_node: List node for placing this node in the @queue list of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * &struct dw_mci.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * @clock: Clock rate configured by set_ios(). Protected by host->lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * @__clk_old: The last clock value that was requested from core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * Keeping track of this helps us to avoid spamming the console.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * @flags: Random state bits associated with the slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * @id: Number of this slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * @sdio_id: Number of this slot in the SDIO interrupt registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct dw_mci_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct mmc_host *mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct dw_mci *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 ctype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct mmc_request *mrq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct list_head queue_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) unsigned int clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned int __clk_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define DW_MMC_CARD_PRESENT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define DW_MMC_CARD_NEED_INIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define DW_MMC_CARD_NO_LOW_PWR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define DW_MMC_CARD_NO_USE_HOLD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define DW_MMC_CARD_NEEDS_POLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int sdio_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * dw_mci driver data - dw-mshc implementation specific driver data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * @caps: mmc subsystem specified capabilities of the controller(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * @num_caps: number of capabilities specified by @caps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * @init: early implementation specific initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * @set_ios: handle bus specific extensions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * @parse_dt: parse implementation specific device tree properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * @execute_tuning: implementation specific tuning procedure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * Provide controller implementation specific extensions. The usage of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * data structure is fully optional and usage of each member in this structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * is optional as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct dw_mci_drv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned long *caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 num_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int (*init)(struct dw_mci *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int (*parse_dt)(struct dw_mci *host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int (*prepare_hs400_tuning)(struct dw_mci *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct mmc_ios *ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int (*switch_voltage)(struct mmc_host *mmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct mmc_ios *ios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #endif /* _DW_MMC_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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