Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _DW_MMC_ZX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _DW_MMC_ZX_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /* ZX296718 SoC specific DLL register offset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define LB_AON_EMMC_CFG_REG0  0x1B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define LB_AON_EMMC_CFG_REG1  0x1B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define LB_AON_EMMC_CFG_REG2  0x1B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* LB_AON_EMMC_CFG_REG0 register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PARA_DLL_START(x)	((x) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PARA_DLL_START_MASK	0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DLL_REG_SET		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PARA_DLL_LOCK_NUM(x)	(((x) & 7) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PARA_DLL_LOCK_NUM_MASK  (7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PARA_PHASE_DET_SEL(x)	(((x) & 7) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PARA_PHASE_DET_SEL_MASK	(7 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PARA_DLL_BYPASS_MODE	BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PARA_HALF_CLK_MODE	BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* LB_AON_EMMC_CFG_REG1 register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define READ_DQS_DELAY(x)	((x) & 0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define READ_DQS_DELAY_MASK	(0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define READ_DQS_BYPASS_MODE	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_SAMP_DELAY(x)	(((x) & 0x7F) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_SAMP_DELAY_MASK	(0x7F << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_SAMP_BYPASS_MODE	BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* LB_AON_EMMC_CFG_REG2 register defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ZX_DLL_LOCKED		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif /* _DW_MMC_ZX_H_ */