^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ZX Specific Extensions for Synopsys DW Multimedia Card Interface driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016, Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2016, ZTE Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mmc/mmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "dw_mmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "dw_mmc-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "dw_mmc-zx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct dw_mci_zx_priv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct regmap *sysc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum delay_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DELAY_TYPE_READ, /* read dqs delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DELAY_TYPE_CLK, /* clk sample delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int dw_mci_zx_emmc_set_delay(struct dw_mci *host, unsigned int delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum delay_type dflag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct dw_mci_zx_priv_data *priv = host->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct regmap *sysc_base = priv->sysc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int clksel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int loop = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (!sysc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ret = regmap_update_bits(sysc_base, LB_AON_EMMC_CFG_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PARA_HALF_CLK_MODE | PARA_DLL_BYPASS_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PARA_PHASE_DET_SEL_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PARA_DLL_LOCK_NUM_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DLL_REG_SET | PARA_DLL_START_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PARA_DLL_START(4) | PARA_DLL_LOCK_NUM(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG1, &clksel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (dflag == DELAY_TYPE_CLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) clksel &= ~CLK_SAMP_DELAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) clksel |= CLK_SAMP_DELAY(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) clksel &= ~READ_DQS_DELAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clksel |= READ_DQS_DELAY(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) regmap_write(sysc_base, LB_AON_EMMC_CFG_REG1, clksel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) regmap_update_bits(sysc_base, LB_AON_EMMC_CFG_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PARA_DLL_START_MASK | PARA_DLL_LOCK_NUM_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DLL_REG_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PARA_DLL_START(4) | PARA_DLL_LOCK_NUM(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DLL_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG2, &clksel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) } while (--loop && !(clksel & ZX_DLL_LOCKED));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!loop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dev_err(host->dev, "Error: %s dll lock fail\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int dw_mci_zx_emmc_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct dw_mci *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct mmc_host *mmc = slot->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int ret, len = 0, start = 0, end = 0, delay, best = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) for (delay = 1; delay < 128; delay++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ret = dw_mci_zx_emmc_set_delay(host, delay, DELAY_TYPE_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!ret && mmc_send_tuning(mmc, opcode, NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (start >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) end = delay - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* check and update longest good range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if ((end - start) > len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) best = (start + end) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) len = end - start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) start = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (start < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) start = delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (start >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) end = delay - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if ((end - start) > len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) best = (start + end) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) len = end - start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (best < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_info(host->dev, "%s best range: start %d end %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return dw_mci_zx_emmc_set_delay(host, best, DELAY_TYPE_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int dw_mci_zx_prepare_hs400_tuning(struct dw_mci *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* config phase shift as 90 degree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = dw_mci_zx_emmc_set_delay(host, 32, DELAY_TYPE_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int dw_mci_zx_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct dw_mci *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (host->verid == 0x290a) /* only for emmc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return dw_mci_zx_emmc_execute_tuning(slot, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* TODO: Add 0x210a dedicated tuning for sd/sdio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int dw_mci_zx_parse_dt(struct dw_mci *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct device_node *np = host->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct dw_mci_zx_priv_data *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct regmap *sysc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* syscon is needed only by emmc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) node = of_parse_phandle(np, "zte,aon-syscon", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) sysc_base = syscon_node_to_regmap(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (IS_ERR(sysc_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return dev_err_probe(host->dev, PTR_ERR(sysc_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "Can't get syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) priv->sysc_base = sysc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) host->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static unsigned long zx_dwmmc_caps[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MMC_CAP_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MMC_CAP_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MMC_CAP_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct dw_mci_drv_data zx_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .caps = zx_dwmmc_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .num_caps = ARRAY_SIZE(zx_dwmmc_caps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .execute_tuning = dw_mci_zx_execute_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .prepare_hs400_tuning = dw_mci_zx_prepare_hs400_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .parse_dt = dw_mci_zx_parse_dt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct of_device_id dw_mci_zx_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { .compatible = "zte,zx296718-dw-mshc", .data = &zx_drv_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MODULE_DEVICE_TABLE(of, dw_mci_zx_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int dw_mci_zx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) const struct dw_mci_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) match = of_match_node(dw_mci_zx_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) drv_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return dw_mci_pltfm_register(pdev, drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct dev_pm_ops dw_mci_zx_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dw_mci_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct platform_driver dw_mci_zx_pltfm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .probe = dw_mci_zx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .remove = dw_mci_pltfm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .name = "dwmmc_zx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .of_match_table = dw_mci_zx_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .pm = &dw_mci_zx_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) module_platform_driver(dw_mci_zx_pltfm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MODULE_DESCRIPTION("ZTE emmc/sd driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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