^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mmc/slot-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/rockchip/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "dw_mmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "dw_mmc-pltfm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RK3288_CLKGEN_DIV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct dw_mci_rockchip_priv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk *drv_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk *sample_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int default_sample_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int num_phases;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) bool use_v2_tuning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int last_degree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 f_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct dw_mci_rockchip_priv_data *priv = host->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int cclkin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 bus_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (ios->clock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * cclkin: source clock of mmc controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * bus_hz: card interface clock generated by CLKGEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * bus_hz = cclkin / RK3288_CLKGEN_DIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Note: div can only be 0 or 1, but div must be set to 1 for eMMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * DDR52 8-bit mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (ios->clock < priv->f_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ios->clock = priv->f_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) host->slot->clock = ios->clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (ios->bus_width == MMC_BUS_WIDTH_8 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ios->timing == MMC_TIMING_MMC_DDR52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) cclkin = ios->clock * RK3288_CLKGEN_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ret = clk_set_rate(host->ciu_clk, cclkin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (bus_hz != host->bus_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) host->bus_hz = bus_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* force dw_mci_setup_bus() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) host->current_speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Make sure we use phases which we can enumerate with */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (!IS_ERR(priv->sample_clk) && ios->timing <= MMC_TIMING_SD_HS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) clk_set_phase(priv->sample_clk, priv->default_sample_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Set the drive phase offset based on speed mode to achieve hold times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * NOTE: this is _not_ a value that is dynamically tuned and is also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * _not_ a value that will vary from board to board. It is a value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * that could vary between different SoC models if they had massively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * different output clock delays inside their dw_mmc IP block (delay_o),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * but since it's OK to overshoot a little we don't need to do complex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * calculations and can pick values that will just work for everyone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * When picking values we'll stick with picking 0/90/180/270 since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * those can be made very accurately on all known Rockchip SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Note that these values match values from the DesignWare Databook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * tables for the most part except for SDR12 and "ID mode". For those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * two modes the databook calculations assume a clock in of 50MHz. As
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * seen above, we always use a clock in rate that is exactly the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * back out before the controller sees it).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * From measurement of a single device, it appears that delay_o is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * about .5 ns. Since we try to leave a bit of margin, it's expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * that numbers here will be fine even with much larger delay_o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * (the 1.4 ns assumed by the DesignWare Databook would result in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * same results, for instance).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (!IS_ERR(priv->drv_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * In almost all cases a 90 degree phase offset will provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * sufficient hold times across all valid input clock rates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * assuming delay_o is not absurd for a given SoC. We'll use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * that as a default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) phase = 90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) switch (ios->timing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case MMC_TIMING_MMC_DDR52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Since clock in rate with MMC_DDR52 is doubled when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * bus width is 8 we need to double the phase offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * to get the same timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (ios->bus_width == MMC_BUS_WIDTH_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) phase = 180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case MMC_TIMING_UHS_SDR104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case MMC_TIMING_MMC_HS200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * In the case of 150 MHz clock (typical max for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Rockchip SoCs), 90 degree offset will add a delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * of 1.67 ns. That will meet min hold time of .8 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * as long as clock output delay is < .87 ns. On
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * SoCs measured this seems to be OK, but it doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * hurt to give margin here, so we use 180.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) phase = 180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) clk_set_phase(priv->drv_clk, phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TUNING_ITERATION_TO_PHASE(i, num_phases) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (DIV_ROUND_UP((i) * 360, num_phases))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int dw_mci_v2_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct dw_mci *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct dw_mci_rockchip_priv_data *priv = host->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct mmc_host *mmc = slot->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 degrees[4] = {0, 90, 180, 270}, degree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static bool inherit = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (inherit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) inherit = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) i = clk_get_phase(priv->sample_clk) / 90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) degree = degrees[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * v2 only support 4 degrees in theory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * First we inherit sample phases from firmware, which should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * be able work fine, at least in the first place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * If retune is needed, we search forward to pick the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * one phase from degree list and loop around until we get one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * It's impossible all 4 fixed phase won't be able to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) for (i = 0; i < ARRAY_SIZE(degrees); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) degree = degrees[i] + priv->last_degree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) degree = degree % 360;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) clk_set_phase(priv->sample_clk, degree);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!mmc_send_tuning(mmc, opcode, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (i == ARRAY_SIZE(degrees)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_warn(host->dev, "All phases bad!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_info(host->dev, "Successfully tuned phase to %d\n", degrees[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) priv->last_degree = degree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct dw_mci *host = slot->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct dw_mci_rockchip_priv_data *priv = host->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct mmc_host *mmc = slot->mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bool v, prev_v = 0, first_v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct range_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int end; /* inclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct range_t *ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int range_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int longest_range_len = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int longest_range = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int middle_phase, real_middle_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (IS_ERR(priv->sample_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (priv->use_v2_tuning) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ret = dw_mci_v2_execute_tuning(slot, opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Otherwise we continue using fine tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ranges = kmalloc_array(priv->num_phases / 2 + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) sizeof(*ranges), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!ranges)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Try each phase and extract good ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) for (i = 0; i < priv->num_phases; ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Cannot guarantee any phases larger than 270 would work well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (TUNING_ITERATION_TO_PHASE(i, priv->num_phases) > 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) clk_set_phase(priv->sample_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) TUNING_ITERATION_TO_PHASE(i, priv->num_phases));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) v = !mmc_send_tuning(mmc, opcode, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) first_v = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if ((!prev_v) && v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) range_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ranges[range_count-1].start = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ranges[range_count-1].end = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) } else if (i == priv->num_phases - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* No extra skipping rules if we're at the end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * No need to check too close to an invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * one since testing bad phases is slow. Skip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * 20 degrees.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) i += DIV_ROUND_UP(20 * priv->num_phases, 360);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Always test the last one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (i >= priv->num_phases)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) i = priv->num_phases - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) prev_v = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (range_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_warn(host->dev, "All phases bad!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* wrap around case, merge the end points */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if ((range_count > 1) && first_v && v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ranges[0].start = ranges[range_count-1].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) range_count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) clk_set_phase(priv->sample_clk, priv->default_sample_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_info(host->dev, "All phases work, using default phase %d.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) priv->default_sample_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Find the longest range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) for (i = 0; i < range_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int len = (ranges[i].end - ranges[i].start + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (len < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) len += priv->num_phases;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (longest_range_len < len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) longest_range_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) longest_range = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) TUNING_ITERATION_TO_PHASE(ranges[i].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) priv->num_phases),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) TUNING_ITERATION_TO_PHASE(ranges[i].end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) priv->num_phases),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) TUNING_ITERATION_TO_PHASE(ranges[longest_range].start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) priv->num_phases),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) TUNING_ITERATION_TO_PHASE(ranges[longest_range].end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) priv->num_phases),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) longest_range_len
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) middle_phase = ranges[longest_range].start + longest_range_len / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) middle_phase %= priv->num_phases;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) real_middle_phase = TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Since we cut out 270 ~ 360, the original algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * still rolling ranges before and after 270 together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * in some corner cases, we should adjust it to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * using any middle phase located between 270 and 360.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * By calculatiion, it happends due to the bad phases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * lay between 90 ~ 180. So others are all fine to chose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Pick 270 is a better choice in those cases. In case of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * bad phases exceed 180, the middle phase of rollback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * would be bigger than 315, so we chose 360.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (real_middle_phase > 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (real_middle_phase < 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) real_middle_phase = 270;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) real_middle_phase = 360;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_info(host->dev, "Successfully tuned phase to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) real_middle_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) clk_set_phase(priv->sample_clk, real_middle_phase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) kfree(ranges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct device_node *np = host->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct dw_mci_rockchip_priv_data *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * RK356X SoCs only support 375KHz for ID mode, so any clk request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * that less than 1.6MHz(2 * 400KHz * RK3288_CLKGEN_DIV) should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * wrapped into 375KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (of_device_is_compatible(host->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "rockchip,rk3568-dw-mshc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) priv->f_min = 375000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) priv->f_min = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (of_property_read_u32(np, "rockchip,desired-num-phases",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) &priv->num_phases))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) priv->num_phases = 360;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (of_property_read_u32(np, "rockchip,default-sample-phase",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) &priv->default_sample_phase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) priv->default_sample_phase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (of_property_read_bool(np, "rockchip,use-v2-tuning"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) priv->use_v2_tuning = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (IS_ERR(priv->drv_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_dbg(host->dev, "ciu-drive not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (IS_ERR(priv->sample_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_dbg(host->dev, "ciu-sample not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) host->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int dw_mci_rockchip_init(struct dw_mci *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* It is slot 8 on Rockchip SoCs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) host->sdio_id0 = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (of_device_is_compatible(host->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "rockchip,rk3288-dw-mshc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) host->bus_hz /= RK3288_CLKGEN_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (of_device_is_compatible(host->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "rockchip,rv1106-dw-mshc") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) rockchip_get_cpu_version() == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) !strcmp(dev_name(host->dev), "ffaa0000.mmc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (device_property_read_bool(host->dev, "no-sd")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(host->dev, "Invalid usage, should be SD card only\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) host->is_rv1106_sd = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_info(host->dev, "is rv1106 sd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) host->need_xfer_timer = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Common capabilities of RK3288 SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MMC_CAP_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MMC_CAP_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MMC_CAP_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MMC_CAP_CMD23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const struct dw_mci_drv_data rk2928_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .init = dw_mci_rockchip_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const struct dw_mci_drv_data rk3288_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .caps = dw_mci_rk3288_dwmmc_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .num_caps = ARRAY_SIZE(dw_mci_rk3288_dwmmc_caps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .set_ios = dw_mci_rk3288_set_ios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .execute_tuning = dw_mci_rk3288_execute_tuning,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .parse_dt = dw_mci_rk3288_parse_dt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .init = dw_mci_rockchip_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const struct of_device_id dw_mci_rockchip_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { .compatible = "rockchip,rk2928-dw-mshc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .data = &rk2928_drv_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { .compatible = "rockchip,rk3288-dw-mshc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .data = &rk3288_drv_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int dw_mci_rockchip_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) const struct dw_mci_drv_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) bool use_rpm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (!device_property_read_bool(&pdev->dev, "non-removable") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) !device_property_read_bool(&pdev->dev, "cd-gpios"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) use_rpm = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) drv_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * increase rpm usage count in order to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * pm_runtime_force_resume calls rpm resume callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (use_rpm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = dw_mci_pltfm_register(pdev, drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (use_rpm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (use_rpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pm_runtime_put_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int dw_mci_rockchip_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return dw_mci_pltfm_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dw_mci_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static struct platform_driver dw_mci_rockchip_pltfm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .probe = dw_mci_rockchip_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .remove = dw_mci_rockchip_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .name = "dwmmc_rockchip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .of_match_table = dw_mci_rockchip_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .pm = &dw_mci_rockchip_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) module_platform_driver(dw_mci_rockchip_pltfm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MODULE_ALIAS("platform:dwmmc_rockchip");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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